backport: i386.c (ix86_data_alignment): Calculate max_align from prefetch_block tune...

	Backport from mainline
	2014-01-05  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.c (ix86_data_alignment): Calculate max_align
	from prefetch_block tune setting.
	(nocona_cost): Correct size of prefetch block to 64.

From-SVN: r206436

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 01c2c3aa3b5c3624b0d1ed7af0e58640d7175732..ceb019d8656829b35db77387838e524c9b1bda9d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2014-01-08  Uros Bizjak  <ubizjak@gmail.com>
+
+       Backport from mainline
+       2014-01-05  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.c (ix86_data_alignment): Calculate max_align
+       from prefetch_block tune setting.
+       (nocona_cost): Correct size of prefetch block to 64.
+
 2013-12-28  Eric Botcazou  <ebotcazou@adacore.com>
 
        * doc/invoke.texi (output file options): Add missing markers.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d7d013bec3358de6f77e87030006fb8c5ca31b34..63622abf78b3772495a50c35912b4a9ff01a76a6 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1623,7 +1623,7 @@ struct processor_costs nocona_cost = {
   8,                                   /* MMX or SSE register to integer */
   8,                                   /* size of l1 cache.  */
   1024,                                        /* size of l2 cache.  */
-  128,                                 /* size of prefetch block */
+  64,                                  /* size of prefetch block */
   8,                                   /* number of parallel prefetches */
   1,                                   /* Branch cost */
   COSTS_N_INSNS (6),                   /* cost of FADD and FSUB insns.  */
@@ -24266,7 +24266,16 @@ ix86_constant_alignment (tree exp, int align)
 int
 ix86_data_alignment (tree type, int align)
 {
-  int max_align = optimize_size ? BITS_PER_WORD : MIN (256, MAX_OFILE_ALIGNMENT);
+  /* A data structure, equal or greater than the size of a cache line
+     (64 bytes in the Pentium 4 and other recent Intel processors, including
+     processors based on Intel Core microarchitecture) should be aligned
+     so that its base address is a multiple of a cache line size.  */
+
+  int max_align
+    = MIN ((unsigned) ix86_cost->prefetch_block * 8, MAX_OFILE_ALIGNMENT);
+
+  if (max_align < BITS_PER_WORD)
+    max_align = BITS_PER_WORD;
 
   if (AGGREGATE_TYPE_P (type)
       && TYPE_SIZE (type)