soc: qcom: ubwc: disable bank swizzling for Glymur platform

Due to the way the DDR controller is organized on Glymur, hardware
engineers strongly recommended disabling UBWC bank swizzling on Glymur.
Follow that recommendation.

Fixes: 9b21c3bd2480 ("soc: qcom: ubwc: Add configuration Glymur platform")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Acked-by: Rob Clark <rob.clark@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Link: https://lore.kernel.org/r/20260228-fix-glymur-ubwc-v2-1-70819bd6a6b4@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 1c25aaf55e523a66268a5e34d5934248582dd01e..8304463f238a6e9e6e5b5d1df2ea912a6e5c575d 100644 (file)
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -231,8 +231,7 @@ static const struct qcom_ubwc_cfg_data x1e80100_data = {
 static const struct qcom_ubwc_cfg_data glymur_data = {
        .ubwc_enc_version = UBWC_5_0,
        .ubwc_dec_version = UBWC_5_0,
-       .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
-                       UBWC_SWIZZLE_ENABLE_LVL3,
+       .ubwc_swizzle = 0,
        .ubwc_bank_spread = true,
        /* TODO: highest_bank_bit = 15 for LP_DDR4 */
        .highest_bank_bit = 16,