i386.h (HARD_REGNO_RENAME_OK): Define.

	* i386.h (HARD_REGNO_RENAME_OK): Define.
	* i386.md (fop_?f_comm): Allow memory operand in both arms
	before reload.

From-SVN: r50144

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f922d01756a9b1ebb00230243edabaf839b64e0d..99924569a42e163cd11287d0a14d4bfbc8459847 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+Don Feb 28 16:46:03 CET 2002  Jan Hubicka  <jh@suse.cz>
+
+       * i386.h (HARD_REGNO_RENAME_OK): Define.
+       * i386.md (fop_?f_comm): Allow memory operand in both arms
+       before reload.
+
 2002-02-23  Zack Weinberg  <zack@codesourcery.com>
 
        * cppinit.c (merge_include_chains): Check for brack being

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 7471560fd09be2e5be2bfa19266f9dad3a198d0d..64abce202f56896a3b73167c867afab92abf23ce 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2939,6 +2939,15 @@ extern enum reg_class const regclass_map[];      /* smalled class containing REGNO */
 extern struct rtx_def *ix86_compare_op0;       /* operand 0 for comparisons */
 extern struct rtx_def *ix86_compare_op1;       /* operand 1 for comparisons */
 \f
+/* Avoid renaming of stack registers, as doing so in combination with
+   scheduling just increases amount of live registers at time and in
+   the turn amount of fxch instructions needed.
+
+   ??? Maybe Pentium chips benefits from renaming, someone can try...  */
+
+#define HARD_REGNO_RENAME_OK(SRC, TARGET)  \
+   ((SRC) < FIRST_STACK_REG || (SRC) > LAST_STACK_REG)
+\f
 /*
 Local variables:
 version-control: t

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 0816fa87c479acb92d5ad40209339212f6fa1e31..b84643b8d7ee37620e3a792fea3fa3507b95fac9 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10095,9 +10095,10 @@
 (define_insn "*fop_sf_comm"
   [(set (match_operand:SF 0 "register_operand" "=f")
        (match_operator:SF 3 "binary_fp_operator"
-                       [(match_operand:SF 1 "register_operand" "%0")
+                       [(match_operand:SF 1 "nonimmediate_operand" "%0")
                         (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
-  "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
+  "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (if_then_else (match_operand:SF 3 "mult_operator" "") 
@@ -10108,9 +10109,10 @@
 (define_insn "*fop_df_comm"
   [(set (match_operand:DF 0 "register_operand" "=f")
        (match_operator:DF 3 "binary_fp_operator"
-                       [(match_operand:DF 1 "register_operand" "%0")
+                       [(match_operand:DF 1 "nonimmediate_operand" "%0")
                         (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
-  "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
+  "TARGET_80387 && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (if_then_else (match_operand:DF 3 "mult_operator" "")