{
int ret, reg_value;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_FINISH);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_FINISH);
if (ret)
return ret;
int ret;
/* Configure CRC */
- ret = air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN,
- AN8811HB_CRC_RD_EN);
+ ret = air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ AN8811HB_CRC_RD_EN);
if (ret < 0)
return ret;
- air_buckpbus_reg_read(phydev, set1, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, set1, &pbus_value);
do {
msleep(300);
- air_buckpbus_reg_read(phydev, mon2, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon2, &pbus_value);
/* We do not know what errors this check is supposed
* catch or what to do about a failure. So print the
* result and continue like the vendor driver does.
*/
if (pbus_value & AN8811HB_CRC_ST) {
- air_buckpbus_reg_read(phydev, mon3, &pbus_value);
+ air_phy_buckpbus_reg_read(phydev, mon3, &pbus_value);
phydev_dbg(phydev, "CRC Check %s!\n",
pbus_value & AN8811HB_CRC_CHECK_PASS ?
"PASS" : "FAIL");
- return air_buckpbus_reg_modify(phydev, set1,
- AN8811HB_CRC_RD_EN, 0);
+ return air_phy_buckpbus_reg_modify(phydev, set1,
+ AN8811HB_CRC_RD_EN,
+ 0);
}
} while (--retry);
{
struct en8811h_priv *priv = phydev->priv;
- air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
- &priv->firmware_version);
+ air_phy_buckpbus_reg_read(phydev, EN8811H_FW_VERSION,
+ &priv->firmware_version);
phydev_info(phydev, "MD32 firmware version: %08x\n",
priv->firmware_version);
}
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
if (ret < 0)
goto en8811h_load_firmware_rel1;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING,
- EN8811H_FW_CTRL_2_LOADING);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING,
+ EN8811H_FW_CTRL_2_LOADING);
if (ret < 0)
goto en8811h_load_firmware_out;
if (ret < 0)
goto en8811h_load_firmware_out;
- ret = air_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
- EN8811H_FW_CTRL_2_LOADING, 0);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_FW_CTRL_2,
+ EN8811H_FW_CTRL_2_LOADING, 0);
if (ret < 0)
goto en8811h_load_firmware_out;
{
int ret;
- ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
- EN8811H_FW_CTRL_1_START);
+ ret = air_phy_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
+ EN8811H_FW_CTRL_1_START);
if (ret < 0)
return ret;
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_HWTRAP2, &pbus_value);
if (ret < 0)
return ret;
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK,
- AN8811HB_CLK_DRV_CKO_MASK);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK,
+ AN8811HB_CLK_DRV_CKO_MASK);
}
static void an8811hb_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
- AN8811HB_CLK_DRV_CKO_MASK, 0);
+ air_phy_buckpbus_reg_modify(phydev, AN8811HB_CLK_DRV,
+ AN8811HB_CLK_DRV_CKO_MASK, 0);
}
static int an8811hb_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, AN8811HB_CLK_DRV, &pbus_value);
if (ret < 0)
return ret;
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_HWTRAP1, &pbus_value);
if (ret < 0)
return ret;
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- return air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO,
- EN8811H_CLK_CGM_CKO);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO,
+ EN8811H_CLK_CGM_CKO);
}
static void en8811h_clk_disable(struct clk_hw *hw)
struct en8811h_priv *priv = clk_hw_to_en8811h_priv(hw);
struct phy_device *phydev = priv->phydev;
- air_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
- EN8811H_CLK_CGM_CKO, 0);
+ air_phy_buckpbus_reg_modify(phydev, EN8811H_CLK_CGM,
+ EN8811H_CLK_CGM_CKO, 0);
}
static int en8811h_clk_is_enabled(struct clk_hw *hw)
u32 pbus_value;
int ret;
- ret = air_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_CLK_CGM, &pbus_value);
if (ret < 0)
return ret;
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
- AN8811HB_GPIO_OUTPUT_345,
- AN8811HB_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_GPIO_OUTPUT,
+ AN8811HB_GPIO_OUTPUT_345,
+ AN8811HB_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
return ret;
/* Configure led gpio pins as output */
- ret = air_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
- EN8811H_GPIO_OUTPUT_345,
- EN8811H_GPIO_OUTPUT_345);
+ ret = air_phy_buckpbus_reg_modify(phydev, EN8811H_GPIO_OUTPUT,
+ EN8811H_GPIO_OUTPUT_345,
+ EN8811H_GPIO_OUTPUT_345);
if (ret < 0)
return ret;
return ret;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_RX_POLARITY_NORMAL;
- ret = air_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
- AN8811HB_RX_POLARITY_NORMAL,
- pbus_value);
+ ret = air_phy_buckpbus_reg_modify(phydev, AN8811HB_RX_POLARITY,
+ AN8811HB_RX_POLARITY_NORMAL,
+ pbus_value);
if (ret < 0)
return ret;
pbus_value = 0;
if (pol == PHY_POL_NORMAL)
pbus_value |= AN8811HB_TX_POLARITY_NORMAL;
- return air_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
- AN8811HB_TX_POLARITY_NORMAL,
- pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, AN8811HB_TX_POLARITY,
+ AN8811HB_TX_POLARITY_NORMAL,
+ pbus_value);
}
static int en8811h_config_serdes_polarity(struct phy_device *phydev)
if (pol == PHY_POL_NORMAL)
pbus_value |= EN8811H_POLARITY_TX_NORMAL;
- return air_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
- EN8811H_POLARITY_RX_REVERSE |
- EN8811H_POLARITY_TX_NORMAL, pbus_value);
+ return air_phy_buckpbus_reg_modify(phydev, EN8811H_POLARITY,
+ EN8811H_POLARITY_RX_REVERSE |
+ EN8811H_POLARITY_TX_NORMAL,
+ pbus_value);
}
static int an8811hb_config_init(struct phy_device *phydev)
val & MDIO_AN_10GBT_STAT_LP2_5G);
} else {
/* Get link partner 2.5GBASE-T ability from vendor register */
- ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
- &pbus_value);
+ ret = air_phy_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA,
+ &pbus_value);
if (ret < 0)
return ret;
linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,