]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
net: dsa: qca8k: Add support for force mode for fixed link topology
authorGeorge Moussalem <george.moussalem@outlook.com>
Fri, 5 Jun 2026 08:11:29 +0000 (12:11 +0400)
committerJakub Kicinski <kuba@kernel.org>
Wed, 10 Jun 2026 00:38:36 +0000 (17:38 -0700)
A fixed link topology is commonly used to connect this switch (on port
0 or 6) to a SoC's MAC over SGMII. When inband negotiation is not used,
the switch needs to be configured to operate in force mode. As such,
enable support for force mode.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://patch.msgid.link/20260605-qca8337-force-mode-v2-1-d9a6b6545bfa@outlook.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/dsa/qca/qca8k-8xxx.c
drivers/net/dsa/qca/qca8k.h

index a36b8b07030e344054f47292718ce91602131d8a..4c928983b862311a3ba8d2ef4e1ac3ce71617791 100644 (file)
@@ -1538,7 +1538,7 @@ static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
 {
        struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
        int cpu_port_index, ret, port;
-       u32 reg, val;
+       u32 mask, reg, val;
 
        port = pcs_to_qca8k_pcs(pcs)->port;
        switch (port) {
@@ -1611,11 +1611,21 @@ static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
        if (priv->ports_config.sgmii_tx_clk_falling_edge)
                val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
 
-       if (val)
-               ret = qca8k_rmw(priv, reg,
-                               QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
-                               QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
-                               val);
+       mask = (val) ? (QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
+                       QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE) : 0;
+
+       /*
+        * (Un)set force mode on QCA8337 only, don't include it in the mask for
+        * others. It is written to the PORT0 PAD register for both port 0 and 6.
+        */
+       if (priv->switch_id == QCA8K_ID_QCA8337) {
+               if (neg_mode == PHYLINK_PCS_NEG_OUTBAND)
+                       val |= QCA8K_PORT_PAD_SGMII_FORCE_MODE;
+               mask |= QCA8K_PORT_PAD_SGMII_FORCE_MODE;
+       }
+
+       if (mask)
+               ret = qca8k_rmw(priv, reg, mask, val);
 
        return 0;
 }
index 1a00e2f62fef3c7bf52ea4d91396718fec80c5df..95633889303257bd2f0a4a606a6494b5d40c40cf 100644 (file)
@@ -58,6 +58,7 @@
 #define          QCA8K_PORT_PAD_RGMII_TX_DELAY_EN              BIT(25)
 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN             BIT(24)
 #define   QCA8K_PORT_PAD_SGMII_EN                      BIT(7)
+#define   QCA8K_PORT_PAD_SGMII_FORCE_MODE              BIT(3)
 #define QCA8K_REG_PWS                                  0x010
 #define   QCA8K_PWS_POWER_ON_SEL                       BIT(31)
 /* This reg is only valid for QCA832x and toggle the package