extern const RRegUniverse* getRRegUniverse_AMD64 ( void );
-extern HInstrArray* iselSB_AMD64 ( const IRSB*,
+extern HInstrSB* iselSB_AMD64 ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,
extern const RRegUniverse* getRRegUniverse_ARM64 ( void );
-extern HInstrArray* iselSB_ARM64 ( const IRSB*,
+extern HInstrSB* iselSB_ARM64 ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,
extern const RRegUniverse* getRRegUniverse_ARM ( void );
-extern HInstrArray* iselSB_ARM ( const IRSB*,
+extern HInstrSB* iselSB_ARM ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,
extern const RRegUniverse* getRRegUniverse_MIPS ( Bool mode64 );
-extern HInstrArray *iselSB_MIPS ( const IRSB*,
+extern HInstrSB *iselSB_MIPS ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,
extern const RRegUniverse* getRRegUniverse_PPC ( Bool mode64 );
-extern HInstrArray* iselSB_PPC ( const IRSB*,
+extern HInstrSB* iselSB_PPC ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,
void genSpill_S390 ( HInstr **, HInstr **, HReg , Int , Bool );
void genReload_S390 ( HInstr **, HInstr **, HReg , Int , Bool );
extern s390_insn* genMove_S390(HReg from, HReg to, Bool mode64);
-HInstrArray *iselSB_S390 ( const IRSB *, VexArch, const VexArchInfo *,
+HInstrSB *iselSB_S390 ( const IRSB *, VexArch, const VexArchInfo *,
const VexAbiInfo *, Int, Int, Bool, Bool, Addr);
/* Return the number of bytes of code needed for an event check */
i->tag = Xin_ProfInc;
return i;
}
+X86Instr* X86Instr_IfThenElse(HInstrIfThenElse* hite)
+{
+ X86Instr* i = LibVEX_Alloc_inline(sizeof(X86Instr));
+ i->tag = Xin_IfThenElse;
+ i->Xin.IfThenElse.hite = hite;
+ return i;
+}
void ppX86Instr ( const X86Instr* i, Bool mode64 ) {
vassert(mode64 == False);
vex_printf("(profInc) addl $1,NotKnownYet; "
"adcl $0,NotKnownYet+4");
return;
+ case Xin_IfThenElse:
+ vex_printf("if (!%s) then {...",
+ showX86CondCode(i->Xin.IfThenElse.hite->ccOOL));
+ return;
default:
vpanic("ppX86Instr");
}
}
+void ppX86CondCode(X86CondCode condCode)
+{
+ vex_printf("%s", showX86CondCode(condCode));
+}
+
/* --------- Helpers for register allocation. --------- */
void getRegUsage_X86Instr (HRegUsage* u, const X86Instr* i, Bool mode64)
return False;
}
+extern HInstrIfThenElse* isIfThenElse_X86Instr(X86Instr* i)
+{
+ if (UNLIKELY(i->tag == Xin_IfThenElse)) {
+ return i->Xin.IfThenElse.hite;
+ }
+ return NULL;
+}
/* Generate x86 spill/reload instructions under the direction of the
register allocator. Note it's critical these don't write the
Xin_SseCMov, /* SSE conditional move */
Xin_SseShuf, /* SSE2 shuffle (pshufd) */
Xin_EvCheck, /* Event check */
- Xin_ProfInc /* 64-bit profile counter increment */
+ Xin_ProfInc, /* 64-bit profile counter increment */
+ Xin_IfThenElse /* HInstrIfThenElse */
}
X86InstrTag;
installed later, post-translation, by patching it in,
as it is not known at translation time. */
} ProfInc;
+ struct {
+ HInstrIfThenElse* hite;
+ } IfThenElse;
} Xin;
}
extern X86Instr* X86Instr_EvCheck ( X86AMode* amCounter,
X86AMode* amFailAddr );
extern X86Instr* X86Instr_ProfInc ( void );
+extern X86Instr* X86Instr_IfThenElse(HInstrIfThenElse*);
extern void ppX86Instr ( const X86Instr*, Bool );
+extern void ppX86CondCode(X86CondCode);
/* Some functions that insulate the register allocator from details
of the underlying instruction set. */
extern void getRegUsage_X86Instr ( HRegUsage*, const X86Instr*, Bool );
extern void mapRegs_X86Instr ( HRegRemap*, X86Instr*, Bool );
extern Bool isMove_X86Instr ( const X86Instr*, HReg*, HReg* );
+extern HInstrIfThenElse* isIfThenElse_X86Instr(X86Instr*);
extern Int emit_X86Instr ( /*MB_MOD*/Bool* is_profInc,
UChar* buf, Int nbuf, const X86Instr* i,
Bool mode64,
extern const RRegUniverse* getRRegUniverse_X86 ( void );
-extern HInstrArray* iselSB_X86 ( const IRSB*,
+extern HInstrSB* iselSB_X86 ( const IRSB*,
VexArch,
const VexArchInfo*,
const VexAbiInfo*,