--- /dev/null
+CONFIG_AR8216_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+# CONFIG_DTB_OMEGA2P is not set
+CONFIG_DTB_RT_NONE=y
+# CONFIG_DTB_VOCORE2 is not set
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FORCE_NR_CPUS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+# CONFIG_GPIO_MT7621 is not set
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+# CONFIG_LIST_HARDENED is not set
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MT7621_WDT is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_JIMAGE_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_VIRT_CONCAT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_RALINK_GSW_MT7620=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MDIO_MT7620=y
+CONFIG_NET_RALINK_MT7620=y
+# CONFIG_NET_RALINK_RT3050 is not set
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_VENDOR_MEDIATEK is not set
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_MT7620=y
+# CONFIG_PINCTRL_MT76X8 is not set
+CONFIG_PINCTRL_MTK_MTMIPS=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+CONFIG_RALINK_TIMER=y
+CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
--- /dev/null
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_AT803X_PHY=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKSRC_MIPS_GIC=y
+CONFIG_CLK_MT7621=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_EI=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DIMLIB=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MT7621=y
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+CONFIG_GRO_CELLS=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_MT7621=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LED_TRIGGER_PHY=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIATEK_GE_PHY=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIKROTIK=y
+CONFIG_MIKROTIK_RB_SYSFS=y
+# CONFIG_MIKROTIK_WLAN_DECOMPRESS_LZ77 is not set
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+CONFIG_MIPS_CM=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_CPC=y
+CONFIG_MIPS_CPS=y
+# CONFIG_MIPS_CPS_NS16550_BOOL is not set
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_GIC=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_NR_CPU_NR_MAP=4
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_MT7621=y
+CONFIG_MTD_NAND_MTK_BMT=y
+# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PARSER_TRX=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_ROUTERBOOT_PARTS=y
+CONFIG_MTD_SERCOMM_PARTS=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SPLIT_MINOR_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_NVMEM=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_VIRT_CONCAT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MT7530=y
+CONFIG_NET_DSA_MT7530_MDIO=y
+# CONFIG_NET_DSA_MT7530_MMIO is not set
+CONFIG_NET_DSA_TAG_MTK=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_MEDIATEK_SOC=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+# CONFIG_NET_VENDOR_RALINK is not set
+CONFIG_NET_XGRESS=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_LAYOUT_MIKROTIK=y
+CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIE_MT7621=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_DRIVERS_GENERIC=y
+CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHY_MT7621_PCI=y
+# CONFIG_PHY_RALINK_USB is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AW9523=y
+CONFIG_PINCTRL_MT7621=y
+CONFIG_PINCTRL_MTK_MTMIPS=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_SX150X=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCOM_NET_PHYLIB=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RALINK=y
+# CONFIG_RALINK_WDT is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_BQ32K=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_SMT=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_MT7620 is not set
+CONFIG_SOC_MT7621=y
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MIPS_CPS=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WEAK_ORDERING=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_MT7620A_EVAL is not set
+# CONFIG_DTB_OMEGA2P is not set
+CONFIG_DTB_RT_NONE=y
+# CONFIG_DTB_VOCORE2 is not set
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FORCE_NR_CPUS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_MT7621=y
+# CONFIG_GPIO_RALINK is not set
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MT7621_WDT=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_PARSER_TPLINK_SAFELOADER is not set
+CONFIG_MTD_PARSER_TRX=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_TPLINK_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_VIRT_CONCAT=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_RALINK_ESW_RT3050=y
+# CONFIG_NET_RALINK_MT7620 is not set
+CONFIG_NET_RALINK_RT3050=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_SWITCHDEV is not set
+# CONFIG_NET_VENDOR_MEDIATEK is not set
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+# CONFIG_PINCTRL_MT7620 is not set
+CONFIG_PINCTRL_MT76X8=y
+CONFIG_PINCTRL_MTK_MTMIPS=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+# CONFIG_RALINK_TIMER is not set
+# CONFIG_RALINK_WDT is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_MT7620=y
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_MT7621=y
+# CONFIG_SPI_RT2880 is not set
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_LEDS=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
--- /dev/null
+From 57cbfd333c9d65bfab1a06b49c75536ee28dc2ce Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Mon, 28 Oct 2024 21:36:43 +0100
+Subject: clocksource/drivers/ralink: Add Ralink System Tick Counter driver
+
+System Tick Counter is present on Ralink SoCs RT3352 and MT7620. This
+driver has been in 'arch/mips/ralink' directory since the beggining of
+Ralink architecture support. However, it can be moved into a more proper
+place in 'drivers/clocksource'. Hence add it here adding also support for
+compile test targets and reducing LOC in architecture code folder.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20241028203643.191268-2-sergio.paracuellos@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+---
+ arch/mips/ralink/Kconfig | 7 --
+ arch/mips/ralink/Makefile | 2 -
+ arch/mips/ralink/cevt-rt3352.c | 153 -------------------------------------
+ drivers/clocksource/Kconfig | 9 +++
+ drivers/clocksource/Makefile | 1 +
+ drivers/clocksource/timer-ralink.c | 150 ++++++++++++++++++++++++++++++++++++
+ 6 files changed, 160 insertions(+), 162 deletions(-)
+ delete mode 100644 arch/mips/ralink/cevt-rt3352.c
+ create mode 100644 drivers/clocksource/timer-ralink.c
+
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -1,13 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
+ if RALINK
+
+-config CLKEVT_RT3352
+- bool
+- depends on SOC_RT305X || SOC_MT7620
+- default y
+- select TIMER_OF
+- select CLKSRC_MMIO
+-
+ config RALINK_ILL_ACC
+ bool
+ depends on SOC_RT305X
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -10,8 +10,6 @@ ifndef CONFIG_MIPS_GIC
+ obj-y += clk.o timer.o
+ endif
+
+-obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
+-
+ obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
+
+ obj-$(CONFIG_IRQ_INTC) += irq.o
+--- a/arch/mips/ralink/cevt-rt3352.c
++++ /dev/null
+@@ -1,153 +0,0 @@
+-/*
+- * This file is subject to the terms and conditions of the GNU General Public
+- * License. See the file "COPYING" in the main directory of this archive
+- * for more details.
+- *
+- * Copyright (C) 2013 by John Crispin <john@phrozen.org>
+- */
+-
+-#include <linux/clockchips.h>
+-#include <linux/clocksource.h>
+-#include <linux/interrupt.h>
+-#include <linux/reset.h>
+-#include <linux/init.h>
+-#include <linux/time.h>
+-#include <linux/of.h>
+-#include <linux/of_irq.h>
+-#include <linux/of_address.h>
+-
+-#include <asm/mach-ralink/ralink_regs.h>
+-
+-#define SYSTICK_FREQ (50 * 1000)
+-
+-#define SYSTICK_CONFIG 0x00
+-#define SYSTICK_COMPARE 0x04
+-#define SYSTICK_COUNT 0x08
+-
+-/* route systick irq to mips irq 7 instead of the r4k-timer */
+-#define CFG_EXT_STK_EN 0x2
+-/* enable the counter */
+-#define CFG_CNT_EN 0x1
+-
+-struct systick_device {
+- void __iomem *membase;
+- struct clock_event_device dev;
+- int irq_requested;
+- int freq_scale;
+-};
+-
+-static int systick_set_oneshot(struct clock_event_device *evt);
+-static int systick_shutdown(struct clock_event_device *evt);
+-
+-static int systick_next_event(unsigned long delta,
+- struct clock_event_device *evt)
+-{
+- struct systick_device *sdev;
+- u32 count;
+-
+- sdev = container_of(evt, struct systick_device, dev);
+- count = ioread32(sdev->membase + SYSTICK_COUNT);
+- count = (count + delta) % SYSTICK_FREQ;
+- iowrite32(count, sdev->membase + SYSTICK_COMPARE);
+-
+- return 0;
+-}
+-
+-static void systick_event_handler(struct clock_event_device *dev)
+-{
+- /* noting to do here */
+-}
+-
+-static irqreturn_t systick_interrupt(int irq, void *dev_id)
+-{
+- struct clock_event_device *dev = (struct clock_event_device *) dev_id;
+-
+- dev->event_handler(dev);
+-
+- return IRQ_HANDLED;
+-}
+-
+-static struct systick_device systick = {
+- .dev = {
+- /*
+- * cevt-r4k uses 300, make sure systick
+- * gets used if available
+- */
+- .rating = 310,
+- .features = CLOCK_EVT_FEAT_ONESHOT,
+- .set_next_event = systick_next_event,
+- .set_state_shutdown = systick_shutdown,
+- .set_state_oneshot = systick_set_oneshot,
+- .event_handler = systick_event_handler,
+- },
+-};
+-
+-static int systick_shutdown(struct clock_event_device *evt)
+-{
+- struct systick_device *sdev;
+-
+- sdev = container_of(evt, struct systick_device, dev);
+-
+- if (sdev->irq_requested)
+- free_irq(systick.dev.irq, &systick.dev);
+- sdev->irq_requested = 0;
+- iowrite32(0, systick.membase + SYSTICK_CONFIG);
+-
+- return 0;
+-}
+-
+-static int systick_set_oneshot(struct clock_event_device *evt)
+-{
+- const char *name = systick.dev.name;
+- struct systick_device *sdev;
+- int irq = systick.dev.irq;
+-
+- sdev = container_of(evt, struct systick_device, dev);
+-
+- if (!sdev->irq_requested) {
+- if (request_irq(irq, systick_interrupt,
+- IRQF_PERCPU | IRQF_TIMER, name, &systick.dev))
+- pr_err("Failed to request irq %d (%s)\n", irq, name);
+- }
+- sdev->irq_requested = 1;
+- iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
+- systick.membase + SYSTICK_CONFIG);
+-
+- return 0;
+-}
+-
+-static int __init ralink_systick_init(struct device_node *np)
+-{
+- int ret;
+-
+- systick.membase = of_iomap(np, 0);
+- if (!systick.membase)
+- return -ENXIO;
+-
+- systick.dev.name = np->name;
+- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
+- systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
+- systick.dev.max_delta_ticks = 0x7fff;
+- systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
+- systick.dev.min_delta_ticks = 0x3;
+- systick.dev.irq = irq_of_parse_and_map(np, 0);
+- if (!systick.dev.irq) {
+- pr_err("%pOFn: request_irq failed", np);
+- return -EINVAL;
+- }
+-
+- ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
+- SYSTICK_FREQ, 301, 16,
+- clocksource_mmio_readl_up);
+- if (ret)
+- return ret;
+-
+- clockevents_register_device(&systick.dev);
+-
+- pr_info("%pOFn: running - mult: %d, shift: %d\n",
+- np, systick.dev.mult, systick.dev.shift);
+-
+- return 0;
+-}
+-
+-TIMER_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
+--- a/drivers/clocksource/Kconfig
++++ b/drivers/clocksource/Kconfig
+@@ -733,4 +733,13 @@ config GOLDFISH_TIMER
+ help
+ Support for the timer/counter of goldfish-rtc
+
++config RALINK_TIMER
++ bool "Ralink System Tick Counter"
++ depends on SOC_RT305X || SOC_MT7620 || COMPILE_TEST
++ select CLKSRC_MMIO
++ select TIMER_OF
++ help
++ Enables support for system tick counter present on
++ Ralink SoCs RT3352 and MT7620.
++
+ endmenu
+--- a/drivers/clocksource/Makefile
++++ b/drivers/clocksource/Makefile
+@@ -89,3 +89,4 @@ obj-$(CONFIG_MSC313E_TIMER) += timer-ms
+ obj-$(CONFIG_GOLDFISH_TIMER) += timer-goldfish.o
+ obj-$(CONFIG_GXP_TIMER) += timer-gxp.o
+ obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) += timer-loongson1-pwm.o
++obj-$(CONFIG_RALINK_TIMER) += timer-ralink.o
+--- /dev/null
++++ b/drivers/clocksource/timer-ralink.c
+@@ -0,0 +1,150 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Ralink System Tick Counter driver present on RT3352 and MT7620 SoCs.
++ *
++ * Copyright (C) 2013 by John Crispin <john@phrozen.org>
++ */
++
++#include <linux/clockchips.h>
++#include <linux/clocksource.h>
++#include <linux/interrupt.h>
++#include <linux/reset.h>
++#include <linux/init.h>
++#include <linux/time.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++
++#define SYSTICK_FREQ (50 * 1000)
++
++#define SYSTICK_CONFIG 0x00
++#define SYSTICK_COMPARE 0x04
++#define SYSTICK_COUNT 0x08
++
++/* route systick irq to mips irq 7 instead of the r4k-timer */
++#define CFG_EXT_STK_EN 0x2
++/* enable the counter */
++#define CFG_CNT_EN 0x1
++
++struct systick_device {
++ void __iomem *membase;
++ struct clock_event_device dev;
++ int irq_requested;
++ int freq_scale;
++};
++
++static int systick_set_oneshot(struct clock_event_device *evt);
++static int systick_shutdown(struct clock_event_device *evt);
++
++static int systick_next_event(unsigned long delta,
++ struct clock_event_device *evt)
++{
++ struct systick_device *sdev;
++ u32 count;
++
++ sdev = container_of(evt, struct systick_device, dev);
++ count = ioread32(sdev->membase + SYSTICK_COUNT);
++ count = (count + delta) % SYSTICK_FREQ;
++ iowrite32(count, sdev->membase + SYSTICK_COMPARE);
++
++ return 0;
++}
++
++static void systick_event_handler(struct clock_event_device *dev)
++{
++ /* noting to do here */
++}
++
++static irqreturn_t systick_interrupt(int irq, void *dev_id)
++{
++ struct clock_event_device *dev = (struct clock_event_device *)dev_id;
++
++ dev->event_handler(dev);
++
++ return IRQ_HANDLED;
++}
++
++static struct systick_device systick = {
++ .dev = {
++ /*
++ * cevt-r4k uses 300, make sure systick
++ * gets used if available
++ */
++ .rating = 310,
++ .features = CLOCK_EVT_FEAT_ONESHOT,
++ .set_next_event = systick_next_event,
++ .set_state_shutdown = systick_shutdown,
++ .set_state_oneshot = systick_set_oneshot,
++ .event_handler = systick_event_handler,
++ },
++};
++
++static int systick_shutdown(struct clock_event_device *evt)
++{
++ struct systick_device *sdev;
++
++ sdev = container_of(evt, struct systick_device, dev);
++
++ if (sdev->irq_requested)
++ free_irq(systick.dev.irq, &systick.dev);
++ sdev->irq_requested = 0;
++ iowrite32(0, systick.membase + SYSTICK_CONFIG);
++
++ return 0;
++}
++
++static int systick_set_oneshot(struct clock_event_device *evt)
++{
++ const char *name = systick.dev.name;
++ struct systick_device *sdev;
++ int irq = systick.dev.irq;
++
++ sdev = container_of(evt, struct systick_device, dev);
++
++ if (!sdev->irq_requested) {
++ if (request_irq(irq, systick_interrupt,
++ IRQF_PERCPU | IRQF_TIMER, name, &systick.dev))
++ pr_err("Failed to request irq %d (%s)\n", irq, name);
++ }
++ sdev->irq_requested = 1;
++ iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
++ systick.membase + SYSTICK_CONFIG);
++
++ return 0;
++}
++
++static int __init ralink_systick_init(struct device_node *np)
++{
++ int ret;
++
++ systick.membase = of_iomap(np, 0);
++ if (!systick.membase)
++ return -ENXIO;
++
++ systick.dev.name = np->name;
++ clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
++ systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
++ systick.dev.max_delta_ticks = 0x7fff;
++ systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
++ systick.dev.min_delta_ticks = 0x3;
++ systick.dev.irq = irq_of_parse_and_map(np, 0);
++ if (!systick.dev.irq) {
++ pr_err("%pOFn: request_irq failed", np);
++ return -EINVAL;
++ }
++
++ ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
++ SYSTICK_FREQ, 301, 16,
++ clocksource_mmio_readl_up);
++ if (ret)
++ return ret;
++
++ clockevents_register_device(&systick.dev);
++
++ pr_info("%pOFn: running - mult: %d, shift: %d\n",
++ np, systick.dev.mult, systick.dev.shift);
++
++ return 0;
++}
++
++TIMER_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
--- /dev/null
+From 198675bbc03d437fb80a35d781ad13d622d0ff68 Mon Sep 17 00:00:00 2001
+From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Date: Tue, 10 Sep 2024 06:40:24 +0200
+Subject: [PATCH 3/3] clk: ralink: mtmips: add mmc related clocks for SoCs
+ MT7620, MT7628 and MT7688
+
+Original architecture clock code from where this driver was derived did not
+include nothing related to mmc clocks. OpenWRT people started to use mtk-sd
+upstream driver recently and they were forced to use a dts 'fixed-clock'
+node with 48 MHz clock:
+- https://github.com/openwrt/openwrt/pull/15896
+The proper thing to do to avoid that is to add the mmc related clocks to the
+driver to avoid a dts with fixed clocks nodes. The minimal documentation in
+the mt7620 programming guide says that there is a BBP_PLL clock of 480 MHz
+derived from the 40 MHz XTAL and from there a clock divider by ten produces
+the desired SDHC clock of 48 MHz for the mmc. Hence add a fixed clock 'bbppll'
+and factor clock 'sdhc' ten divider child to properly set the 'mmc' peripheral
+clock with the desired 48 Mhz rate.
+
+Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+Link: https://lore.kernel.org/r/20240910044024.120009-4-sergio.paracuellos@gmail.com
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+---
+ drivers/clk/ralink/clk-mtmips.c | 30 +++++++++++++++++++++++-------
+ 1 file changed, 23 insertions(+), 7 deletions(-)
+
+--- a/drivers/clk/ralink/clk-mtmips.c
++++ b/drivers/clk/ralink/clk-mtmips.c
+@@ -207,6 +207,7 @@ static struct mtmips_clk mt7620_pherip_c
+ { CLK_PERIPH("10000b00.spi", "bus") },
+ { CLK_PERIPH("10000b40.spi", "bus") },
+ { CLK_PERIPH("10000c00.uartlite", "periph") },
++ { CLK_PERIPH("10130000.mmc", "sdhc") },
+ { CLK_PERIPH("10180000.wmac", "xtal") }
+ };
+
+@@ -220,6 +221,7 @@ static struct mtmips_clk mt76x8_pherip_c
+ { CLK_PERIPH("10000c00.uart0", "periph") },
+ { CLK_PERIPH("10000d00.uart1", "periph") },
+ { CLK_PERIPH("10000e00.uart2", "periph") },
++ { CLK_PERIPH("10130000.mmc", "sdhc") },
+ { CLK_PERIPH("10300000.wmac", "xtal") }
+ };
+
+@@ -271,8 +273,13 @@ static struct mtmips_clk_fixed rt3352_fi
+ CLK_FIXED("periph", "xtal", 40000000)
+ };
+
++static struct mtmips_clk_fixed mt7620_fixed_clocks[] = {
++ CLK_FIXED("bbppll", "xtal", 480000000)
++};
++
+ static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
+- CLK_FIXED("pcmi2s", "xtal", 480000000),
++ CLK_FIXED("bbppll", "xtal", 480000000),
++ CLK_FIXED("pcmi2s", "bbppll", 480000000),
+ CLK_FIXED("periph", "xtal", 40000000)
+ };
+
+@@ -327,6 +334,15 @@ static struct mtmips_clk_factor rt305x_f
+ CLK_FACTOR("bus", "cpu", 1, 3)
+ };
+
++static struct mtmips_clk_factor mt7620_factor_clocks[] = {
++ CLK_FACTOR("sdhc", "bbppll", 1, 10)
++};
++
++static struct mtmips_clk_factor mt76x8_factor_clocks[] = {
++ CLK_FACTOR("bus", "cpu", 1, 3),
++ CLK_FACTOR("sdhc", "bbppll", 1, 10)
++};
++
+ static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
+ struct mtmips_clk_priv *priv)
+ {
+@@ -810,10 +826,10 @@ static const struct mtmips_clk_data rt53
+ static const struct mtmips_clk_data mt7620_clk_data = {
+ .clk_base = mt7620_clks_base,
+ .num_clk_base = ARRAY_SIZE(mt7620_clks_base),
+- .clk_fixed = NULL,
+- .num_clk_fixed = 0,
+- .clk_factor = NULL,
+- .num_clk_factor = 0,
++ .clk_fixed = mt7620_fixed_clocks,
++ .num_clk_fixed = ARRAY_SIZE(mt7620_fixed_clocks),
++ .clk_factor = mt7620_factor_clocks,
++ .num_clk_factor = ARRAY_SIZE(mt7620_factor_clocks),
+ .clk_periph = mt7620_pherip_clks,
+ .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
+ };
+@@ -823,8 +839,8 @@ static const struct mtmips_clk_data mt76
+ .num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
+ .clk_fixed = mt76x8_fixed_clocks,
+ .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
+- .clk_factor = rt305x_factor_clocks,
+- .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
++ .clk_factor = mt76x8_factor_clocks,
++ .num_clk_factor = ARRAY_SIZE(mt76x8_factor_clocks),
+ .clk_periph = mt76x8_pherip_clks,
+ .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
+ };
--- /dev/null
+From ef57412d070fe663a66a5473ffc708bd89671259 Mon Sep 17 00:00:00 2001
+From: Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Date: Sun, 2 Feb 2025 17:10:14 +0800
+Subject: [PATCH] mips: ralink: update CPU clock index
+
+Some clock indexes have been reorganized in commit d34db686a3d7
+("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs").
+Update CPU clock index to match the clock driver changes.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+Co-authored-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
+---
+ arch/mips/ralink/clk.c | 11 ++---------
+ 1 file changed, 2 insertions(+), 9 deletions(-)
+
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -19,27 +19,22 @@
+
+ static const char *clk_cpu(int *idx)
+ {
++ *idx = 1;
++
+ switch (ralink_soc) {
+ case RT2880_SOC:
+- *idx = 0;
+ return "ralink,rt2880-sysc";
+ case RT3883_SOC:
+- *idx = 0;
+ return "ralink,rt3883-sysc";
+ case RT305X_SOC_RT3050:
+- *idx = 0;
+ return "ralink,rt3050-sysc";
+ case RT305X_SOC_RT3052:
+- *idx = 0;
+ return "ralink,rt3052-sysc";
+ case RT305X_SOC_RT3350:
+- *idx = 1;
+ return "ralink,rt3350-sysc";
+ case RT305X_SOC_RT3352:
+- *idx = 1;
+ return "ralink,rt3352-sysc";
+ case RT305X_SOC_RT5350:
+- *idx = 1;
+ return "ralink,rt5350-sysc";
+ case MT762X_SOC_MT7620A:
+ *idx = 2;
+@@ -48,10 +43,8 @@ static const char *clk_cpu(int *idx)
+ *idx = 2;
+ return "ralink,mt7620-sysc";
+ case MT762X_SOC_MT7628AN:
+- *idx = 1;
+ return "ralink,mt7628-sysc";
+ case MT762X_SOC_MT7688:
+- *idx = 1;
+ return "ralink,mt7688-sysc";
+ default:
+ *idx = -1;
--- /dev/null
+--- a/drivers/net/ethernet/Kconfig
++++ b/drivers/net/ethernet/Kconfig
+@@ -166,6 +166,7 @@ source "drivers/net/ethernet/pensando/Kc
+ source "drivers/net/ethernet/qlogic/Kconfig"
+ source "drivers/net/ethernet/brocade/Kconfig"
+ source "drivers/net/ethernet/qualcomm/Kconfig"
++source "drivers/net/ethernet/ralink/Kconfig"
+ source "drivers/net/ethernet/rdc/Kconfig"
+ source "drivers/net/ethernet/realtek/Kconfig"
+ source "drivers/net/ethernet/renesas/Kconfig"
+--- a/drivers/net/ethernet/Makefile
++++ b/drivers/net/ethernet/Makefile
+@@ -77,6 +77,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES)
+ obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
+ obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
+ obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/
++obj-$(CONFIG_NET_VENDOR_RALINK) += ralink/
+ obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
+ obj-$(CONFIG_NET_VENDOR_RENESAS) += renesas/
+ obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
--- /dev/null
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -62,4 +62,16 @@ static inline int mt7620_get_eco(void)
+ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
+ }
+
++static inline int mt7620_get_chipver(void)
++{
++ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) &
++ CHIP_REV_VER_MASK;
++}
++
++static inline int mt7620_get_pkg(void)
++{
++ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) &
++ CHIP_REV_PKG_MASK;
++}
++
+ #endif
--- /dev/null
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:08:11 +0200
+Subject: [PATCH 1/2] MIPS: use set_mode() to enable/disable the cevt-r4k irq
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/kernel/cevt-r4k.c | 43 +++++++++++++++++++++++++++++++++++++
+ drivers/clocksource/Kconfig | 5 +++++
+ 2 files changed, 48 insertions(+)
+
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -16,6 +16,31 @@
+ #include <asm/time.h>
+ #include <asm/cevt-r4k.h>
+
++#ifdef CONFIG_CEVT_SYSTICK_QUIRK
++static int mips_state_oneshot(struct clock_event_device *evt)
++{
++ unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
++ if (!cp0_timer_irq_installed) {
++ cp0_timer_irq_installed = 1;
++ if (request_irq(evt->irq, c0_compare_interrupt, flags, "timer",
++ c0_compare_interrupt))
++ pr_err("Failed to request irq %d (timer)\n", evt->irq);
++ }
++
++ return 0;
++}
++
++static int mips_state_shutdown(struct clock_event_device *evt)
++{
++ if (cp0_timer_irq_installed) {
++ cp0_timer_irq_installed = 0;
++ free_irq(evt->irq, NULL);
++ }
++
++ return 0;
++}
++#endif
++
+ static int mips_next_event(unsigned long delta,
+ struct clock_event_device *evt)
+ {
+@@ -292,7 +317,9 @@ core_initcall(r4k_register_cpufreq_notif
+
+ int r4k_clockevent_init(void)
+ {
++#ifndef CONFIG_CEVT_SYSTICK_QUIRK
+ unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
++#endif
+ unsigned int cpu = smp_processor_id();
+ struct clock_event_device *cd;
+ unsigned int irq, min_delta;
+@@ -303,6 +330,15 @@ int r4k_clockevent_init(void)
+ if (!c0_compare_int_usable())
+ return -ENXIO;
+
++#ifdef CONFIG_CEVT_SYSTICK_QUIRK
++ /*
++ * With vectored interrupts things are getting platform specific.
++ * get_c0_compare_int is a hook to allow a platform to return the
++ * interrupt number of its liking.
++ */
++ irq = get_c0_compare_int();
++#endif
++
+ cd = &per_cpu(mips_clockevent_device, cpu);
+
+ cd->name = "MIPS";
+@@ -314,11 +350,17 @@ int r4k_clockevent_init(void)
+
+ cd->rating = 300;
+ cd->cpumask = cpumask_of(cpu);
++#ifdef CONFIG_CEVT_SYSTICK_QUIRK
++ cd->irq = irq;
++ cd->set_state_shutdown = mips_state_shutdown;
++ cd->set_state_oneshot = mips_state_oneshot;
++#endif
+ cd->set_next_event = mips_next_event;
+ cd->event_handler = mips_event_handler;
+
+ clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
+
++#ifndef CONFIG_CEVT_SYSTICK_QUIRK
+ if (cp0_timer_irq_installed)
+ return 0;
+
+@@ -334,6 +376,7 @@ int r4k_clockevent_init(void)
+ if (request_irq(irq, c0_compare_interrupt, flags, "timer",
+ c0_compare_interrupt))
+ pr_err("Failed to request irq %d (timer)\n", irq);
++#endif
+
+ return 0;
+ }
+--- a/drivers/clocksource/Kconfig
++++ b/drivers/clocksource/Kconfig
+@@ -732,10 +732,15 @@ config GOLDFISH_TIMER
+ depends on RTC_DRV_GOLDFISH
+ help
+ Support for the timer/counter of goldfish-rtc
++
++config CEVT_SYSTICK_QUIRK
++ bool
++ default n
+
+ config RALINK_TIMER
+ bool "Ralink System Tick Counter"
+ depends on SOC_RT305X || SOC_MT7620 || COMPILE_TEST
++ select CEVT_SYSTICK_QUIRK
+ select CLKSRC_MMIO
+ select TIMER_OF
+ help
--- /dev/null
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 16:26:41 +0200
+Subject: [PATCH 2/2] MIPS: ralink: add cpu frequency scaling
+
+This feature will break udelay() and cause the delay loop to have longer delays
+when the frequency is scaled causing a performance hit.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/clocksource/timer-ralink.c | 117 ++++++++++++++++++++++-------
+ 1 file changed, 89 insertions(+), 28 deletions(-)
+
+--- a/drivers/clocksource/timer-ralink.c
++++ b/drivers/clocksource/timer-ralink.c
+@@ -5,6 +5,7 @@
+ * Copyright (C) 2013 by John Crispin <john@phrozen.org>
+ */
+
++#include <asm/mach-ralink/ralink_regs.h>
+ #include <linux/clockchips.h>
+ #include <linux/clocksource.h>
+ #include <linux/interrupt.h>
+@@ -26,6 +27,10 @@
+ /* enable the counter */
+ #define CFG_CNT_EN 0x1
+
++/* mt7620 frequency scaling defines */
++#define CLK_LUT_CFG 0x40
++#define SLEEP_EN BIT(31)
++
+ struct systick_device {
+ void __iomem *membase;
+ struct clock_event_device dev;
+@@ -33,21 +38,53 @@ struct systick_device {
+ int freq_scale;
+ };
+
++static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
++
+ static int systick_set_oneshot(struct clock_event_device *evt);
+ static int systick_shutdown(struct clock_event_device *evt);
+
++static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
++{
++ if (sdev->freq_scale == status)
++ return;
++
++ sdev->freq_scale = status;
++
++ pr_info("%s: %s autosleep mode\n", sdev->dev.name,
++ (status) ? ("enable") : ("disable"));
++ if (status)
++ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
++ else
++ rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
++}
++
++static inline unsigned int read_count(struct systick_device *sdev)
++{
++ return ioread32(sdev->membase + SYSTICK_COUNT);
++}
++
++static inline unsigned int read_compare(struct systick_device *sdev)
++{
++ return ioread32(sdev->membase + SYSTICK_COMPARE);
++}
++
++static inline void write_compare(struct systick_device *sdev, unsigned int val)
++{
++ iowrite32(val, sdev->membase + SYSTICK_COMPARE);
++}
++
+ static int systick_next_event(unsigned long delta,
+ struct clock_event_device *evt)
+ {
+ struct systick_device *sdev;
+- u32 count;
++ int res;
+
+ sdev = container_of(evt, struct systick_device, dev);
+- count = ioread32(sdev->membase + SYSTICK_COUNT);
+- count = (count + delta) % SYSTICK_FREQ;
+- iowrite32(count, sdev->membase + SYSTICK_COMPARE);
++ delta += read_count(sdev);
++ write_compare(sdev, delta);
++ res = ((int)(read_count(sdev) - delta) >= 0) ? -ETIME : 0;
+
+- return 0;
++ return res;
+ }
+
+ static void systick_event_handler(struct clock_event_device *dev)
+@@ -57,20 +94,25 @@ static void systick_event_handler(struct
+
+ static irqreturn_t systick_interrupt(int irq, void *dev_id)
+ {
+- struct clock_event_device *dev = (struct clock_event_device *)dev_id;
++ int ret = 0;
++ struct clock_event_device *cdev;
++ struct systick_device *sdev;
+
+- dev->event_handler(dev);
++ if (read_c0_cause() & STATUSF_IP7) {
++ cdev = (struct clock_event_device *)dev_id;
++ sdev = container_of(cdev, struct systick_device, dev);
++
++ /* Clear Count/Compare Interrupt */
++ write_compare(sdev, read_compare(sdev));
++ cdev->event_handler(cdev);
++ ret = 1;
++ }
+
+- return IRQ_HANDLED;
++ return IRQ_RETVAL(ret);
+ }
+
+ static struct systick_device systick = {
+ .dev = {
+- /*
+- * cevt-r4k uses 300, make sure systick
+- * gets used if available
+- */
+- .rating = 310,
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .set_next_event = systick_next_event,
+ .set_state_shutdown = systick_shutdown,
+@@ -88,7 +130,13 @@ static int systick_shutdown(struct clock
+ if (sdev->irq_requested)
+ free_irq(systick.dev.irq, &systick.dev);
+ sdev->irq_requested = 0;
+- iowrite32(0, systick.membase + SYSTICK_CONFIG);
++ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
++
++ if (systick_freq_scaling)
++ systick_freq_scaling(sdev, 0);
++
++ if (systick_freq_scaling)
++ systick_freq_scaling(sdev, 1);
+
+ return 0;
+ }
+@@ -113,33 +161,46 @@ static int systick_set_oneshot(struct cl
+ return 0;
+ }
+
++static const struct of_device_id systick_match[] = {
++ { .compatible = "ralink,mt7620a-systick", .data = mt7620_freq_scaling},
++ {},
++};
++
+ static int __init ralink_systick_init(struct device_node *np)
+ {
+- int ret;
++ const struct of_device_id *match;
++ int rating = 200;
+
+ systick.membase = of_iomap(np, 0);
+ if (!systick.membase)
+ return -ENXIO;
+
+- systick.dev.name = np->name;
+- clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
+- systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
+- systick.dev.max_delta_ticks = 0x7fff;
+- systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
+- systick.dev.min_delta_ticks = 0x3;
++ match = of_match_node(systick_match, np);
++ if (match) {
++ systick_freq_scaling = match->data;
++ /*
++ * cevt-r4k uses 300, make sure systick
++ * gets used if available
++ */
++ rating = 310;
++ }
++
++ /* enable counter than register clock source */
++ iowrite32(CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
++ clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
++ SYSTICK_FREQ, rating, 16, clocksource_mmio_readl_up);
++
++ /* register clock event */
+ systick.dev.irq = irq_of_parse_and_map(np, 0);
+ if (!systick.dev.irq) {
+ pr_err("%pOFn: request_irq failed", np);
+ return -EINVAL;
+ }
+
+- ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
+- SYSTICK_FREQ, 301, 16,
+- clocksource_mmio_readl_up);
+- if (ret)
+- return ret;
+-
+- clockevents_register_device(&systick.dev);
++ systick.dev.name = np->name;
++ systick.dev.rating = rating;
++ systick.dev.cpumask = cpumask_of(0);
++ clockevents_config_and_register(&systick.dev, SYSTICK_FREQ, 0x3, 0x7fff);
+
+ pr_info("%pOFn: running - mult: %d, shift: %d\n",
+ np, systick.dev.mult, systick.dev.shift);
--- /dev/null
+From f15d27f9c90ede4b16eb37f9ae573ef81c2b6996 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 31 Dec 2020 18:49:12 +0100
+Subject: [PATCH] MIPS: add bootargs-override property
+
+Add support for the bootargs-override property to the chosen node
+similar to the one used on ipq806x or mpc85xx.
+
+This is necessary, as the U-Boot used on some boards, notably the
+Ubiquiti UniFi 6 Lite, overwrite the bootargs property of the chosen
+node leading to a kernel panic when loading OpenWrt.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/mips/kernel/setup.c | 30 ++++++++++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+
+--- a/arch/mips/kernel/setup.c
++++ b/arch/mips/kernel/setup.c
+@@ -564,8 +564,28 @@ static int __init bootcmdline_scan_chose
+
+ #endif /* CONFIG_OF_EARLY_FLATTREE */
+
++static int __init bootcmdline_scan_chosen_override(unsigned long node, const char *uname,
++ int depth, void *data)
++{
++ bool *dt_bootargs = data;
++ const char *p;
++ int l;
++
++ if (depth != 1 || !data || strcmp(uname, "chosen") != 0)
++ return 0;
++
++ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
++ if (p != NULL && l > 0) {
++ strlcpy(boot_command_line, p, COMMAND_LINE_SIZE);
++ *dt_bootargs = true;
++ }
++
++ return 1;
++}
++
+ static void __init bootcmdline_init(void)
+ {
++ bool dt_bootargs_override = false;
+ bool dt_bootargs = false;
+
+ /*
+@@ -579,6 +599,14 @@ static void __init bootcmdline_init(void
+ }
+
+ /*
++ * If bootargs-override in the chosen node is set, use this as the
++ * command line
++ */
++ of_scan_flat_dt(bootcmdline_scan_chosen_override, &dt_bootargs_override);
++ if (dt_bootargs_override)
++ return;
++
++ /*
+ * If the user specified a built-in command line &
+ * MIPS_CMDLINE_BUILTIN_EXTEND, then the built-in command line is
+ * prepended to arguments from the bootloader or DT so we'll copy them
--- /dev/null
+From 5ede027f6c4a57ed25da872420508b7f1168b36b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 7 Dec 2015 17:15:32 +0100
+Subject: [PATCH 13/53] owrt: hack: fix mt7688 cache issue
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/kernel/setup.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/kernel/setup.c
++++ b/arch/mips/kernel/setup.c
+@@ -706,7 +706,6 @@ static void __init arch_mem_init(char **
+ mips_reserve_vmcore();
+
+ mips_parse_crashkernel();
+- device_tree_init();
+
+ /*
+ * In order to reduce the possibility of kernel panic when failed to
+@@ -842,6 +841,7 @@ void __init setup_arch(char **cmdline_p)
+
+ cpu_cache_init();
+ paging_init();
++ device_tree_init();
+
+ memblock_dump_all();
+
--- /dev/null
+From 9e6ce539092a1dd605a20bf73c655a9de58d8641 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 7 Dec 2015 17:18:05 +0100
+Subject: [PATCH 15/53] arch: mips: do not select illegal access driver by
+ default
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Kconfig | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -2,9 +2,9 @@
+ if RALINK
+
+ config RALINK_ILL_ACC
+- bool
++ bool "illegal access irq"
+ depends on SOC_RT305X
+- default y
++ default n
+
+ config IRQ_INTC
+ bool
--- /dev/null
+From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
+From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Date: Wed, 7 Apr 2021 13:07:38 -0700
+Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
+
+Most MT7621 SoCs have 2 cores, which is detected and supported properly
+by CPS.
+
+Unfortunately, MT7621 SoC has a less common S variant with only one core.
+On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
+starting SMP. CPULAUNCH registers can be used in that case to detect the
+absence of the second core and override the GCR_CONFIG PCORES field.
+
+Rework a long-standing OpenWrt patch to override the value of
+mips_cps_numcores on single-core MT7621 systems.
+
+Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
+MT7621 device (Netgear R6220).
+
+Original 4.14 OpenWrt patch:
+Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
+Current 5.10 OpenWrt patch:
+Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
+
+Suggested-by: Felix Fietkau <nbd@nbd.name>
+Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
+Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+---
+
+The proposed detection method was based on reading the LAUNCH_FREADY core flag.
+However, this method only works before the cores are launched.
+For this reason, the core number detection method has been changed to a simpler one.
+For mt6721s the 17th revision bit is zero, hence we know that it is this chip,
+so the number of cores is 1.
+
+Co-authored-by: Shiji Yang <yangshiji66@qq.com>
+Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
+---
+ arch/mips/include/asm/mips-cps.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/mips/include/asm/mips-cps.h
++++ b/arch/mips/include/asm/mips-cps.h
+@@ -11,6 +11,8 @@
+ #include <linux/io.h>
+ #include <linux/types.h>
+
++#include <asm/mach-ralink/mt7621.h>
++
+ extern unsigned long __cps_access_bad_size(void)
+ __compiletime_error("Bad size for CPS accessor");
+
+@@ -165,6 +167,10 @@ static inline unsigned int mips_cps_numc
+ if (!mips_cm_present())
+ return 0;
+
++ if (IS_ENABLED(CONFIG_SOC_MT7621) &&
++ !FIELD_GET(0x20000, __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV)))
++ return 1;
++
+ /* Add one before masking to handle 0xff indicating no cores */
+ return FIELD_GET(CM_GCR_CONFIG_PCORES,
+ mips_cps_cluster_config(cluster) + 1);
--- /dev/null
+--- a/arch/mips/ralink/irq-gic.c
++++ b/arch/mips/ralink/irq-gic.c
+@@ -13,6 +13,12 @@
+
+ int get_c0_perfcount_int(void)
+ {
++ /*
++ * Performance counter events are routed through GIC.
++ * Prevent them from firing on CPU IRQ7 as well
++ */
++ clear_c0_status(IE_SW0 << 7);
++
+ return gic_get_c0_perfcount_int();
+ }
+ EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
--- /dev/null
+From ee9081b2726a5ca8cde5497afdc5425e21ff8f8b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 15 Jul 2013 00:39:21 +0200
+Subject: [PATCH 37/53] mtd: cfi cmdset 0002 force word write
+
+---
+ drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -38,7 +38,7 @@
+ #include <linux/mtd/xip.h>
+
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+
+ #define MAX_RETRIES 3
+
--- /dev/null
+From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 6 May 2021 17:49:55 +0200
+Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as
+
+Add MTD support for the BoHong bh25q128as SPI NOR chip.
+The chip has 16MB of total capacity, divided into a total of 256
+sectors, each 64KB sized. The chip also supports 4KB sectors.
+Additionally, it supports dual and quad read modes.
+
+Functionality was verified on an Tenbay WR1800K / MTK MT7621 board.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/mtd/spi-nor/Makefile | 1 +
+ drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++
+ drivers/mtd/spi-nor/core.c | 1 +
+ drivers/mtd/spi-nor/core.h | 1 +
+ 4 files changed, 24 insertions(+)
+ create mode 100644 drivers/mtd/spi-nor/bohong.c
+
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -2,6 +2,7 @@
+
+ spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o
+ spi-nor-objs += atmel.o
++spi-nor-objs += bohong.o
+ spi-nor-objs += catalyst.o
+ spi-nor-objs += eon.o
+ spi-nor-objs += esmt.o
+--- /dev/null
++++ b/drivers/mtd/spi-nor/bohong.c
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2005, Intec Automation Inc.
++ * Copyright (C) 2014, Freescale Semiconductor, Inc.
++ */
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info bohong_parts[] = {
++ /* BoHong Microelectronics */
++ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256)
++ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++};
++
++const struct spi_nor_manufacturer spi_nor_bohong = {
++ .name = "bohong",
++ .parts = bohong_parts,
++ .nparts = ARRAY_SIZE(bohong_parts),
++};
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -2001,6 +2001,7 @@ int spi_nor_sr2_bit7_quad_enable(struct
+
+ static const struct spi_nor_manufacturer *manufacturers[] = {
+ &spi_nor_atmel,
++ &spi_nor_bohong,
+ &spi_nor_catalyst,
+ &spi_nor_eon,
+ &spi_nor_esmt,
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -631,6 +631,7 @@ struct sfdp {
+
+ /* Manufacturer drivers. */
+ extern const struct spi_nor_manufacturer spi_nor_atmel;
++extern const struct spi_nor_manufacturer spi_nor_bohong;
+ extern const struct spi_nor_manufacturer spi_nor_catalyst;
+ extern const struct spi_nor_manufacturer spi_nor_eon;
+ extern const struct spi_nor_manufacturer spi_nor_esmt;
--- /dev/null
+From e84e2430ee0e483842b4ff013ae8a6e7e2fa2734 Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 1 Apr 2020 02:07:58 +0800
+Subject: [PATCH 1/2] mtd: rawnand: add driver support for MT7621 nand
+ flash controller
+
+This patch adds NAND flash controller driver for MediaTek MT7621 SoC.
+
+The NAND flash controller is similar with controllers described in
+mtk_nand.c, except that the controller from MT7621 doesn't support DMA
+transmission, and some registers' offset and fields are different.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ drivers/mtd/nand/raw/Kconfig | 8 +
+ drivers/mtd/nand/raw/Makefile | 1 +
+ drivers/mtd/nand/raw/mt7621_nand.c | 1348 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 1357 insertions(+)
+ create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c
+
+--- a/drivers/mtd/nand/raw/Kconfig
++++ b/drivers/mtd/nand/raw/Kconfig
+@@ -337,6 +337,14 @@ config MTD_NAND_QCOM
+ Enables support for NAND flash chips on SoCs containing the EBI2 NAND
+ controller. This controller is found on IPQ806x SoC.
+
++config MTD_NAND_MT7621
++ tristate "MT7621 NAND controller"
++ depends on SOC_MT7621 || COMPILE_TEST
++ depends on HAS_IOMEM
++ help
++ Enables support for NAND controller on MT7621 SoC.
++ This driver uses PIO mode for data transmission instead of DMA mode.
++
+ config MTD_NAND_MTK
+ tristate "MTK NAND controller"
+ depends on MTD_NAND_ECC_MEDIATEK
+--- a/drivers/mtd/nand/raw/Makefile
++++ b/drivers/mtd/nand/raw/Makefile
+@@ -46,6 +46,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n
+ obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
+ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
+ obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
++obj-$(CONFIG_MTD_NAND_MT7621) += mt7621_nand.o
+ obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o
+ obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o
+ obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
--- /dev/null
+From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001
+From: Weijie Gao <weijie.gao@mediatek.com>
+Date: Wed, 1 Apr 2020 02:07:59 +0800
+Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver
+
+This patch adds documentation for MediaTek MT7621 NAND flash controller
+driver.
+
+Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+---
+ .../bindings/mtd/mediatek,mt7621-nfc.yaml | 68 ++++++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
+@@ -0,0 +1,68 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding
++
++maintainers:
++ - Weijie Gao <weijie.gao@mediatek.com>
++
++description: |
++ This driver uses a single node to describe both NAND Flash controller
++ interface (NFI) and ECC engine for MT7621 SoC.
++ MT7621 supports only one chip select.
++
++properties:
++ "#address-cells": false
++ "#size-cells": false
++
++ compatible:
++ enum:
++ - mediatek,mt7621-nfc
++
++ reg:
++ items:
++ - description: Register base of NFI core
++ - description: Register base of ECC engine
++
++ reg-names:
++ items:
++ - const: nfi
++ - const: ecc
++
++ clocks:
++ items:
++ - description: Source clock for NFI core, fixed 125MHz
++
++ clock-names:
++ items:
++ - const: nfi_clk
++
++required:
++ - compatible
++ - reg
++ - reg-names
++ - clocks
++ - clock-names
++
++examples:
++ - |
++ nficlock: nficlock {
++ #clock-cells = <0>;
++ compatible = "fixed-clock";
++
++ clock-frequency = <125000000>;
++ };
++
++ nand@1e003000 {
++ compatible = "mediatek,mt7621-nfc";
++
++ reg = <0x1e003000 0x800
++ 0x1e003800 0x800>;
++ reg-names = "nfi", "ecc";
++
++ clocks = <&nficlock>;
++ clock-names = "nfi_clk";
++ };
--- /dev/null
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:38:50 +0100
+Subject: [PATCH] NET: multi phy support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/phy_device.c | 2 +-
+ include/linux/phy.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1075,7 +1075,7 @@ static void phy_link_change(struct phy_d
+
+ if (up)
+ netif_carrier_on(netdev);
+- else
++ else if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(netdev);
+ phydev->adjust_link(netdev);
+ if (phydev->mii_ts && phydev->mii_ts->link_state)
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -661,6 +661,7 @@ struct phy_device {
+ unsigned downshifted_rate:1;
+ unsigned is_on_sfp_module:1;
+ unsigned mac_managed_pm:1;
++ unsigned no_auto_carrier_off:1;
+ unsigned wol_enabled:1;
+
+ unsigned autoneg:1;
--- /dev/null
+From d94fc5ce1dc395747c3934ecffcdec0396583755 Mon Sep 17 00:00:00 2001
+From: Nick Hainke <vincent@systemli.org>
+Date: Fri, 26 May 2023 19:46:33 +0200
+Subject: [PATCH] dmaengine: mediatek: add HSDMA support for mt7621
+
+Commit 87dd67f496f7 ("staging: mt7621-dma: remove driver from tree")
+removed the mt7621-dma driver. Move the driver from staging to the
+folder "drivers/dma/mediatek" containing already other mediatek dma
+driver implementations and maintain it downstream in OpenWrt.
+
+This patch will not be sent to upstream linux. It is just a workaround.
+
+Signed-off-by: Nick Hainke <vincent@systemli.org>
+---
+ drivers/dma/mediatek/Kconfig | 6 ++++++
+ drivers/dma/mediatek/Makefile | 1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/dma/mediatek/Kconfig
++++ b/drivers/dma/mediatek/Kconfig
+@@ -36,3 +36,9 @@ config MTK_UART_APDMA
+ When SERIAL_8250_MT6577 is enabled, and if you want to use DMA,
+ you can enable the config. The DMA engine can only be used
+ with MediaTek SoCs.
++
++config MTK_HSDMA
++ tristate "MTK HSDMA support"
++ depends on RALINK && SOC_MT7621
++ select DMA_ENGINE
++ select DMA_VIRTUAL_CHANNELS
+--- a/drivers/dma/mediatek/Makefile
++++ b/drivers/dma/mediatek/Makefile
+@@ -2,3 +2,4 @@
+ obj-$(CONFIG_MTK_UART_APDMA) += mtk-uart-apdma.o
+ obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+ obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
++obj-$(CONFIG_MTK_HSDMA) += hsdma-mt7621.o
--- /dev/null
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 19:45:30 +0200
+Subject: [PATCH 1/2] DT: Add documentation for gpio-ralink
+
+Describe gpio-ralink binding.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/gpio/gpio-ralink.txt | 42 +++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+@@ -0,0 +1,42 @@
++Ralink SoC GPIO controller bindings
++
++Required properties:
++- compatible:
++ - "ralink,rt2880-gpio" for Ralink controllers
++- #gpio-cells : Should be two.
++ - first cell is the pin number
++ - second cell is used to specify optional parameters (unused)
++- gpio-controller : Marks the device node as a GPIO controller
++- reg : Physical base address and length of the controller's registers
++- interrupt-parent: phandle to the INTC device node
++- interrupts : Specify the INTC interrupt number
++- ngpios : Specify the number of GPIOs
++- ralink,register-map : The register layout depends on the GPIO bank and actual
++ SoC type. Register offsets need to be in this order.
++ [ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
++- interrupt-controller : marks this as an interrupt controller
++- #interrupt-cells : a standard two-cell interrupt flag, see
++ interrupt-controller/interrupts.txt
++
++Example:
++
++ gpio0: gpio@600 {
++ compatible = "ralink,rt2880-gpio";
++
++ #gpio-cells = <2>;
++ gpio-controller;
++
++ reg = <0x600 0x34>;
++
++ interrupt-controller;
++ #interrupt-cells = <2>;
++
++ interrupt-parent = <&intc>;
++ interrupts = <6>;
++
++ ngpios = <24>;
++ ralink,register-map = [ 00 04 08 0c
++ 20 24 28 2c
++ 30 34 ];
++
++ };
--- /dev/null
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 4 Aug 2014 20:36:29 +0200
+Subject: [PATCH 2/2] GPIO: MIPS: ralink: add gpio driver for ralink SoC
+
+Add gpio driver for Ralink SoC. This driver makes the gpio core on
+RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/gpio/Kconfig | 8 ++
+ drivers/gpio/Makefile | 1 +
+ drivers/gpio/gpio-ralink.c | 230 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 239 insertions(+)
+ create mode 100644 drivers/gpio/gpio-ralink.c
+
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -509,6 +509,14 @@ config GPIO_PXA
+ help
+ Say yes here to support the PXA GPIO device.
+
++config GPIO_RALINK
++ bool "Ralink GPIO Support"
++ depends on SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620
++ select GPIO_GENERIC
++ select GPIOLIB_IRQCHIP
++ help
++ Say yes here to support the Ralink SoC GPIO device
++
+ config GPIO_RCAR
+ tristate "Renesas R-Car and RZ/G GPIO support"
+ depends on ARCH_RENESAS || COMPILE_TEST
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -130,6 +130,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos
+ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
+ obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
+ obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
++obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
+ obj-$(CONFIG_GPIO_RASPBERRYPI_EXP) += gpio-raspberrypi-exp.o
+ obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
+ obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
+--- /dev/null
++++ b/drivers/gpio/gpio-ralink.c
+@@ -0,0 +1,230 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/err.h>
++#include <linux/gpio/driver.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++
++enum ralink_gpio_reg {
++ GPIO_REG_INT = 0,
++ GPIO_REG_EDGE,
++ GPIO_REG_RENA,
++ GPIO_REG_FENA,
++ GPIO_REG_DATA,
++ GPIO_REG_DIR,
++ GPIO_REG_POL,
++ GPIO_REG_SET,
++ GPIO_REG_RESET,
++ GPIO_REG_TOGGLE,
++ GPIO_REG_MAX
++};
++
++struct ralink_gpio_chip {
++ struct gpio_chip chip;
++ u8 regs[GPIO_REG_MAX];
++
++ spinlock_t lock;
++ void __iomem *membase;
++ int gpio_irq;
++
++ u32 rising;
++ u32 falling;
++};
++
++static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
++{
++ iowrite32(val, rg->membase + rg->regs[reg]);
++}
++
++static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
++{
++ return ioread32(rg->membase + rg->regs[reg]);
++}
++
++static irqreturn_t ralink_gpio_irq_handler(int irq, void *data)
++{
++ struct gpio_chip *gc = data;
++ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
++ irqreturn_t ret = IRQ_NONE;
++ unsigned long pending;
++ int bit;
++
++ pending = rt_gpio_r32(rg, GPIO_REG_INT);
++ for_each_set_bit(bit, &pending, rg->chip.ngpio) {
++ generic_handle_domain_irq(gc->irq.domain, bit);
++ rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
++ ret |= IRQ_HANDLED;
++ }
++
++ return ret;
++}
++
++static void ralink_gpio_irq_unmask(struct irq_data *d)
++{
++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
++ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
++ unsigned long flags;
++ u32 rise, fall;
++
++ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
++ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
++
++ spin_lock_irqsave(&rg->lock, flags);
++ rt_gpio_w32(rg, GPIO_REG_RENA, rise | (BIT(d->hwirq) & rg->rising));
++ rt_gpio_w32(rg, GPIO_REG_FENA, fall | (BIT(d->hwirq) & rg->falling));
++ spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static void ralink_gpio_irq_mask(struct irq_data *d)
++{
++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
++ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
++ unsigned long flags;
++ u32 rise, fall;
++
++ rise = rt_gpio_r32(rg, GPIO_REG_RENA);
++ fall = rt_gpio_r32(rg, GPIO_REG_FENA);
++
++ spin_lock_irqsave(&rg->lock, flags);
++ rt_gpio_w32(rg, GPIO_REG_FENA, fall & ~BIT(d->hwirq));
++ rt_gpio_w32(rg, GPIO_REG_RENA, rise & ~BIT(d->hwirq));
++ spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
++{
++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
++ struct ralink_gpio_chip *rg = gpiochip_get_data(gc);
++ u32 mask = BIT(d->hwirq);
++
++ if (type == IRQ_TYPE_PROBE) {
++ if ((rg->rising | rg->falling) & mask)
++ return 0;
++
++ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
++ }
++
++ if (type & IRQ_TYPE_EDGE_RISING)
++ rg->rising |= mask;
++ else
++ rg->rising &= ~mask;
++
++ if (type & IRQ_TYPE_EDGE_FALLING)
++ rg->falling |= mask;
++ else
++ rg->falling &= ~mask;
++
++ return 0;
++}
++
++static struct irq_chip ralink_gpio_irq_chip = {
++ .name = "gpio-ralink",
++ .irq_unmask = ralink_gpio_irq_unmask,
++ .irq_mask = ralink_gpio_irq_mask,
++ .irq_mask_ack = ralink_gpio_irq_mask,
++ .irq_set_type = ralink_gpio_irq_type,
++ .flags = IRQCHIP_IMMUTABLE,
++ GPIOCHIP_IRQ_RESOURCE_HELPERS,
++};
++
++static int ralink_gpio_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ struct ralink_gpio_chip *rg;
++ int ret;
++
++ rg = devm_kzalloc(dev, sizeof(struct ralink_gpio_chip), GFP_KERNEL);
++ if (!rg)
++ return -ENOMEM;
++
++ rg->membase = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(rg->membase))
++ return PTR_ERR(rg->membase);
++
++ if (of_property_read_u8_array(np, "ralink,register-map",
++ rg->regs, GPIO_REG_MAX)) {
++ dev_err(dev, "failed to read register definition\n");
++ return -EINVAL;
++ }
++
++ spin_lock_init(&rg->lock);
++
++ ret = bgpio_init(&rg->chip, dev, 4,
++ rg->membase + rg->regs[GPIO_REG_DATA],
++ rg->membase + rg->regs[GPIO_REG_SET],
++ rg->membase + rg->regs[GPIO_REG_RESET],
++ rg->membase + rg->regs[GPIO_REG_DIR],
++ NULL, 0);
++ if (ret)
++ return dev_err_probe(dev, ret, "bgpio_init() failed\n");
++
++ /* set polarity to low for all lines */
++ rt_gpio_w32(rg, GPIO_REG_POL, 0);
++
++ rg->gpio_irq = platform_get_irq(pdev, 0);
++ if (rg->gpio_irq < 0)
++ return rg->gpio_irq;
++
++ if (rg->gpio_irq) {
++ struct gpio_irq_chip *girq;
++
++ /*
++ * Directly request the irq here instead of passing
++ * a flow-handler because the irq is shared.
++ */
++ ret = devm_request_irq(dev, rg->gpio_irq,
++ ralink_gpio_irq_handler, IRQF_SHARED,
++ NULL, &rg->chip);
++ if (ret) {
++ dev_err(dev, "Error requesting IRQ %d: %d\n",
++ rg->gpio_irq, ret);
++ return ret;
++ }
++
++ girq = &rg->chip.irq;
++ gpio_irq_chip_set_chip(girq, &ralink_gpio_irq_chip);
++ /* This will let us handle the parent IRQ in the driver */
++ girq->parent_handler = NULL;
++ girq->num_parents = 0;
++ girq->parents = NULL;
++ girq->default_type = IRQ_TYPE_NONE;
++ girq->handler = handle_simple_irq;
++
++ rt_gpio_w32(rg, GPIO_REG_RENA, 0);
++ rt_gpio_w32(rg, GPIO_REG_FENA, 0);
++ }
++
++ return devm_gpiochip_add_data(dev, &rg->chip, rg);
++}
++
++static const struct of_device_id ralink_gpio_match[] = {
++ { .compatible = "ralink,rt2880-gpio" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ralink_gpio_match);
++
++static struct platform_driver ralink_gpio_driver = {
++ .probe = ralink_gpio_probe,
++ .driver = {
++ .name = "ralink_gpio",
++ .of_match_table = ralink_gpio_match,
++ },
++};
++
++static int __init ralink_gpio_init(void)
++{
++ return platform_driver_register(&ralink_gpio_driver);
++}
++
++subsys_initcall(ralink_gpio_init);
--- /dev/null
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Mon, 27 May 2024 08:25:57 +0000
+Subject: [PATCH] dma: ralink: add back gdma driver
+
+The upstream staging driver has been removed[1] since kernel v5.17.
+
+[1] 5bfc10690c6c ("staging: ralink-gdma: remove driver from tree")
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/dma/Kconfig | 6 ++++++
+ drivers/dma/Makefile | 1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/dma/Kconfig
++++ b/drivers/dma/Kconfig
+@@ -532,6 +532,12 @@ config PLX_DMA
+ These are exposed via extra functions on the switch's
+ upstream port. Each function exposes one DMA channel.
+
++config RALINK_GDMA
++ tristate "RALINK GDMA support"
++ depends on RALINK && !SOC_RT288X
++ select DMA_ENGINE
++ select DMA_VIRTUAL_CHANNELS
++
+ config STE_DMA40
+ bool "ST-Ericsson DMA40 support"
+ depends on ARCH_U8500
+--- a/drivers/dma/Makefile
++++ b/drivers/dma/Makefile
+@@ -64,6 +64,7 @@ obj-$(CONFIG_PL330_DMA) += pl330.o
+ obj-$(CONFIG_PLX_DMA) += plx_dma.o
+ obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
+ obj-$(CONFIG_PXA_DMA) += pxa_dma.o
++obj-$(CONFIG_RALINK_GDMA) += ralink-gdma.o
+ obj-$(CONFIG_RENESAS_DMA) += sh/
+ obj-$(CONFIG_SF_PDMA) += sf-pdma/
+ obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
--- /dev/null
+From 576623d706613feec2392ef16b84e23a46200552 Mon Sep 17 00:00:00 2001
+From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
+Date: Fri, 1 Mar 2024 14:29:24 +0100
+Subject: [PATCH] pinctrl: Add driver for Awinic AW9523/B I2C GPIO Expander
+
+The Awinic AW9523(B) is a multi-function I2C gpio expander in a
+TQFN-24L package, featuring PWM (max 37mA per pin, or total max
+power 3.2Watts) for LED driving capability.
+
+It has two ports with 8 pins per port (for a total of 16 pins),
+configurable as either PWM with 1/256 stepping or GPIO input/output,
+1.8V logic input; each GPIO can be configured as input or output
+independently from each other.
+
+This IC also has an internal interrupt controller, which is capable
+of generating an interrupt for each GPIO, depending on the
+configuration, and will raise an interrupt on the INTN pin to
+advertise this to an external interrupt controller.
+
+Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
+Signed-off-by: David Bauer <mail@david-bauer.net>
+Link: https://lore.kernel.org/r/20210624214458.68716-2-mail@david-bauer.net
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20240301-awinic-aw9523-v8-1-7ec572f5dfb4@linaro.org
+---
+ drivers/pinctrl/Kconfig | 18 +
+ drivers/pinctrl/Makefile | 1 +
+ drivers/pinctrl/pinctrl-aw9523.c | 1118 ++++++++++++++++++++++++++++++
+ 3 files changed, 1137 insertions(+)
+ create mode 100644 drivers/pinctrl/pinctrl-aw9523.c
+
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -127,6 +127,24 @@ config PINCTRL_AXP209
+ selected.
+ Say Y to enable pinctrl and GPIO support for the AXP209 PMIC.
+
++config PINCTRL_AW9523
++ bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver"
++ depends on OF && I2C
++ select PINMUX
++ select PINCONF
++ select GENERIC_PINCONF
++ select GPIOLIB
++ select GPIOLIB_IRQCHIP
++ select REGMAP
++ select REGMAP_I2C
++ help
++ The Awinic AW9523/AW9523B is a multi-function I2C GPIO
++ expander with PWM functionality. This driver bundles a
++ pinctrl driver to select the function muxing and a GPIO
++ driver to handle GPIO, when the GPIO function is selected.
++
++ Say yes to enable pinctrl and GPIO support for the AW9523(B).
++
+ config PINCTRL_BM1880
+ bool "Bitmain BM1880 Pinctrl driver"
+ depends on OF && (ARCH_BITMAIN || COMPILE_TEST)
+--- a/drivers/pinctrl/Makefile
++++ b/drivers/pinctrl/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl
+ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
+ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
+ obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
++obj-$(CONFIG_PINCTRL_AW9523) += pinctrl-aw9523.o
+ obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
+ obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
+ obj-$(CONFIG_PINCTRL_CY8C95X0) += pinctrl-cy8c95x0.o
+--- /dev/null
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -0,0 +1,1118 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Awinic AW9523B i2c pin controller driver
++ * Copyright (c) 2020, AngeloGioacchino Del Regno
++ * <angelogioacchino.delregno@somainline.org>
++ */
++
++#include <linux/bitfield.h>
++#include <linux/gpio/consumer.h>
++#include <linux/gpio/driver.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/mutex.h>
++#include <linux/module.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/property.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/slab.h>
++
++#define AW9523_MAX_FUNCS 2
++#define AW9523_NUM_PORTS 2
++#define AW9523_PINS_PER_PORT 8
++
++/*
++ * HW needs at least 20uS for reset and at least 1-2uS to recover from
++ * reset, but we have to account for eventual board quirks, if any:
++ * for this reason, keep reset asserted for 50uS and wait for 20uS
++ * to recover from the reset.
++ */
++#define AW9523_HW_RESET_US 50
++#define AW9523_HW_RESET_RECOVERY_US 20
++
++/* Port 0: P0_0...P0_7 - Port 1: P1_0...P1_7 */
++#define AW9523_PIN_TO_PORT(pin) (pin >> 3)
++#define AW9523_REG_IN_STATE(pin) (0x00 + AW9523_PIN_TO_PORT(pin))
++#define AW9523_REG_OUT_STATE(pin) (0x02 + AW9523_PIN_TO_PORT(pin))
++#define AW9523_REG_CONF_STATE(pin) (0x04 + AW9523_PIN_TO_PORT(pin))
++#define AW9523_REG_INTR_DIS(pin) (0x06 + AW9523_PIN_TO_PORT(pin))
++#define AW9523_REG_CHIPID 0x10
++#define AW9523_VAL_EXPECTED_CHIPID 0x23
++
++#define AW9523_REG_GCR 0x11
++#define AW9523_GCR_ISEL_MASK GENMASK(0, 1)
++#define AW9523_GCR_GPOMD_MASK BIT(4)
++
++#define AW9523_REG_PORT_MODE(pin) (0x12 + AW9523_PIN_TO_PORT(pin))
++#define AW9523_REG_SOFT_RESET 0x7f
++#define AW9523_VAL_RESET 0x00
++
++/*
++ * struct aw9523_irq - Interrupt controller structure
++ * @lock: mutex locking for the irq bus
++ * @irqchip: structure holding irqchip params
++ * @cached_gpio: stores the previous gpio status for bit comparison
++ */
++struct aw9523_irq {
++ struct mutex lock;
++ struct irq_chip *irqchip;
++ u16 cached_gpio;
++};
++
++/*
++ * struct aw9523_pinmux - Pin mux params
++ * @name: Name of the mux
++ * @grps: Groups of the mux
++ * @num_grps: Number of groups (sizeof array grps)
++ */
++struct aw9523_pinmux {
++ const char *name;
++ const char * const *grps;
++ const u8 num_grps;
++};
++
++/*
++ * struct aw9523 - Main driver structure
++ * @dev: device handle
++ * @regmap: regmap handle for current device
++ * @i2c_lock: Mutex lock for i2c operations
++ * @reset_gpio: Hardware reset (RSTN) signal GPIO
++ * @vio_vreg: VCC regulator (Optional)
++ * @pctl: pinctrl handle for current device
++ * @gpio: structure holding gpiochip params
++ * @irq: Interrupt controller structure
++ */
++struct aw9523 {
++ struct device *dev;
++ struct regmap *regmap;
++ struct mutex i2c_lock;
++ struct gpio_desc *reset_gpio;
++ struct regulator *vio_vreg;
++ struct pinctrl_dev *pctl;
++ struct gpio_chip gpio;
++ struct aw9523_irq *irq;
++};
++
++static const struct pinctrl_pin_desc aw9523_pins[] = {
++ /* Port 0 */
++ PINCTRL_PIN(0, "gpio0"),
++ PINCTRL_PIN(1, "gpio1"),
++ PINCTRL_PIN(2, "gpio2"),
++ PINCTRL_PIN(3, "gpio3"),
++ PINCTRL_PIN(4, "gpio4"),
++ PINCTRL_PIN(5, "gpio5"),
++ PINCTRL_PIN(6, "gpio6"),
++ PINCTRL_PIN(7, "gpio7"),
++
++ /* Port 1 */
++ PINCTRL_PIN(8, "gpio8"),
++ PINCTRL_PIN(9, "gpio9"),
++ PINCTRL_PIN(10, "gpio10"),
++ PINCTRL_PIN(11, "gpio11"),
++ PINCTRL_PIN(12, "gpio12"),
++ PINCTRL_PIN(13, "gpio13"),
++ PINCTRL_PIN(14, "gpio14"),
++ PINCTRL_PIN(15, "gpio15"),
++};
++
++static int aw9523_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
++{
++ return ARRAY_SIZE(aw9523_pins);
++}
++
++static const char *aw9523_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
++ unsigned int selector)
++{
++ return aw9523_pins[selector].name;
++}
++
++static int aw9523_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
++ unsigned int selector,
++ const unsigned int **pins,
++ unsigned int *num_pins)
++{
++ *pins = &aw9523_pins[selector].number;
++ *num_pins = 1;
++ return 0;
++}
++
++static const struct pinctrl_ops aw9523_pinctrl_ops = {
++ .get_groups_count = aw9523_pinctrl_get_groups_count,
++ .get_group_pins = aw9523_pinctrl_get_group_pins,
++ .get_group_name = aw9523_pinctrl_get_group_name,
++ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
++ .dt_free_map = pinconf_generic_dt_free_map,
++};
++
++static const char * const gpio_pwm_groups[] = {
++ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
++ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
++ "gpio12", "gpio13", "gpio14", "gpio15"
++};
++
++/* Warning: Do NOT reorder this array */
++static const struct aw9523_pinmux aw9523_pmx[] = {
++ {
++ .name = "pwm",
++ .grps = gpio_pwm_groups,
++ .num_grps = ARRAY_SIZE(gpio_pwm_groups),
++ },
++ {
++ .name = "gpio",
++ .grps = gpio_pwm_groups,
++ .num_grps = ARRAY_SIZE(gpio_pwm_groups),
++ },
++};
++
++static int aw9523_pmx_get_funcs_count(struct pinctrl_dev *pctl)
++{
++ return ARRAY_SIZE(aw9523_pmx);
++}
++
++static const char *aw9523_pmx_get_fname(struct pinctrl_dev *pctl,
++ unsigned int sel)
++{
++ return aw9523_pmx[sel].name;
++}
++
++static int aw9523_pmx_get_groups(struct pinctrl_dev *pctl, unsigned int sel,
++ const char * const **groups,
++ unsigned int * const num_groups)
++{
++ *groups = aw9523_pmx[sel].grps;
++ *num_groups = aw9523_pmx[sel].num_grps;
++ return 0;
++}
++
++static int aw9523_pmx_set_mux(struct pinctrl_dev *pctl, unsigned int fsel,
++ unsigned int grp)
++{
++ struct aw9523 *awi = pinctrl_dev_get_drvdata(pctl);
++ int ret, pin = aw9523_pins[grp].number % AW9523_PINS_PER_PORT;
++
++ if (fsel >= ARRAY_SIZE(aw9523_pmx))
++ return -EINVAL;
++
++ /*
++ * This maps directly to the aw9523_pmx array: programming a
++ * high bit means "gpio" and a low bit means "pwm".
++ */
++ mutex_lock(&awi->i2c_lock);
++ ret = regmap_update_bits(awi->regmap, AW9523_REG_PORT_MODE(pin),
++ BIT(pin), (fsel ? BIT(pin) : 0));
++ mutex_unlock(&awi->i2c_lock);
++ return ret;
++}
++
++static const struct pinmux_ops aw9523_pinmux_ops = {
++ .get_functions_count = aw9523_pmx_get_funcs_count,
++ .get_function_name = aw9523_pmx_get_fname,
++ .get_function_groups = aw9523_pmx_get_groups,
++ .set_mux = aw9523_pmx_set_mux,
++};
++
++static int aw9523_pcfg_param_to_reg(enum pin_config_param pcp, int pin, u8 *r)
++{
++ u8 reg;
++
++ switch (pcp) {
++ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
++ case PIN_CONFIG_BIAS_PULL_DOWN:
++ case PIN_CONFIG_BIAS_PULL_UP:
++ reg = AW9523_REG_IN_STATE(pin);
++ break;
++ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
++ case PIN_CONFIG_DRIVE_PUSH_PULL:
++ reg = AW9523_REG_GCR;
++ break;
++ case PIN_CONFIG_INPUT_ENABLE:
++ case PIN_CONFIG_OUTPUT_ENABLE:
++ reg = AW9523_REG_CONF_STATE(pin);
++ break;
++ case PIN_CONFIG_OUTPUT:
++ reg = AW9523_REG_OUT_STATE(pin);
++ break;
++ default:
++ return -EOPNOTSUPP;
++ }
++ *r = reg;
++
++ return 0;
++}
++
++static int aw9523_pconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
++ unsigned long *config)
++{
++ struct aw9523 *awi = pinctrl_dev_get_drvdata(pctldev);
++ enum pin_config_param param = pinconf_to_config_param(*config);
++ int regbit = pin % AW9523_PINS_PER_PORT;
++ unsigned int val;
++ u8 reg;
++ int rc;
++
++ rc = aw9523_pcfg_param_to_reg(param, pin, ®);
++ if (rc)
++ return rc;
++
++ mutex_lock(&awi->i2c_lock);
++ rc = regmap_read(awi->regmap, reg, &val);
++ mutex_unlock(&awi->i2c_lock);
++ if (rc)
++ return rc;
++
++ switch (param) {
++ case PIN_CONFIG_BIAS_PULL_UP:
++ case PIN_CONFIG_INPUT_ENABLE:
++ case PIN_CONFIG_OUTPUT:
++ val &= BIT(regbit);
++ break;
++ case PIN_CONFIG_BIAS_PULL_DOWN:
++ case PIN_CONFIG_OUTPUT_ENABLE:
++ val &= BIT(regbit);
++ val = !val;
++ break;
++ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
++ if (pin >= AW9523_PINS_PER_PORT)
++ val = 0;
++ else
++ val = !FIELD_GET(AW9523_GCR_GPOMD_MASK, val);
++ break;
++ case PIN_CONFIG_DRIVE_PUSH_PULL:
++ if (pin >= AW9523_PINS_PER_PORT)
++ val = 1;
++ else
++ val = FIELD_GET(AW9523_GCR_GPOMD_MASK, val);
++ break;
++ default:
++ return -EOPNOTSUPP;
++ }
++ if (val < 1)
++ return -EINVAL;
++
++ *config = pinconf_to_config_packed(param, !!val);
++
++ return rc;
++}
++
++static int aw9523_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
++ unsigned long *configs, unsigned int num_configs)
++{
++ struct aw9523 *awi = pinctrl_dev_get_drvdata(pctldev);
++ enum pin_config_param param;
++ int regbit = pin % AW9523_PINS_PER_PORT;
++ u32 arg;
++ u8 reg;
++ unsigned int mask, val;
++ int i, rc;
++
++ mutex_lock(&awi->i2c_lock);
++ for (i = 0; i < num_configs; i++) {
++ param = pinconf_to_config_param(configs[i]);
++ arg = pinconf_to_config_argument(configs[i]);
++
++ rc = aw9523_pcfg_param_to_reg(param, pin, ®);
++ if (rc)
++ goto end;
++
++ switch (param) {
++ case PIN_CONFIG_OUTPUT:
++ /* First, enable pin output */
++ rc = regmap_update_bits(awi->regmap,
++ AW9523_REG_CONF_STATE(pin),
++ BIT(regbit), 0);
++ if (rc)
++ goto end;
++
++ /* Then, fall through to config output level */
++ fallthrough;
++ case PIN_CONFIG_OUTPUT_ENABLE:
++ arg = !arg;
++ fallthrough;
++ case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
++ case PIN_CONFIG_BIAS_PULL_DOWN:
++ case PIN_CONFIG_BIAS_PULL_UP:
++ case PIN_CONFIG_INPUT_ENABLE:
++ mask = BIT(regbit);
++ val = arg ? BIT(regbit) : 0;
++ break;
++ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
++ /* Open-Drain is supported only on port 0 */
++ if (pin >= AW9523_PINS_PER_PORT) {
++ rc = -EOPNOTSUPP;
++ goto end;
++ }
++ mask = AW9523_GCR_GPOMD_MASK;
++ val = 0;
++ break;
++ case PIN_CONFIG_DRIVE_PUSH_PULL:
++ /* Port 1 is always Push-Pull */
++ if (pin >= AW9523_PINS_PER_PORT) {
++ mask = 0;
++ val = 0;
++ continue;
++ }
++ mask = AW9523_GCR_GPOMD_MASK;
++ val = AW9523_GCR_GPOMD_MASK;
++ break;
++ default:
++ rc = -EOPNOTSUPP;
++ goto end;
++ }
++
++ rc = regmap_update_bits(awi->regmap, reg, mask, val);
++ if (rc)
++ goto end;
++ }
++end:
++ mutex_unlock(&awi->i2c_lock);
++ return rc;
++}
++
++static const struct pinconf_ops aw9523_pinconf_ops = {
++ .pin_config_get = aw9523_pconf_get,
++ .pin_config_set = aw9523_pconf_set,
++ .is_generic = true,
++};
++
++/*
++ * aw9523_get_pin_direction - Get pin direction
++ * @regmap: Regmap structure
++ * @pin: gpiolib pin number
++ * @n: pin index in port register
++ *
++ * Return: Pin direction for success or negative number for error
++ */
++static int aw9523_get_pin_direction(struct regmap *regmap, u8 pin, u8 n)
++{
++ int ret;
++
++ ret = regmap_test_bits(regmap, AW9523_REG_CONF_STATE(pin), BIT(n));
++ if (ret < 0)
++ return ret;
++
++ return ret ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
++}
++
++/*
++ * aw9523_get_port_state - Get input or output state for entire port
++ * @regmap: Regmap structure
++ * @pin: gpiolib pin number
++ * @regbit: hw pin index, used to retrieve port number
++ * @state: returned port state
++ *
++ * Return: Zero for success or negative number for error
++ */
++static int aw9523_get_port_state(struct regmap *regmap, u8 pin,
++ u8 regbit, unsigned int *state)
++{
++ u8 reg;
++ int dir;
++
++ dir = aw9523_get_pin_direction(regmap, pin, regbit);
++ if (dir < 0)
++ return dir;
++
++ if (dir == GPIO_LINE_DIRECTION_IN)
++ reg = AW9523_REG_IN_STATE(pin);
++ else
++ reg = AW9523_REG_OUT_STATE(pin);
++
++ return regmap_read(regmap, reg, state);
++}
++
++static int aw9523_gpio_irq_type(struct irq_data *d, unsigned int type)
++{
++ switch (type) {
++ case IRQ_TYPE_NONE:
++ case IRQ_TYPE_EDGE_BOTH:
++ return 0;
++ default:
++ return -EINVAL;
++ };
++}
++
++/*
++ * aw9523_irq_mask - Mask interrupt
++ * @d: irq data
++ *
++ * Sets which interrupt to mask in the bitmap;
++ * The interrupt will be masked when unlocking the irq bus.
++ */
++static void aw9523_irq_mask(struct irq_data *d)
++{
++ struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
++ unsigned int n = d->hwirq % AW9523_PINS_PER_PORT;
++
++ regmap_update_bits(awi->regmap,
++ AW9523_REG_INTR_DIS(d->hwirq),
++ BIT(n), BIT(n));
++ gpiochip_disable_irq(&awi->gpio, irqd_to_hwirq(d));
++}
++
++/*
++ * aw9523_irq_unmask - Unmask interrupt
++ * @d: irq data
++ *
++ * Sets which interrupt to unmask in the bitmap;
++ * The interrupt will be masked when unlocking the irq bus.
++ */
++static void aw9523_irq_unmask(struct irq_data *d)
++{
++ struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
++ unsigned int n = d->hwirq % AW9523_PINS_PER_PORT;
++
++ gpiochip_enable_irq(&awi->gpio, irqd_to_hwirq(d));
++ regmap_update_bits(awi->regmap,
++ AW9523_REG_INTR_DIS(d->hwirq),
++ BIT(n), 0);
++}
++
++static irqreturn_t aw9523_irq_thread_func(int irq, void *dev_id)
++{
++ struct aw9523 *awi = (struct aw9523 *)dev_id;
++ unsigned long n, val = 0;
++ unsigned long changed_gpio;
++ unsigned int tmp, port_pin, i, ret;
++
++ for (i = 0; i < AW9523_NUM_PORTS; i++) {
++ port_pin = i * AW9523_PINS_PER_PORT;
++ ret = regmap_read(awi->regmap,
++ AW9523_REG_IN_STATE(port_pin),
++ &tmp);
++ if (ret)
++ return ret;
++ val |= (u8)tmp << (i * 8);
++ }
++
++ /* Handle GPIO input release interrupt as well */
++ changed_gpio = awi->irq->cached_gpio ^ val;
++ awi->irq->cached_gpio = val;
++
++ /*
++ * To avoid up to four *slow* i2c reads from any driver hooked
++ * up to our interrupts, just check for the irq_find_mapping
++ * result: if the interrupt is not mapped, then we don't want
++ * to care about it.
++ */
++ for_each_set_bit(n, &changed_gpio, awi->gpio.ngpio) {
++ tmp = irq_find_mapping(awi->gpio.irq.domain, n);
++ if (tmp <= 0)
++ continue;
++ handle_nested_irq(tmp);
++ }
++
++ return IRQ_HANDLED;
++}
++
++/*
++ * aw9523_irq_bus_lock - Grab lock for interrupt operation
++ * @d: irq data
++ */
++static void aw9523_irq_bus_lock(struct irq_data *d)
++{
++ struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
++
++ mutex_lock(&awi->irq->lock);
++ regcache_cache_only(awi->regmap, true);
++}
++
++/*
++ * aw9523_irq_bus_sync_unlock - Synchronize state and unlock
++ * @d: irq data
++ *
++ * Writes the interrupt mask bits (found in the bit map) to the
++ * hardware, then unlocks the bus.
++ */
++static void aw9523_irq_bus_sync_unlock(struct irq_data *d)
++{
++ struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
++
++ regcache_cache_only(awi->regmap, false);
++ regcache_sync(awi->regmap);
++ mutex_unlock(&awi->irq->lock);
++}
++
++static int aw9523_gpio_get_direction(struct gpio_chip *chip,
++ unsigned int offset)
++{
++ struct aw9523 *awi = gpiochip_get_data(chip);
++ u8 regbit = offset % AW9523_PINS_PER_PORT;
++ int ret;
++
++ mutex_lock(&awi->i2c_lock);
++ ret = aw9523_get_pin_direction(awi->regmap, offset, regbit);
++ mutex_unlock(&awi->i2c_lock);
++
++ return ret;
++}
++
++static int aw9523_gpio_get(struct gpio_chip *chip, unsigned int offset)
++{
++ struct aw9523 *awi = gpiochip_get_data(chip);
++ u8 regbit = offset % AW9523_PINS_PER_PORT;
++ unsigned int val;
++ int ret;
++
++ mutex_lock(&awi->i2c_lock);
++ ret = aw9523_get_port_state(awi->regmap, offset, regbit, &val);
++ mutex_unlock(&awi->i2c_lock);
++ if (ret)
++ return ret;
++
++ return !!(val & BIT(regbit));
++}
++
++/**
++ * _aw9523_gpio_get_multiple - Get I/O state for an entire port
++ * @regmap: Regmap structure
++ * @pin: gpiolib pin number
++ * @regbit: hw pin index, used to retrieve port number
++ * @state: returned port I/O state
++ *
++ * Return: Zero for success or negative number for error
++ */
++static int _aw9523_gpio_get_multiple(struct aw9523 *awi, u8 regbit,
++ u8 *state, u8 mask)
++{
++ u32 dir_in, val;
++ u8 m;
++ int ret;
++
++ /* Registers are 8-bits wide */
++ ret = regmap_read(awi->regmap, AW9523_REG_CONF_STATE(regbit), &dir_in);
++ if (ret)
++ return ret;
++ *state = 0;
++
++ m = mask & dir_in;
++ if (m) {
++ ret = regmap_read(awi->regmap, AW9523_REG_IN_STATE(regbit),
++ &val);
++ if (ret)
++ return ret;
++ *state |= (u8)val & m;
++ }
++
++ m = mask & ~dir_in;
++ if (m) {
++ ret = regmap_read(awi->regmap, AW9523_REG_OUT_STATE(regbit),
++ &val);
++ if (ret)
++ return ret;
++ *state |= (u8)val & m;
++ }
++
++ return 0;
++}
++
++static int aw9523_gpio_get_multiple(struct gpio_chip *chip,
++ unsigned long *mask,
++ unsigned long *bits)
++{
++ struct aw9523 *awi = gpiochip_get_data(chip);
++ u8 m, state = 0;
++ int ret;
++
++ mutex_lock(&awi->i2c_lock);
++
++ /* Port 0 (gpio 0-7) */
++ m = *mask & U8_MAX;
++ if (m) {
++ ret = _aw9523_gpio_get_multiple(awi, 0, &state, m);
++ if (ret)
++ goto out;
++ }
++ *bits = state;
++
++ /* Port 1 (gpio 8-15) */
++ m = (*mask >> 8) & U8_MAX;
++ if (m) {
++ ret = _aw9523_gpio_get_multiple(awi, AW9523_PINS_PER_PORT,
++ &state, m);
++ if (ret)
++ goto out;
++
++ *bits |= (state << 8);
++ }
++out:
++ mutex_unlock(&awi->i2c_lock);
++ return ret;
++}
++
++static void aw9523_gpio_set_multiple(struct gpio_chip *chip,
++ unsigned long *mask,
++ unsigned long *bits)
++{
++ struct aw9523 *awi = gpiochip_get_data(chip);
++ u8 mask_lo, mask_hi, bits_lo, bits_hi;
++ unsigned int reg;
++ int ret = 0;
++
++ mask_lo = *mask & U8_MAX;
++ mask_hi = (*mask >> 8) & U8_MAX;
++ mutex_lock(&awi->i2c_lock);
++ if (mask_hi) {
++ reg = AW9523_REG_OUT_STATE(AW9523_PINS_PER_PORT);
++ bits_hi = (*bits >> 8) & U8_MAX;
++
++ ret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi);
++ if (ret) {
++ dev_warn(awi->dev, "Cannot write port1 out level\n");
++ goto out;
++ }
++ }
++ if (mask_lo) {
++ reg = AW9523_REG_OUT_STATE(0);
++ bits_lo = *bits & U8_MAX;
++ ret = regmap_write_bits(awi->regmap, reg, mask_lo, bits_lo);
++ if (ret)
++ dev_warn(awi->dev, "Cannot write port0 out level\n");
++ }
++out:
++ mutex_unlock(&awi->i2c_lock);
++}
++
++static void aw9523_gpio_set(struct gpio_chip *chip,
++ unsigned int offset, int value)
++{
++ struct aw9523 *awi = gpiochip_get_data(chip);
++ u8 regbit = offset % AW9523_PINS_PER_PORT;
++
++ mutex_lock(&awi->i2c_lock);
++ regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),
++ BIT(regbit), value ? BIT(regbit) : 0);
++ mutex_unlock(&awi->i2c_lock);
++}
++
++
++static int aw9523_direction_input(struct gpio_chip *chip, unsigned int offset)
++{
++ struct aw9523 *awi = gpiochip_get_data(chip);
++ u8 regbit = offset % AW9523_PINS_PER_PORT;
++ int ret;
++
++ mutex_lock(&awi->i2c_lock);
++ ret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset),
++ BIT(regbit), BIT(regbit));
++ mutex_unlock(&awi->i2c_lock);
++
++ return ret;
++}
++
++static int aw9523_direction_output(struct gpio_chip *chip,
++ unsigned int offset, int value)
++{
++ struct aw9523 *awi = gpiochip_get_data(chip);
++ u8 regbit = offset % AW9523_PINS_PER_PORT;
++ int ret;
++
++ mutex_lock(&awi->i2c_lock);
++ ret = regmap_update_bits(awi->regmap, AW9523_REG_OUT_STATE(offset),
++ BIT(regbit), value ? BIT(regbit) : 0);
++ if (ret)
++ goto end;
++
++ ret = regmap_update_bits(awi->regmap, AW9523_REG_CONF_STATE(offset),
++ BIT(regbit), 0);
++end:
++ mutex_unlock(&awi->i2c_lock);
++ return ret;
++}
++
++static int aw9523_drive_reset_gpio(struct aw9523 *awi)
++{
++ unsigned int chip_id;
++ int ret;
++
++ /*
++ * If the chip is already configured for any reason, then we
++ * will probably succeed in sending the soft reset signal to
++ * the hardware through I2C: this operation takes less time
++ * compared to a full HW reset and it gives the same results.
++ */
++ ret = regmap_write(awi->regmap, AW9523_REG_SOFT_RESET, 0);
++ if (ret == 0)
++ goto done;
++
++ dev_dbg(awi->dev, "Cannot execute soft reset: trying hard reset\n");
++ ret = gpiod_direction_output(awi->reset_gpio, 0);
++ if (ret)
++ return ret;
++
++ /* The reset pulse has to be longer than 20uS due to deglitch */
++ usleep_range(AW9523_HW_RESET_US, AW9523_HW_RESET_US + 1);
++
++ ret = gpiod_direction_output(awi->reset_gpio, 1);
++ if (ret)
++ return ret;
++done:
++ /* The HW needs at least 1uS to reliably recover after reset */
++ usleep_range(AW9523_HW_RESET_RECOVERY_US,
++ AW9523_HW_RESET_RECOVERY_US + 1);
++
++ /* Check the ChipID */
++ ret = regmap_read(awi->regmap, AW9523_REG_CHIPID, &chip_id);
++ if (ret) {
++ dev_err(awi->dev, "Cannot read Chip ID: %d\n", ret);
++ return ret;
++ }
++ if (chip_id != AW9523_VAL_EXPECTED_CHIPID) {
++ dev_err(awi->dev, "Bad ChipID; read 0x%x, expected 0x%x\n",
++ chip_id, AW9523_VAL_EXPECTED_CHIPID);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++static int aw9523_hw_reset(struct aw9523 *awi)
++{
++ int ret, max_retries = 2;
++
++ /* Sometimes the chip needs more than one reset cycle */
++ do {
++ ret = aw9523_drive_reset_gpio(awi);
++ if (ret == 0)
++ break;
++ max_retries--;
++ } while (max_retries);
++
++ return ret;
++}
++
++static int aw9523_init_gpiochip(struct aw9523 *awi, unsigned int npins)
++{
++ struct device *dev = awi->dev;
++ struct gpio_chip *gc = &awi->gpio;
++
++ gc->label = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
++ if (!gc->label)
++ return -ENOMEM;
++
++ gc->base = -1;
++ gc->ngpio = npins;
++ gc->get_direction = aw9523_gpio_get_direction;
++ gc->direction_input = aw9523_direction_input;
++ gc->direction_output = aw9523_direction_output;
++ gc->get = aw9523_gpio_get;
++ gc->get_multiple = aw9523_gpio_get_multiple;
++ gc->set = aw9523_gpio_set;
++ gc->set_multiple = aw9523_gpio_set_multiple;
++ gc->set_config = gpiochip_generic_config;
++ gc->parent = dev;
++ gc->owner = THIS_MODULE;
++ gc->can_sleep = false;
++
++ return 0;
++}
++
++static const struct irq_chip aw9523_irq_chip = {
++ .name = "aw9523",
++ .irq_mask = aw9523_irq_mask,
++ .irq_unmask = aw9523_irq_unmask,
++ .irq_bus_lock = aw9523_irq_bus_lock,
++ .irq_bus_sync_unlock = aw9523_irq_bus_sync_unlock,
++ .irq_set_type = aw9523_gpio_irq_type,
++ .flags = IRQCHIP_IMMUTABLE,
++ GPIOCHIP_IRQ_RESOURCE_HELPERS,
++};
++
++static int aw9523_init_irq(struct aw9523 *awi, int irq)
++{
++ struct device *dev = awi->dev;
++ struct gpio_irq_chip *girq;
++ struct irq_chip *irqchip;
++ int ret;
++
++ if (!device_property_read_bool(dev, "interrupt-controller"))
++ return 0;
++
++ irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
++ if (!irqchip)
++ return -ENOMEM;
++
++ awi->irq = devm_kzalloc(dev, sizeof(*awi->irq), GFP_KERNEL);
++ if (!awi->irq)
++ return -ENOMEM;
++
++ awi->irq->irqchip = irqchip;
++ mutex_init(&awi->irq->lock);
++
++ ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func,
++ IRQF_ONESHOT, dev_name(dev), awi);
++ if (ret) {
++ dev_err(dev, "Failed to request irq %d\n", irq);
++ return ret;
++ }
++
++ girq = &awi->gpio.irq;
++ gpio_irq_chip_set_chip(girq, &aw9523_irq_chip);
++ girq->parent_handler = NULL;
++ girq->num_parents = 0;
++ girq->parents = NULL;
++ girq->default_type = IRQ_TYPE_EDGE_BOTH;
++ girq->handler = handle_simple_irq;
++ girq->threaded = true;
++
++ return 0;
++}
++
++static bool aw9523_is_reg_hole(unsigned int reg)
++{
++ return (reg > AW9523_REG_PORT_MODE(AW9523_PINS_PER_PORT) &&
++ reg < AW9523_REG_SOFT_RESET) ||
++ (reg > AW9523_REG_INTR_DIS(AW9523_PINS_PER_PORT) &&
++ reg < AW9523_REG_CHIPID);
++}
++
++static bool aw9523_readable_reg(struct device *dev, unsigned int reg)
++{
++ /* All available registers (minus holes) can be read */
++ return !aw9523_is_reg_hole(reg);
++}
++
++static bool aw9523_volatile_reg(struct device *dev, unsigned int reg)
++{
++ return aw9523_is_reg_hole(reg) ||
++ reg == AW9523_REG_IN_STATE(0) ||
++ reg == AW9523_REG_IN_STATE(AW9523_PINS_PER_PORT) ||
++ reg == AW9523_REG_CHIPID ||
++ reg == AW9523_REG_SOFT_RESET;
++}
++
++static bool aw9523_writeable_reg(struct device *dev, unsigned int reg)
++{
++ return !aw9523_is_reg_hole(reg) && reg != AW9523_REG_CHIPID;
++}
++
++static bool aw9523_precious_reg(struct device *dev, unsigned int reg)
++{
++ /* Reading AW9523_REG_IN_STATE clears interrupt status */
++ return aw9523_is_reg_hole(reg) ||
++ reg == AW9523_REG_IN_STATE(0) ||
++ reg == AW9523_REG_IN_STATE(AW9523_PINS_PER_PORT);
++}
++
++static const struct regmap_config aw9523_regmap = {
++ .reg_bits = 8,
++ .val_bits = 8,
++ .reg_stride = 1,
++
++ .precious_reg = aw9523_precious_reg,
++ .readable_reg = aw9523_readable_reg,
++ .volatile_reg = aw9523_volatile_reg,
++ .writeable_reg = aw9523_writeable_reg,
++
++ .cache_type = REGCACHE_FLAT,
++ .disable_locking = true,
++
++ .num_reg_defaults_raw = AW9523_REG_SOFT_RESET,
++};
++
++static int aw9523_hw_init(struct aw9523 *awi)
++{
++ u8 p1_pin = AW9523_PINS_PER_PORT;
++ unsigned int val;
++ int ret;
++
++ /* No register caching during initialization */
++ regcache_cache_bypass(awi->regmap, true);
++
++ /* Bring up the chip */
++ ret = aw9523_hw_reset(awi);
++ if (ret) {
++ dev_err(awi->dev, "HW Reset failed: %d\n", ret);
++ return ret;
++ }
++
++ /*
++ * This is the expected chip and it is running: it's time to
++ * set a safe default configuration in case the user doesn't
++ * configure (all of the available) pins in this chip.
++ * P.S.: The writes order doesn't matter.
++ */
++
++ /* Set all pins as GPIO */
++ ret = regmap_write(awi->regmap, AW9523_REG_PORT_MODE(0), U8_MAX);
++ if (ret)
++ return ret;
++ ret = regmap_write(awi->regmap, AW9523_REG_PORT_MODE(p1_pin), U8_MAX);
++ if (ret)
++ return ret;
++
++ /* Set Open-Drain mode on Port 0 (Port 1 is always P-P) */
++ ret = regmap_write(awi->regmap, AW9523_REG_GCR, 0);
++ if (ret)
++ return ret;
++
++ /* Set all pins as inputs */
++ ret = regmap_write(awi->regmap, AW9523_REG_CONF_STATE(0), U8_MAX);
++ if (ret)
++ return ret;
++ ret = regmap_write(awi->regmap, AW9523_REG_CONF_STATE(p1_pin), U8_MAX);
++ if (ret)
++ return ret;
++
++ /* Disable all interrupts to avoid unreasoned wakeups */
++ ret = regmap_write(awi->regmap, AW9523_REG_INTR_DIS(0), U8_MAX);
++ if (ret)
++ return ret;
++ ret = regmap_write(awi->regmap, AW9523_REG_INTR_DIS(p1_pin), U8_MAX);
++ if (ret)
++ return ret;
++
++ /* Clear setup-generated interrupts by performing a port state read */
++ ret = aw9523_get_port_state(awi->regmap, 0, 0, &val);
++ if (ret)
++ return ret;
++ ret = aw9523_get_port_state(awi->regmap, p1_pin, 0, &val);
++ if (ret)
++ return ret;
++
++ /* Everything went fine: activate and reinitialize register cache */
++ regcache_cache_bypass(awi->regmap, false);
++ return regmap_reinit_cache(awi->regmap, &aw9523_regmap);
++}
++
++static int aw9523_probe(struct i2c_client *client)
++{
++ struct device *dev = &client->dev;
++ struct pinctrl_desc *pdesc;
++ struct aw9523 *awi;
++ int ret;
++
++ awi = devm_kzalloc(dev, sizeof(*awi), GFP_KERNEL);
++ if (!awi)
++ return -ENOMEM;
++
++ i2c_set_clientdata(client, awi);
++
++ awi->dev = dev;
++ awi->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
++ if (IS_ERR(awi->reset_gpio))
++ return PTR_ERR(awi->reset_gpio);
++ gpiod_set_consumer_name(awi->reset_gpio, "aw9523 reset");
++
++ awi->regmap = devm_regmap_init_i2c(client, &aw9523_regmap);
++ if (IS_ERR(awi->regmap))
++ return PTR_ERR(awi->regmap);
++
++ awi->vio_vreg = devm_regulator_get_optional(dev, "vio");
++ if (IS_ERR(awi->vio_vreg)) {
++ if (PTR_ERR(awi->vio_vreg) == -EPROBE_DEFER)
++ return -EPROBE_DEFER;
++ awi->vio_vreg = NULL;
++ } else {
++ ret = regulator_enable(awi->vio_vreg);
++ if (ret)
++ return ret;
++ }
++
++ mutex_init(&awi->i2c_lock);
++ lockdep_set_subclass(&awi->i2c_lock,
++ i2c_adapter_depth(client->adapter));
++
++ pdesc = devm_kzalloc(dev, sizeof(*pdesc), GFP_KERNEL);
++ if (!pdesc)
++ return -ENOMEM;
++
++ ret = aw9523_hw_init(awi);
++ if (ret)
++ goto err_disable_vregs;
++
++ pdesc->name = dev_name(dev);
++ pdesc->owner = THIS_MODULE;
++ pdesc->pctlops = &aw9523_pinctrl_ops;
++ pdesc->pmxops = &aw9523_pinmux_ops;
++ pdesc->confops = &aw9523_pinconf_ops;
++ pdesc->pins = aw9523_pins;
++ pdesc->npins = ARRAY_SIZE(aw9523_pins);
++
++ ret = aw9523_init_gpiochip(awi, pdesc->npins);
++ if (ret)
++ goto err_disable_vregs;
++
++ if (client->irq) {
++ ret = aw9523_init_irq(awi, client->irq);
++ if (ret)
++ goto err_disable_vregs;
++ }
++
++ awi->pctl = devm_pinctrl_register(dev, pdesc, awi);
++ if (IS_ERR(awi->pctl)) {
++ ret = PTR_ERR(awi->pctl);
++ dev_err(dev, "Cannot register pinctrl: %d", ret);
++ goto err_disable_vregs;
++ }
++
++ ret = devm_gpiochip_add_data(dev, &awi->gpio, awi);
++ if (ret)
++ goto err_disable_vregs;
++
++ return ret;
++
++err_disable_vregs:
++ if (awi->vio_vreg)
++ regulator_disable(awi->vio_vreg);
++ mutex_destroy(&awi->i2c_lock);
++ return ret;
++}
++
++static void aw9523_remove(struct i2c_client *client)
++{
++ struct aw9523 *awi = i2c_get_clientdata(client);
++ int ret;
++
++ if (!awi)
++ return;
++
++ /*
++ * If the chip VIO is connected to a regulator that we can turn
++ * off, life is easy... otherwise, reinitialize the chip and
++ * set the pins to hardware defaults before removing the driver
++ * to leave it in a clean, safe and predictable state.
++ */
++ if (awi->vio_vreg) {
++ regulator_disable(awi->vio_vreg);
++ } else {
++ mutex_lock(&awi->i2c_lock);
++ ret = aw9523_hw_init(awi);
++ mutex_unlock(&awi->i2c_lock);
++ if (ret)
++ return;
++ }
++
++ mutex_destroy(&awi->i2c_lock);
++}
++
++static const struct i2c_device_id aw9523_i2c_id_table[] = {
++ { "aw9523_i2c", 0 },
++ { }
++};
++MODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_table);
++
++static const struct of_device_id of_aw9523_i2c_match[] = {
++ { .compatible = "awinic,aw9523-pinctrl", },
++};
++MODULE_DEVICE_TABLE(of, of_aw9523_i2c_match);
++
++static struct i2c_driver aw9523_driver = {
++ .driver = {
++ .name = "aw9523-pinctrl",
++ .of_match_table = of_aw9523_i2c_match,
++ },
++ .probe = aw9523_probe,
++ .remove = aw9523_remove,
++ .id_table = aw9523_i2c_id_table,
++};
++module_i2c_driver(aw9523_driver);
++
++MODULE_DESCRIPTION("Awinic AW9523 I2C GPIO Expander driver");
++MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>");
++MODULE_LICENSE("GPL v2");
--- /dev/null
+From 52279c3d50d964c646692c42a0db87ef7bb451cc Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 6 Mar 2024 08:54:25 +0100
+Subject: [PATCH] pinctrl: aw9523: Add proper terminator
+
+The of_device_id array needs to be terminated with a NULL
+entry.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202403061147.85XYVsk3-lkp@intel.com/
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20240306-fix-aw9523-terminator-v1-1-13f90f87a7f6@linaro.org
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -1099,6 +1099,7 @@ MODULE_DEVICE_TABLE(i2c, aw9523_i2c_id_t
+
+ static const struct of_device_id of_aw9523_i2c_match[] = {
+ { .compatible = "awinic,aw9523-pinctrl", },
++ { }
+ };
+ MODULE_DEVICE_TABLE(of, of_aw9523_i2c_match);
+
--- /dev/null
+From e5e8a58023707472e5dbe9bc7b473a8703b401e0 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andy.shevchenko@gmail.com>
+Date: Fri, 29 Mar 2024 12:55:15 +0200
+Subject: [PATCH] pinctrl: aw9523: Destroy mutex on ->remove()
+
+If aw9523_hw_init() fails on ->remove() the mutex left alive.
+Destroy it in that case as well. While at it, remove never
+true check at the beginning of the function.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-2-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -1067,10 +1067,6 @@ err_disable_vregs:
+ static void aw9523_remove(struct i2c_client *client)
+ {
+ struct aw9523 *awi = i2c_get_clientdata(client);
+- int ret;
+-
+- if (!awi)
+- return;
+
+ /*
+ * If the chip VIO is connected to a regulator that we can turn
+@@ -1082,10 +1078,8 @@ static void aw9523_remove(struct i2c_cli
+ regulator_disable(awi->vio_vreg);
+ } else {
+ mutex_lock(&awi->i2c_lock);
+- ret = aw9523_hw_init(awi);
++ aw9523_hw_init(awi);
+ mutex_unlock(&awi->i2c_lock);
+- if (ret)
+- return;
+ }
+
+ mutex_destroy(&awi->i2c_lock);
--- /dev/null
+From f91eafcb18e096108cd19d24ab71a0db5bc12416 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andy.shevchenko@gmail.com>
+Date: Fri, 29 Mar 2024 12:55:16 +0200
+Subject: [PATCH] pinctrl: aw9523: Use correct error code for not supported
+ functionality
+
+The pin control subsystem internally uses ENOTSUPP for the not supported
+functionality. The checkpatch is false positive about this error code.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-3-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 9 +++++----
+ 1 file changed, 5 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -6,6 +6,7 @@
+ */
+
+ #include <linux/bitfield.h>
++#include <linux/errno.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/gpio/driver.h>
+ #include <linux/i2c.h>
+@@ -239,7 +240,7 @@ static int aw9523_pcfg_param_to_reg(enum
+ reg = AW9523_REG_OUT_STATE(pin);
+ break;
+ default:
+- return -EOPNOTSUPP;
++ return -ENOTSUPP;
+ }
+ *r = reg;
+
+@@ -290,7 +291,7 @@ static int aw9523_pconf_get(struct pinct
+ val = FIELD_GET(AW9523_GCR_GPOMD_MASK, val);
+ break;
+ default:
+- return -EOPNOTSUPP;
++ return -ENOTSUPP;
+ }
+ if (val < 1)
+ return -EINVAL;
+@@ -344,7 +345,7 @@ static int aw9523_pconf_set(struct pinct
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ /* Open-Drain is supported only on port 0 */
+ if (pin >= AW9523_PINS_PER_PORT) {
+- rc = -EOPNOTSUPP;
++ rc = -ENOTSUPP;
+ goto end;
+ }
+ mask = AW9523_GCR_GPOMD_MASK;
+@@ -361,7 +362,7 @@ static int aw9523_pconf_set(struct pinct
+ val = AW9523_GCR_GPOMD_MASK;
+ break;
+ default:
+- rc = -EOPNOTSUPP;
++ rc = -ENOTSUPP;
+ goto end;
+ }
+
--- /dev/null
+From 091655b9285d837db520381924c689bd5dc5d286 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andy.shevchenko@gmail.com>
+Date: Fri, 29 Mar 2024 12:55:17 +0200
+Subject: [PATCH] pinctrl: aw9523: Always try both ports in
+ aw9523_gpio_set_multiple()
+
+The ports are equivalent from the user's point of view. Don't limit
+trying them both if writing to one fails.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-4-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -653,7 +653,7 @@ static void aw9523_gpio_set_multiple(str
+ struct aw9523 *awi = gpiochip_get_data(chip);
+ u8 mask_lo, mask_hi, bits_lo, bits_hi;
+ unsigned int reg;
+- int ret = 0;
++ int ret;
+
+ mask_lo = *mask & U8_MAX;
+ mask_hi = (*mask >> 8) & U8_MAX;
+@@ -663,10 +663,8 @@ static void aw9523_gpio_set_multiple(str
+ bits_hi = (*bits >> 8) & U8_MAX;
+
+ ret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi);
+- if (ret) {
++ if (ret)
+ dev_warn(awi->dev, "Cannot write port1 out level\n");
+- goto out;
+- }
+ }
+ if (mask_lo) {
+ reg = AW9523_REG_OUT_STATE(0);
+@@ -675,7 +673,6 @@ static void aw9523_gpio_set_multiple(str
+ if (ret)
+ dev_warn(awi->dev, "Cannot write port0 out level\n");
+ }
+-out:
+ mutex_unlock(&awi->i2c_lock);
+ }
+
--- /dev/null
+From 418ee9488ff74ab4ada3a539a2840dda9e56f847 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Fri, 29 Mar 2024 12:55:18 +0200
+Subject: [PATCH] pinctrl: aw9523: Make use of struct pinfunction and
+ PINCTRL_PINFUNCTION()
+
+Since pin control provides a generic data type and a macro for
+the pin function definition, use them in the driver.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-5-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 32 ++++++--------------------------
+ 1 file changed, 6 insertions(+), 26 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -67,18 +67,6 @@ struct aw9523_irq {
+ };
+
+ /*
+- * struct aw9523_pinmux - Pin mux params
+- * @name: Name of the mux
+- * @grps: Groups of the mux
+- * @num_grps: Number of groups (sizeof array grps)
+- */
+-struct aw9523_pinmux {
+- const char *name;
+- const char * const *grps;
+- const u8 num_grps;
+-};
+-
+-/*
+ * struct aw9523 - Main driver structure
+ * @dev: device handle
+ * @regmap: regmap handle for current device
+@@ -158,17 +146,9 @@ static const char * const gpio_pwm_group
+ };
+
+ /* Warning: Do NOT reorder this array */
+-static const struct aw9523_pinmux aw9523_pmx[] = {
+- {
+- .name = "pwm",
+- .grps = gpio_pwm_groups,
+- .num_grps = ARRAY_SIZE(gpio_pwm_groups),
+- },
+- {
+- .name = "gpio",
+- .grps = gpio_pwm_groups,
+- .num_grps = ARRAY_SIZE(gpio_pwm_groups),
+- },
++static const struct pinfunction aw9523_pmx[] = {
++ PINCTRL_PINFUNCTION("pwm", gpio_pwm_groups, ARRAY_SIZE(gpio_pwm_groups)),
++ PINCTRL_PINFUNCTION("gpio", gpio_pwm_groups, ARRAY_SIZE(gpio_pwm_groups)),
+ };
+
+ static int aw9523_pmx_get_funcs_count(struct pinctrl_dev *pctl)
+@@ -184,10 +164,10 @@ static const char *aw9523_pmx_get_fname(
+
+ static int aw9523_pmx_get_groups(struct pinctrl_dev *pctl, unsigned int sel,
+ const char * const **groups,
+- unsigned int * const num_groups)
++ unsigned int * const ngroups)
+ {
+- *groups = aw9523_pmx[sel].grps;
+- *num_groups = aw9523_pmx[sel].num_grps;
++ *groups = aw9523_pmx[sel].groups;
++ *ngroups = aw9523_pmx[sel].ngroups;
+ return 0;
+ }
+
--- /dev/null
+From 66413f0468d35adb352c76bc286bf6f6746ba354 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andy.shevchenko@gmail.com>
+Date: Fri, 29 Mar 2024 12:55:19 +0200
+Subject: [PATCH] pinctrl: aw9523: Use temporary variable for HW IRQ number
+
+There are two different ways on how to get HW IRQ number in some functions.
+Unify that by using temporary variable and irqd_to_hwirq() call.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-6-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -428,12 +428,12 @@ static int aw9523_gpio_irq_type(struct i
+ static void aw9523_irq_mask(struct irq_data *d)
+ {
+ struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+- unsigned int n = d->hwirq % AW9523_PINS_PER_PORT;
++ irq_hw_number_t hwirq = irqd_to_hwirq(d);
++ unsigned int n = hwirq % AW9523_PINS_PER_PORT;
+
+- regmap_update_bits(awi->regmap,
+- AW9523_REG_INTR_DIS(d->hwirq),
++ regmap_update_bits(awi->regmap, AW9523_REG_INTR_DIS(hwirq),
+ BIT(n), BIT(n));
+- gpiochip_disable_irq(&awi->gpio, irqd_to_hwirq(d));
++ gpiochip_disable_irq(&awi->gpio, hwirq);
+ }
+
+ /*
+@@ -446,11 +446,11 @@ static void aw9523_irq_mask(struct irq_d
+ static void aw9523_irq_unmask(struct irq_data *d)
+ {
+ struct aw9523 *awi = gpiochip_get_data(irq_data_get_irq_chip_data(d));
+- unsigned int n = d->hwirq % AW9523_PINS_PER_PORT;
++ irq_hw_number_t hwirq = irqd_to_hwirq(d);
++ unsigned int n = hwirq % AW9523_PINS_PER_PORT;
+
+- gpiochip_enable_irq(&awi->gpio, irqd_to_hwirq(d));
+- regmap_update_bits(awi->regmap,
+- AW9523_REG_INTR_DIS(d->hwirq),
++ gpiochip_enable_irq(&awi->gpio, hwirq);
++ regmap_update_bits(awi->regmap, AW9523_REG_INTR_DIS(hwirq),
+ BIT(n), 0);
+ }
+
--- /dev/null
+From 4210ef801a248223a0ea5f47b5446081b4925e10 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andy.shevchenko@gmail.com>
+Date: Fri, 29 Mar 2024 12:55:20 +0200
+Subject: [PATCH] pinctrl: aw9523: Get rid of redundant ' & U8_MAX' pieces
+
+When the variable is declared as u8, no need to perform ' & U8_MAX'
+as it's implied anyway.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-7-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -603,7 +603,7 @@ static int aw9523_gpio_get_multiple(stru
+ mutex_lock(&awi->i2c_lock);
+
+ /* Port 0 (gpio 0-7) */
+- m = *mask & U8_MAX;
++ m = *mask;
+ if (m) {
+ ret = _aw9523_gpio_get_multiple(awi, 0, &state, m);
+ if (ret)
+@@ -612,7 +612,7 @@ static int aw9523_gpio_get_multiple(stru
+ *bits = state;
+
+ /* Port 1 (gpio 8-15) */
+- m = (*mask >> 8) & U8_MAX;
++ m = *mask >> 8;
+ if (m) {
+ ret = _aw9523_gpio_get_multiple(awi, AW9523_PINS_PER_PORT,
+ &state, m);
+@@ -635,20 +635,20 @@ static void aw9523_gpio_set_multiple(str
+ unsigned int reg;
+ int ret;
+
+- mask_lo = *mask & U8_MAX;
+- mask_hi = (*mask >> 8) & U8_MAX;
++ mask_lo = *mask;
++ mask_hi = *mask >> 8;
++ bits_lo = *bits;
++ bits_hi = *bits >> 8;
++
+ mutex_lock(&awi->i2c_lock);
+ if (mask_hi) {
+ reg = AW9523_REG_OUT_STATE(AW9523_PINS_PER_PORT);
+- bits_hi = (*bits >> 8) & U8_MAX;
+-
+ ret = regmap_write_bits(awi->regmap, reg, mask_hi, bits_hi);
+ if (ret)
+ dev_warn(awi->dev, "Cannot write port1 out level\n");
+ }
+ if (mask_lo) {
+ reg = AW9523_REG_OUT_STATE(0);
+- bits_lo = *bits & U8_MAX;
+ ret = regmap_write_bits(awi->regmap, reg, mask_lo, bits_lo);
+ if (ret)
+ dev_warn(awi->dev, "Cannot write port0 out level\n");
--- /dev/null
+From 6bf270863ade776485d1c6bdb8f69d642b0e5f64 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andy.shevchenko@gmail.com>
+Date: Fri, 29 Mar 2024 12:55:21 +0200
+Subject: [PATCH] pinctrl: aw9523: Remove unused irqchip field in struct
+ aw9523_irq
+
+The irqchip field is allocated, assigned but never used. Remove it.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-8-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 8 --------
+ 1 file changed, 8 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -57,12 +57,10 @@
+ /*
+ * struct aw9523_irq - Interrupt controller structure
+ * @lock: mutex locking for the irq bus
+- * @irqchip: structure holding irqchip params
+ * @cached_gpio: stores the previous gpio status for bit comparison
+ */
+ struct aw9523_irq {
+ struct mutex lock;
+- struct irq_chip *irqchip;
+ u16 cached_gpio;
+ };
+
+@@ -805,21 +803,15 @@ static int aw9523_init_irq(struct aw9523
+ {
+ struct device *dev = awi->dev;
+ struct gpio_irq_chip *girq;
+- struct irq_chip *irqchip;
+ int ret;
+
+ if (!device_property_read_bool(dev, "interrupt-controller"))
+ return 0;
+
+- irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL);
+- if (!irqchip)
+- return -ENOMEM;
+-
+ awi->irq = devm_kzalloc(dev, sizeof(*awi->irq), GFP_KERNEL);
+ if (!awi->irq)
+ return -ENOMEM;
+
+- awi->irq->irqchip = irqchip;
+ mutex_init(&awi->irq->lock);
+
+ ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func,
--- /dev/null
+From c567b00cc3d73f3ce4e92126731545d177262090 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Fri, 29 Mar 2024 12:55:22 +0200
+Subject: [PATCH] pinctrl: aw9523: Make use of dev_err_probe()
+
+Simplify the error handling in probe function by switching from
+dev_err() to dev_err_probe().
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-9-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 9 +++------
+ 1 file changed, 3 insertions(+), 6 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -816,10 +816,8 @@ static int aw9523_init_irq(struct aw9523
+
+ ret = devm_request_threaded_irq(dev, irq, NULL, aw9523_irq_thread_func,
+ IRQF_ONESHOT, dev_name(dev), awi);
+- if (ret) {
+- dev_err(dev, "Failed to request irq %d\n", irq);
+- return ret;
+- }
++ if (ret)
++ return dev_err_probe(dev, ret, "Failed to request irq %d\n", irq);
+
+ girq = &awi->gpio.irq;
+ gpio_irq_chip_set_chip(girq, &aw9523_irq_chip);
+@@ -1016,8 +1014,7 @@ static int aw9523_probe(struct i2c_clien
+
+ awi->pctl = devm_pinctrl_register(dev, pdesc, awi);
+ if (IS_ERR(awi->pctl)) {
+- ret = PTR_ERR(awi->pctl);
+- dev_err(dev, "Cannot register pinctrl: %d", ret);
++ ret = dev_err_probe(dev, PTR_ERR(awi->pctl), "Cannot register pinctrl");
+ goto err_disable_vregs;
+ }
+
--- /dev/null
+From 7b8b9b5450b89d01e4b8f120b903cee85b529231 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andy.shevchenko@gmail.com>
+Date: Fri, 29 Mar 2024 12:55:23 +0200
+Subject: [PATCH] pinctrl: aw9523: Sort headers and group pinctrl/*
+
+One header was misplaced and group pinctrl/* ones to show the relation
+with the pin control subsystem.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-10-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -13,17 +13,18 @@
+ #include <linux/init.h>
+ #include <linux/interrupt.h>
+ #include <linux/irq.h>
+-#include <linux/mutex.h>
+ #include <linux/module.h>
+-#include <linux/pinctrl/pinconf.h>
+-#include <linux/pinctrl/pinctrl.h>
+-#include <linux/pinctrl/pinmux.h>
+-#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/mutex.h>
+ #include <linux/property.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinmux.h>
++
+ #define AW9523_MAX_FUNCS 2
+ #define AW9523_NUM_PORTS 2
+ #define AW9523_PINS_PER_PORT 8
--- /dev/null
+From 4aad0ad20f4ea80180a3e58b04b701728541c0f7 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andy.shevchenko@gmail.com>
+Date: Fri, 29 Mar 2024 12:55:24 +0200
+Subject: [PATCH] pinctrl: aw9523: Fix indentation in a few places
+
+In the comment, function prototype, and array of strings indentation
+is kinda broken. Reindent that.
+
+Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
+Message-ID: <20240329105634.712457-11-andy.shevchenko@gmail.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-aw9523.c | 17 ++++++++---------
+ 1 file changed, 8 insertions(+), 9 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-aw9523.c
++++ b/drivers/pinctrl/pinctrl-aw9523.c
+@@ -1,8 +1,7 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+ /*
+ * Awinic AW9523B i2c pin controller driver
+- * Copyright (c) 2020, AngeloGioacchino Del Regno
+- * <angelogioacchino.delregno@somainline.org>
++ * Copyright (c) 2020, AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
+ */
+
+ #include <linux/bitfield.h>
+@@ -139,9 +138,10 @@ static const struct pinctrl_ops aw9523_p
+ };
+
+ static const char * const gpio_pwm_groups[] = {
+- "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
+- "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11",
+- "gpio12", "gpio13", "gpio14", "gpio15"
++ "gpio0", "gpio1", "gpio2", "gpio3", /* 0-3 */
++ "gpio4", "gpio5", "gpio6", "gpio7", /* 4-7 */
++ "gpio8", "gpio9", "gpio10", "gpio11", /* 8-11 */
++ "gpio12", "gpio13", "gpio14", "gpio15", /* 11-15 */
+ };
+
+ /* Warning: Do NOT reorder this array */
+@@ -388,8 +388,8 @@ static int aw9523_get_pin_direction(stru
+ *
+ * Return: Zero for success or negative number for error
+ */
+-static int aw9523_get_port_state(struct regmap *regmap, u8 pin,
+- u8 regbit, unsigned int *state)
++static int aw9523_get_port_state(struct regmap *regmap, u8 pin, u8 regbit,
++ unsigned int *state)
+ {
+ u8 reg;
+ int dir;
+@@ -984,8 +984,7 @@ static int aw9523_probe(struct i2c_clien
+ }
+
+ mutex_init(&awi->i2c_lock);
+- lockdep_set_subclass(&awi->i2c_lock,
+- i2c_adapter_depth(client->adapter));
++ lockdep_set_subclass(&awi->i2c_lock, i2c_adapter_depth(client->adapter));
+
+ pdesc = devm_kzalloc(dev, sizeof(*pdesc), GFP_KERNEL);
+ if (!pdesc)
--- /dev/null
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 26 Jul 2023 01:32:55 +0800
+Subject: [PATCH] pinctrl: mtmips: support requesting different functions for
+ same group
+
+Sometimes pinctrl consumers may request different functions for the
+same pin group in different situations. This patch can help to reset
+the group function flag when requesting a different function.
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pinctrl/mediatek/pinctrl-mtmips.c | 21 +++++++++++++++++----
+ 1 file changed, 17 insertions(+), 4 deletions(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mtmips.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mtmips.c
+@@ -123,11 +123,24 @@ static int mtmips_pmx_group_enable(struc
+ int i;
+ int shift;
+
+- /* dont allow double use */
++ /*
++ * for the same pin group, if request a different function,
++ * then clear the group function flag and continue, else exit.
++ */
+ if (p->groups[group].enabled) {
+- dev_err(p->dev, "%s is already enabled\n",
+- p->groups[group].name);
+- return 0;
++ for (i = 0; i < p->groups[group].func_count; i++) {
++ if (p->groups[group].func[i].enabled == 1) {
++ if (!strcmp(p->func[func]->name,
++ p->groups[group].func[i].name))
++ return 0;
++ p->groups[group].func[i].enabled = 0;
++ break;
++ }
++ }
++
++ /* exit if request the "gpio" function again */
++ if (i == p->groups[group].func_count && func == 0)
++ return 0;
+ }
+
+ p->groups[group].enabled = 1;
--- /dev/null
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 1 Jan 2025 13:30:11 +0800
+Subject: [PATCH] pinctrl: mtmips: allow mux SDXC pins for mt76x8
+
+This is a hack to supprot two types of mt76x8 SDXC pinmaps:
+
+a) Use ethernet phy pins as SDXC IO.
+
+&pinctrl {
+ ephy-digital;
+
+ sdxc_iot_mode: sdxc_iot_mode {
+ esd {
+ groups = "esd";
+ function = "iot";
+ };
+
+ sdxc {
+ groups = "sdmode";
+ function = "sdxc";
+ };
+ };
+};
+
+b) Use I2S/I2C/GPIO0/UART1 pins as SDXC IO.
+
+&pinctrl {
+ ephy-analog;
+
+ sdxc_router_mode: sdxc_router_mode {
+ groups = "esd", "gpio", "i2c", "i2s", "sdmode", "uart1";
+ function = "gpio";
+ };
+};
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/pinctrl/mediatek/pinctrl-mt76x8.c | 24 ++++++++++++++++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/mediatek/pinctrl-mt76x8.c
++++ b/drivers/pinctrl/mediatek/pinctrl-mt76x8.c
+@@ -1,10 +1,13 @@
+ // SPDX-License-Identifier: GPL-2.0-only
+
++#include <asm/mach-ralink/ralink_regs.h>
+ #include <linux/module.h>
+ #include <linux/platform_device.h>
+ #include <linux/of.h>
+ #include "pinctrl-mtmips.h"
+
++#define SYSC_REG_AGPIO_CFG 0x3c
++
+ #define MT76X8_GPIO_MODE_MASK 0x3
+
+ #define MT76X8_GPIO_MODE_P4LED_KN 58
+@@ -26,6 +29,7 @@
+ #define MT76X8_GPIO_MODE_I2C 20
+ #define MT76X8_GPIO_MODE_REFCLK 18
+ #define MT76X8_GPIO_MODE_PERST 16
++#define MT76X8_GPIO_MODE_ESD 15
+ #define MT76X8_GPIO_MODE_WDT 14
+ #define MT76X8_GPIO_MODE_SPI 12
+ #define MT76X8_GPIO_MODE_SDMODE 10
+@@ -74,6 +78,12 @@ static struct mtmips_pmx_func refclk_grp
+ static struct mtmips_pmx_func perst_grp[] = { FUNC("perst", 0, 36, 1) };
+ static struct mtmips_pmx_func wdt_grp[] = { FUNC("wdt", 0, 38, 1) };
+ static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 7, 4) };
++/*
++ * "esd" (Ethernet SDXC) group supports two mode:
++ * "gpio" - SDXC mux to I2S/I2C/GPIO0/UART1 pins with "gpio" mode
++ * "iot" - SDXC mux to EPHY pins, eth p1-p4 pad must be set to "digital"
++ */
++static struct mtmips_pmx_func esd_grp[] = { FUNC("iot", 0, 47, 1) };
+
+ static struct mtmips_pmx_func sd_mode_grp[] = {
+ FUNC("jtag", 3, 22, 8),
+@@ -216,6 +226,7 @@ static struct mtmips_pmx_group mt76x8_pi
+ GRP("perst", perst_grp, 1, MT76X8_GPIO_MODE_PERST),
+ GRP("wdt", wdt_grp, 1, MT76X8_GPIO_MODE_WDT),
+ GRP("spi", spi_grp, 1, MT76X8_GPIO_MODE_SPI),
++ GRP("esd", esd_grp, 1, MT76X8_GPIO_MODE_ESD),
+ GRP_G("sdmode", sd_mode_grp, MT76X8_GPIO_MODE_MASK,
+ 1, MT76X8_GPIO_MODE_SDMODE),
+ GRP_G("uart0", uart0_grp, MT76X8_GPIO_MODE_MASK,
+@@ -257,7 +268,18 @@ static struct mtmips_pmx_group mt76x8_pi
+
+ static int mt76x8_pinctrl_probe(struct platform_device *pdev)
+ {
+- return mtmips_pinctrl_init(pdev, mt76x8_pinmux_data);
++ int ret;
++
++ ret = mtmips_pinctrl_init(pdev, mt76x8_pinmux_data);
++ if (ret)
++ return ret;
++
++ if (of_property_present(pdev->dev.of_node, "ephy-analog"))
++ rt_sysc_m32(0xf << 17, 0, SYSC_REG_AGPIO_CFG);
++ else if (of_property_present(pdev->dev.of_node, "ephy-digital"))
++ rt_sysc_m32(0xf << 17, 0xf << 17, SYSC_REG_AGPIO_CFG);
++
++ return ret;
+ }
+
+ static const struct of_device_id mt76x8_pinctrl_match[] = {
--- /dev/null
+From 975e76214cd2516eb6cfff4c3eec581872645e88 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 19 Sep 2013 01:50:59 +0200
+Subject: [PATCH 31/53] uvc: add iPassion iP2970 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/media/usb/uvc/uvc_driver.c | 12 +++
+ drivers/media/usb/uvc/uvc_status.c | 2 +
+ drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++
+ drivers/media/usb/uvc/uvcvideo.h | 5 +-
+ 4 files changed, 165 insertions(+), 1 deletion(-)
+
+--- a/drivers/media/usb/uvc/uvc_driver.c
++++ b/drivers/media/usb/uvc/uvc_driver.c
+@@ -3296,6 +3296,18 @@ static const struct usb_device_id uvc_id
+ .bInterfaceSubClass = 1,
+ .bInterfaceProtocol = 0,
+ .driver_info = UVC_INFO_META(V4L2_META_FMT_D4XX) },
++ /* iPassion iP2970 */
++ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE
++ | USB_DEVICE_ID_MATCH_INT_INFO,
++ .idVendor = 0x1B3B,
++ .idProduct = 0x2970,
++ .bInterfaceClass = USB_CLASS_VIDEO,
++ .bInterfaceSubClass = 1,
++ .bInterfaceProtocol = 0,
++ .driver_info = UVC_QUIRK_PROBE_MINMAX
++ | UVC_QUIRK_STREAM_NO_FID
++ | UVC_QUIRK_MOTION
++ | UVC_QUIRK_SINGLE_ISO },
+ /* Generic USB Video Class */
+ { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_UNDEFINED) },
+ { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },
+--- a/drivers/media/usb/uvc/uvc_status.c
++++ b/drivers/media/usb/uvc/uvc_status.c
+@@ -228,6 +228,7 @@ static void uvc_status_complete(struct u
+ if (uvc_event_control(urb, dev->status, len))
+ /* The URB will be resubmitted in work context. */
+ return;
++ dev->motion = 1;
+ break;
+ }
+
+@@ -274,6 +275,7 @@ int uvc_status_init(struct uvc_device *d
+ }
+
+ pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
++ dev->motion = 0;
+
+ /*
+ * For high-speed interrupt endpoints, the bInterval value is used as
+--- a/drivers/media/usb/uvc/uvc_video.c
++++ b/drivers/media/usb/uvc/uvc_video.c
+@@ -19,6 +19,11 @@
+ #include <linux/wait.h>
+ #include <linux/atomic.h>
+ #include <asm/unaligned.h>
++#include <linux/skbuff.h>
++#include <linux/kobject.h>
++#include <linux/netlink.h>
++#include <linux/kobject.h>
++#include <linux/workqueue.h>
+
+ #include <media/jpeg.h>
+ #include <media/v4l2-common.h>
+@@ -1321,9 +1326,149 @@ static void uvc_video_decode_data(struct
+ uvc_urb->async_operations++;
+ }
+
++struct bh_priv {
++ unsigned long seen;
++};
++
++struct bh_event {
++ const char *name;
++ struct sk_buff *skb;
++ struct work_struct work;
++};
++
++#define BH_ERR(fmt, args...) printk(KERN_ERR "%s: " fmt, "webcam", ##args )
++#define BH_DBG(fmt, args...) do {} while (0)
++#define BH_SKB_SIZE 2048
++
++extern u64 uevent_next_seqnum(void);
++static int seen = 0;
++
++static int bh_event_add_var(struct bh_event *event, int argv,
++ const char *format, ...)
++{
++ static char buf[128];
++ char *s;
++ va_list args;
++ int len;
++
++ if (argv)
++ return 0;
++
++ va_start(args, format);
++ len = vsnprintf(buf, sizeof(buf), format, args);
++ va_end(args);
++
++ if (len >= sizeof(buf)) {
++ BH_ERR("buffer size too small\n");
++ WARN_ON(1);
++ return -ENOMEM;
++ }
++
++ s = skb_put(event->skb, len + 1);
++ strcpy(s, buf);
++
++ BH_DBG("added variable '%s'\n", s);
++
++ return 0;
++}
++
++static int motion_hotplug_fill_event(struct bh_event *event)
++{
++ int s = jiffies;
++ int ret;
++
++ if (!seen)
++ seen = jiffies;
++
++ ret = bh_event_add_var(event, 0, "HOME=%s", "/");
++ if (ret)
++ return ret;
++
++ ret = bh_event_add_var(event, 0, "PATH=%s",
++ "/sbin:/bin:/usr/sbin:/usr/bin");
++ if (ret)
++ return ret;
++
++ ret = bh_event_add_var(event, 0, "SUBSYSTEM=usb");
++ if (ret)
++ return ret;
++
++ ret = bh_event_add_var(event, 0, "ACTION=motion");
++ if (ret)
++ return ret;
++
++ ret = bh_event_add_var(event, 0, "SEEN=%d", s - seen);
++ if (ret)
++ return ret;
++ seen = s;
++
++ ret = bh_event_add_var(event, 0, "SEQNUM=%llu", uevent_next_seqnum());
++
++ return ret;
++}
++
++static void motion_hotplug_work(struct work_struct *work)
++{
++ struct bh_event *event = container_of(work, struct bh_event, work);
++ int ret = 0;
++
++ event->skb = alloc_skb(BH_SKB_SIZE, GFP_KERNEL);
++ if (!event->skb)
++ goto out_free_event;
++
++ ret = bh_event_add_var(event, 0, "%s@", "add");
++ if (ret)
++ goto out_free_skb;
++
++ ret = motion_hotplug_fill_event(event);
++ if (ret)
++ goto out_free_skb;
++
++ NETLINK_CB(event->skb).dst_group = 1;
++ broadcast_uevent(event->skb, 0, 1, GFP_KERNEL);
++
++out_free_skb:
++ if (ret) {
++ BH_ERR("work error %d\n", ret);
++ kfree_skb(event->skb);
++ }
++out_free_event:
++ kfree(event);
++}
++
++static int motion_hotplug_create_event(void)
++{
++ struct bh_event *event;
++
++ event = kzalloc(sizeof(*event), GFP_KERNEL);
++ if (!event)
++ return -ENOMEM;
++
++ event->name = "motion";
++
++ INIT_WORK(&event->work, (void *)(void *)motion_hotplug_work);
++ schedule_work(&event->work);
++
++ return 0;
++}
++
++#define MOTION_FLAG_OFFSET 4
+ static void uvc_video_decode_end(struct uvc_streaming *stream,
+ struct uvc_buffer *buf, const u8 *data, int len)
+ {
++ if ((stream->dev->quirks & UVC_QUIRK_MOTION) &&
++ (data[len - 2] == 0xff) && (data[len - 1] == 0xd9)) {
++ u8 *mem;
++ buf->state = UVC_BUF_STATE_READY;
++ mem = (u8 *) (buf->mem + MOTION_FLAG_OFFSET);
++ if ( stream->dev->motion ) {
++ stream->dev->motion = 0;
++ motion_hotplug_create_event();
++ } else {
++ *mem &= 0x7f;
++ }
++ }
++
+ /* Mark the buffer as done if the EOF marker is set. */
+ if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
+ uvc_dbg(stream->dev, FRAME, "Frame complete (EOF found)\n");
+@@ -1905,6 +2050,8 @@ static int uvc_init_video_isoc(struct uv
+ if (npackets == 0)
+ return -ENOMEM;
+
++ if (stream->dev->quirks & UVC_QUIRK_SINGLE_ISO)
++ npackets = 1;
+ size = npackets * psize;
+
+ for_each_uvc_urb(uvc_urb, stream) {
+--- a/drivers/media/usb/uvc/uvcvideo.h
++++ b/drivers/media/usb/uvc/uvcvideo.h
+@@ -77,6 +77,8 @@
+ #define UVC_QUIRK_DISABLE_AUTOSUSPEND 0x00008000
+ #define UVC_QUIRK_INVALID_DEVICE_SOF 0x00010000
+ #define UVC_QUIRK_MJPEG_NO_EOF 0x00020000
++#define UVC_QUIRK_MOTION 0x00040000
++#define UVC_QUIRK_SINGLE_ISO 0x00080000
+
+ /* Format flags */
+ #define UVC_FMT_FLAG_COMPRESSED 0x00000001
+@@ -591,6 +593,7 @@ struct uvc_device {
+
+ struct input_dev *input;
+ char input_phys[64];
++ int motion;
+
+ struct uvc_ctrl_work {
+ struct work_struct work;
--- /dev/null
+From da6015e7f19d749f135f7ac55c4ec47b06faa868 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 9 Aug 2013 20:12:59 +0200
+Subject: [PATCH 41/53] DT: Add documentation for spi-rt2880
+
+Describe the SPI master found on the MIPS based Ralink RT2880 SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/spi/spi-rt2880.txt | 28 ++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt
+@@ -0,0 +1,28 @@
++Ralink SoC RT2880 SPI master controller.
++
++This SPI controller is found on most wireless SoCs made by ralink.
++
++Required properties:
++- compatible : "ralink,rt2880-spi"
++- reg : The register base for the controller.
++- #address-cells : <1>, as required by generic SPI binding.
++- #size-cells : <0>, also as required by generic SPI binding.
++
++Child nodes as per the generic SPI binding.
++
++Example:
++
++ spi@b00 {
++ compatible = "ralink,rt2880-spi";
++ reg = <0xb00 0x100>;
++
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ m25p80@0 {
++ compatible = "m25p80";
++ reg = <0>;
++ spi-max-frequency = <10000000>;
++ };
++ };
++
--- /dev/null
+From 683af4ebb91a1600df1946ac4769d916b8a1be65 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 11:15:12 +0100
+Subject: [PATCH 42/53] SPI: ralink: add Ralink SoC spi driver
+
+Add the driver needed to make SPI work on Ralink SoC.
+
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/spi/Kconfig | 6 +
+ drivers/spi/Makefile | 1 +
+ drivers/spi/spi-rt2880.c | 530 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 537 insertions(+)
+ create mode 100644 drivers/spi/spi-rt2880.c
+
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -904,6 +904,12 @@ config SPI_QCOM_GENI
+ This driver can also be built as a module. If so, the module
+ will be called spi-geni-qcom.
+
++config SPI_RT2880
++ tristate "Ralink RT288x SPI Controller"
++ depends on RALINK
++ help
++ This selects a driver for the Ralink RT288x/RT305x SPI Controller.
++
+ config SPI_S3C64XX
+ tristate "Samsung S3C64XX/Exynos SoC series type SPI"
+ depends on (PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST)
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -118,6 +118,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
+ obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
+ obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
+ obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
++obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
+ obj-$(CONFIG_SPI_RZV2M_CSI) += spi-rzv2m-csi.o
+ obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
+ obj-$(CONFIG_SPI_SC18IS602) += spi-sc18is602.o
+--- /dev/null
++++ b/drivers/spi/spi-rt2880.c
+@@ -0,0 +1,473 @@
++/*
++ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
++ *
++ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
++ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Some parts are based on spi-orion.c:
++ * Author: Shadi Ammouri <shadi@marvell.com>
++ * Copyright (C) 2007-2008 Marvell Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/reset.h>
++#include <linux/spi/spi.h>
++#include <linux/platform_device.h>
++
++#define DRIVER_NAME "spi-rt2880"
++
++#define RAMIPS_SPI_STAT 0x00
++#define RAMIPS_SPI_CFG 0x10
++#define RAMIPS_SPI_CTL 0x14
++#define RAMIPS_SPI_DATA 0x20
++#define RAMIPS_SPI_ADDR 0x24
++#define RAMIPS_SPI_BS 0x28
++#define RAMIPS_SPI_USER 0x2C
++#define RAMIPS_SPI_TXFIFO 0x30
++#define RAMIPS_SPI_RXFIFO 0x34
++#define RAMIPS_SPI_FIFO_STAT 0x38
++#define RAMIPS_SPI_MODE 0x3C
++#define RAMIPS_SPI_DEV_OFFSET 0x40
++#define RAMIPS_SPI_DMA 0x80
++#define RAMIPS_SPI_DMASTAT 0x84
++#define RAMIPS_SPI_ARBITER 0xF0
++
++/* SPISTAT register bit field */
++#define SPISTAT_BUSY BIT(0)
++
++/* SPICFG register bit field */
++#define SPICFG_ADDRMODE BIT(12)
++#define SPICFG_RXENVDIS BIT(11)
++#define SPICFG_RXCAP BIT(10)
++#define SPICFG_SPIENMODE BIT(9)
++#define SPICFG_MSBFIRST BIT(8)
++#define SPICFG_SPICLKPOL BIT(6)
++#define SPICFG_RXCLKEDGE_FALLING BIT(5)
++#define SPICFG_TXCLKEDGE_FALLING BIT(4)
++#define SPICFG_HIZSPI BIT(3)
++#define SPICFG_SPICLK_PRESCALE_MASK 0x7
++#define SPICFG_SPICLK_DIV2 0
++#define SPICFG_SPICLK_DIV4 1
++#define SPICFG_SPICLK_DIV8 2
++#define SPICFG_SPICLK_DIV16 3
++#define SPICFG_SPICLK_DIV32 4
++#define SPICFG_SPICLK_DIV64 5
++#define SPICFG_SPICLK_DIV128 6
++#define SPICFG_SPICLK_DISABLE 7
++
++/* SPICTL register bit field */
++#define SPICTL_START BIT(4)
++#define SPICTL_HIZSDO BIT(3)
++#define SPICTL_STARTWR BIT(2)
++#define SPICTL_STARTRD BIT(1)
++#define SPICTL_SPIENA BIT(0)
++
++/* SPIUSER register bit field */
++#define SPIUSER_USERMODE BIT(21)
++#define SPIUSER_INSTR_PHASE BIT(20)
++#define SPIUSER_ADDR_PHASE_MASK 0x7
++#define SPIUSER_ADDR_PHASE_OFFSET 17
++#define SPIUSER_MODE_PHASE BIT(16)
++#define SPIUSER_DUMMY_PHASE_MASK 0x3
++#define SPIUSER_DUMMY_PHASE_OFFSET 14
++#define SPIUSER_DATA_PHASE_MASK 0x3
++#define SPIUSER_DATA_PHASE_OFFSET 12
++#define SPIUSER_DATA_READ (BIT(0) << SPIUSER_DATA_PHASE_OFFSET)
++#define SPIUSER_DATA_WRITE (BIT(1) << SPIUSER_DATA_PHASE_OFFSET)
++#define SPIUSER_ADDR_TYPE_OFFSET 9
++#define SPIUSER_MODE_TYPE_OFFSET 6
++#define SPIUSER_DUMMY_TYPE_OFFSET 3
++#define SPIUSER_DATA_TYPE_OFFSET 0
++#define SPIUSER_TRANSFER_MASK 0x7
++#define SPIUSER_TRANSFER_SINGLE BIT(0)
++#define SPIUSER_TRANSFER_DUAL BIT(1)
++#define SPIUSER_TRANSFER_QUAD BIT(2)
++
++#define SPIUSER_TRANSFER_TYPE(type) ( \
++ (type << SPIUSER_ADDR_TYPE_OFFSET) | \
++ (type << SPIUSER_MODE_TYPE_OFFSET) | \
++ (type << SPIUSER_DUMMY_TYPE_OFFSET) | \
++ (type << SPIUSER_DATA_TYPE_OFFSET) \
++)
++
++/* SPIFIFOSTAT register bit field */
++#define SPIFIFOSTAT_TXEMPTY BIT(19)
++#define SPIFIFOSTAT_RXEMPTY BIT(18)
++#define SPIFIFOSTAT_TXFULL BIT(17)
++#define SPIFIFOSTAT_RXFULL BIT(16)
++#define SPIFIFOSTAT_FIFO_MASK 0xff
++#define SPIFIFOSTAT_TX_OFFSET 8
++#define SPIFIFOSTAT_RX_OFFSET 0
++
++#define SPI_FIFO_DEPTH 16
++
++/* SPIMODE register bit field */
++#define SPIMODE_MODE_OFFSET 24
++#define SPIMODE_DUMMY_OFFSET 0
++
++/* SPIARB register bit field */
++#define SPICTL_ARB_EN BIT(31)
++#define SPICTL_CSCTL1 BIT(16)
++#define SPI1_POR BIT(1)
++#define SPI0_POR BIT(0)
++
++#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | \
++ SPI_CS_HIGH)
++
++struct rt2880_spi {
++ struct spi_master *master;
++ void __iomem *base;
++ u32 speed;
++ u16 wait_loops;
++ u16 mode;
++ struct clk *clk;
++};
++
++static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
++{
++ return spi_master_get_devdata(spi->master);
++}
++
++static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
++{
++ return ioread32(rs->base + reg);
++}
++
++static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg,
++ const u32 val)
++{
++ iowrite32(val, rs->base + reg);
++}
++
++static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
++{
++ void __iomem *addr = rs->base + reg;
++
++ iowrite32((ioread32(addr) | mask), addr);
++}
++
++static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
++{
++ void __iomem *addr = rs->base + reg;
++
++ iowrite32((ioread32(addr) & ~mask), addr);
++}
++
++static u32 rt2880_spi_baudrate_get(struct spi_device *spi, unsigned int speed)
++{
++ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++ u32 rate;
++ u32 prescale;
++
++ /*
++ * the supported rates are: 2, 4, 8, ... 128
++ * round up as we look for equal or less speed
++ */
++ rate = DIV_ROUND_UP(clk_get_rate(rs->clk), speed);
++ rate = roundup_pow_of_two(rate);
++
++ /* Convert the rate to SPI clock divisor value. */
++ prescale = ilog2(rate / 2);
++
++ /* some tolerance. double and add 100 */
++ rs->wait_loops = (8 * HZ * loops_per_jiffy) /
++ (clk_get_rate(rs->clk) / rate);
++ rs->wait_loops = (rs->wait_loops << 1) + 100;
++ rs->speed = speed;
++
++ dev_dbg(&spi->dev, "speed: %lu/%u, rate: %u, prescal: %u, loops: %hu\n",
++ clk_get_rate(rs->clk) / rate, speed, rate, prescale,
++ rs->wait_loops);
++
++ return prescale;
++}
++
++static u32 get_arbiter_offset(struct spi_master *master)
++{
++ u32 offset;
++
++ offset = RAMIPS_SPI_ARBITER;
++ if (master->bus_num == 1)
++ offset -= RAMIPS_SPI_DEV_OFFSET;
++
++ return offset;
++}
++
++static void rt2880_spi_set_cs(struct spi_device *spi, bool enable)
++{
++ struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
++
++ if (enable)
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++ else
++ rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++}
++
++static int rt2880_spi_wait_ready(struct rt2880_spi *rs, int len)
++{
++ int loop = rs->wait_loops * len;
++
++ while ((rt2880_spi_read(rs, RAMIPS_SPI_STAT) & SPISTAT_BUSY) && --loop)
++ cpu_relax();
++
++ if (loop)
++ return 0;
++
++ return -ETIMEDOUT;
++}
++
++static void rt2880_dump_reg(struct spi_master *master)
++{
++ struct rt2880_spi *rs = spi_master_get_devdata(master);
++
++ dev_dbg(&master->dev, "stat: %08x, cfg: %08x, ctl: %08x, " \
++ "data: %08x, arb: %08x\n",
++ rt2880_spi_read(rs, RAMIPS_SPI_STAT),
++ rt2880_spi_read(rs, RAMIPS_SPI_CFG),
++ rt2880_spi_read(rs, RAMIPS_SPI_CTL),
++ rt2880_spi_read(rs, RAMIPS_SPI_DATA),
++ rt2880_spi_read(rs, get_arbiter_offset(master)));
++}
++
++static int rt2880_spi_transfer_one(struct spi_master *master,
++ struct spi_device *spi, struct spi_transfer *xfer)
++{
++ struct rt2880_spi *rs = spi_master_get_devdata(master);
++ unsigned len;
++ const u8 *tx = xfer->tx_buf;
++ u8 *rx = xfer->rx_buf;
++ int err = 0;
++
++ /* change clock speed */
++ if (unlikely(rs->speed != xfer->speed_hz)) {
++ u32 reg;
++ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
++ reg &= ~SPICFG_SPICLK_PRESCALE_MASK;
++ reg |= rt2880_spi_baudrate_get(spi, xfer->speed_hz);
++ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
++ }
++
++ if (tx) {
++ len = xfer->len;
++ while (len-- > 0) {
++ rt2880_spi_write(rs, RAMIPS_SPI_DATA, *tx++);
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
++ err = rt2880_spi_wait_ready(rs, 1);
++ if (err) {
++ dev_err(&spi->dev, "TX failed, err=%d\n", err);
++ goto out;
++ }
++ }
++ }
++
++ if (rx) {
++ len = xfer->len;
++ while (len-- > 0) {
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
++ err = rt2880_spi_wait_ready(rs, 1);
++ if (err) {
++ dev_err(&spi->dev, "RX failed, err=%d\n", err);
++ goto out;
++ }
++ *rx++ = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
++ }
++ }
++
++out:
++ return err;
++}
++
++static int rt2880_spi_setup(struct spi_device *spi)
++{
++ struct spi_master *master = spi->master;
++ struct rt2880_spi *rs = spi_master_get_devdata(master);
++ u32 reg, old_reg, arbit_off;
++
++ if ((spi->max_speed_hz > master->max_speed_hz) ||
++ (spi->max_speed_hz < master->min_speed_hz)) {
++ dev_err(&spi->dev, "invalide requested speed %d Hz\n",
++ spi->max_speed_hz);
++ return -EINVAL;
++ }
++
++ if (!(master->bits_per_word_mask &
++ BIT(spi->bits_per_word - 1))) {
++ dev_err(&spi->dev, "invalide bits_per_word %d\n",
++ spi->bits_per_word);
++ return -EINVAL;
++ }
++
++ /* the hardware seems can't work on mode0 force it to mode3 */
++ if ((spi->mode & (SPI_CPOL | SPI_CPHA)) == SPI_MODE_0) {
++ dev_warn(&spi->dev, "force spi mode3\n");
++ spi->mode |= SPI_MODE_3;
++ }
++
++ /* chip polarity */
++ arbit_off = get_arbiter_offset(master);
++ reg = old_reg = rt2880_spi_read(rs, arbit_off);
++ if (spi->mode & SPI_CS_HIGH) {
++ switch (master->bus_num) {
++ case 1:
++ reg |= SPI1_POR;
++ break;
++ default:
++ reg |= SPI0_POR;
++ break;
++ }
++ } else {
++ switch (master->bus_num) {
++ case 1:
++ reg &= ~SPI1_POR;
++ break;
++ default:
++ reg &= ~SPI0_POR;
++ break;
++ }
++ }
++
++ /* enable spi1 */
++ if (master->bus_num == 1)
++ reg |= SPICTL_ARB_EN;
++
++ if (reg != old_reg)
++ rt2880_spi_write(rs, arbit_off, reg);
++
++ rt2880_dump_reg(master);
++
++ return 0;
++}
++
++static int rt2880_spi_prepare_message(struct spi_master *master,
++ struct spi_message *msg)
++{
++ struct rt2880_spi *rs = spi_master_get_devdata(master);
++ struct spi_device *spi = msg->spi;
++ u32 reg;
++
++ if ((rs->mode == spi->mode) && (rs->speed == spi->max_speed_hz))
++ return 0;
++
++#if 0
++ /* set spido to tri-state */
++ rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO);
++#endif
++
++ reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
++
++ reg &= ~(SPICFG_MSBFIRST | SPICFG_SPICLKPOL |
++ SPICFG_RXCLKEDGE_FALLING |
++ SPICFG_TXCLKEDGE_FALLING |
++ SPICFG_SPICLK_PRESCALE_MASK);
++
++ /* MSB */
++ if (!(spi->mode & SPI_LSB_FIRST))
++ reg |= SPICFG_MSBFIRST;
++
++ /* spi mode */
++ switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
++ case SPI_MODE_0:
++ reg |= SPICFG_TXCLKEDGE_FALLING;
++ break;
++ case SPI_MODE_1:
++ reg |= SPICFG_RXCLKEDGE_FALLING;
++ break;
++ case SPI_MODE_2:
++ reg |= SPICFG_SPICLKPOL | SPICFG_RXCLKEDGE_FALLING;
++ break;
++ case SPI_MODE_3:
++ reg |= SPICFG_SPICLKPOL | SPICFG_TXCLKEDGE_FALLING;
++ break;
++ }
++ rs->mode = spi->mode;
++
++#if 0
++ /* set spiclk and spiena to tri-state */
++ reg |= SPICFG_HIZSPI;
++#endif
++
++ /* clock divide */
++ reg |= rt2880_spi_baudrate_get(spi, spi->max_speed_hz);
++
++ rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
++
++ return 0;
++}
++
++static int rt2880_spi_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct spi_master *master;
++ struct rt2880_spi *rs;
++ void __iomem *base;
++ struct clk *clk;
++ int ret;
++
++ base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(base))
++ return PTR_ERR(base);
++
++ clk = devm_clk_get_enabled(dev, NULL);
++ if (IS_ERR(clk))
++ return dev_err_probe(dev, PTR_ERR(clk), "unable to get SYS clock");
++
++ master = devm_spi_alloc_master(dev, sizeof(*rs));
++ if (!master) {
++ dev_err(dev, "master allocation failed\n");
++ return -ENOMEM;
++ }
++
++ master->dev.of_node = pdev->dev.of_node;
++ master->mode_bits = RT2880_SPI_MODE_BITS;
++ master->bits_per_word_mask = SPI_BPW_MASK(8);
++ master->min_speed_hz = clk_get_rate(clk) / 128;
++ master->max_speed_hz = clk_get_rate(clk) / 2;
++ master->flags = SPI_MASTER_HALF_DUPLEX;
++ master->setup = rt2880_spi_setup;
++ master->prepare_message = rt2880_spi_prepare_message;
++ master->set_cs = rt2880_spi_set_cs;
++ master->transfer_one = rt2880_spi_transfer_one,
++
++ rs = spi_master_get_devdata(master);
++ rs->master = master;
++ rs->base = base;
++ rs->clk = clk;
++
++ ret = device_reset(&pdev->dev);
++ if (ret)
++ return ret;
++
++ return devm_spi_register_master(dev, master);
++}
++
++MODULE_ALIAS("platform:" DRIVER_NAME);
++
++static const struct of_device_id rt2880_spi_match[] = {
++ { .compatible = "ralink,rt2880-spi" },
++ {},
++};
++MODULE_DEVICE_TABLE(of, rt2880_spi_match);
++
++static struct platform_driver rt2880_spi_driver = {
++ .driver = {
++ .name = DRIVER_NAME,
++ .of_match_table = rt2880_spi_match,
++ },
++ .probe = rt2880_spi_probe,
++};
++
++module_platform_driver(rt2880_spi_driver);
++
++MODULE_DESCRIPTION("Ralink SPI driver");
++MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
++MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
++MODULE_LICENSE("GPL");
--- /dev/null
+From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:52:56 +0100
+Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
+ drivers/i2c/busses/Kconfig | 4 +
+ drivers/i2c/busses/Makefile | 1 +
+ drivers/i2c/busses/i2c-ralink.c | 327 ++++++++++++++++++++
+ 4 files changed, 359 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+ create mode 100644 drivers/i2c/busses/i2c-ralink.c
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+@@ -0,0 +1,27 @@
++I2C for Ralink platforms
++
++Required properties :
++- compatible : Must be "link,rt3052-i2c"
++- reg: physical base address of the controller and length of memory mapped
++ region.
++- #address-cells = <1>;
++- #size-cells = <0>;
++
++Optional properties:
++- Child nodes conforming to i2c bus binding
++
++Example :
++
++palmbus@10000000 {
++ i2c@900 {
++ compatible = "link,rt3052-i2c";
++ reg = <0x900 0x100>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ hwmon@4b {
++ compatible = "national,lm92";
++ reg = <0x4b>;
++ };
++ };
++};
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -1023,6 +1023,11 @@ config I2C_RK3X
+ This driver can also be built as a module. If so, the module will
+ be called i2c-rk3x.
+
++config I2C_RALINK
++ tristate "Ralink I2C Controller"
++ depends on RALINK && !SOC_MT7621
++ select OF_I2C
++
+ config I2C_RZV2M
+ tristate "Renesas RZ/V2M adapter"
+ depends on ARCH_RENESAS || COMPILE_TEST
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -96,6 +96,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pc
+ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
+ obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
+ obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
++obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
+ obj-$(CONFIG_I2C_QCOM_CCI) += i2c-qcom-cci.o
+ obj-$(CONFIG_I2C_QCOM_GENI) += i2c-qcom-geni.o
+ obj-$(CONFIG_I2C_QUP) += i2c-qup.o
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-ralink.c
+@@ -0,0 +1,397 @@
++/*
++ * drivers/i2c/busses/i2c-ralink.c
++ *
++ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
++ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
++ *
++ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
++ * (C) 2014 Sittisak <sittisaks@hotmail.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/reset.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/platform_device.h>
++#include <linux/of_platform.h>
++#include <linux/i2c.h>
++#include <linux/io.h>
++#include <linux/err.h>
++#include <linux/clk.h>
++
++#define REG_CONFIG_REG 0x00
++#define REG_CLKDIV_REG 0x04
++#define REG_DEVADDR_REG 0x08
++#define REG_ADDR_REG 0x0C
++#define REG_DATAOUT_REG 0x10
++#define REG_DATAIN_REG 0x14
++#define REG_STATUS_REG 0x18
++#define REG_STARTXFR_REG 0x1C
++#define REG_BYTECNT_REG 0x20
++
++/* REG_CONFIG_REG */
++#define I2C_ADDRLEN_OFFSET 5
++#define I2C_DEVADLEN_OFFSET 2
++#define I2C_ADDRLEN_MASK 0x3
++#define I2C_ADDR_DIS BIT(1)
++#define I2C_DEVADDR_DIS BIT(0)
++#define I2C_ADDRLEN_8 (7 << I2C_ADDRLEN_OFFSET)
++#define I2C_DEVADLEN_7 (6 << I2C_DEVADLEN_OFFSET)
++#define I2C_CONF_DEFAULT (I2C_ADDRLEN_8 | I2C_DEVADLEN_7)
++
++/* REG_CLKDIV_REG */
++#define I2C_CLKDIV_MASK 0xffff
++
++/* REG_DEVADDR_REG */
++#define I2C_DEVADDR_MASK 0x7f
++
++/* REG_ADDR_REG */
++#define I2C_ADDR_MASK 0xff
++
++/* REG_STATUS_REG */
++#define I2C_STARTERR BIT(4)
++#define I2C_ACKERR BIT(3)
++#define I2C_DATARDY BIT(2)
++#define I2C_SDOEMPTY BIT(1)
++#define I2C_BUSY BIT(0)
++
++/* REG_STARTXFR_REG */
++#define NOSTOP_CMD BIT(2)
++#define NODATA_CMD BIT(1)
++#define READ_CMD BIT(0)
++
++/* REG_BYTECNT_REG */
++#define BYTECNT_MAX 64
++#define SET_BYTECNT(x) (x - 1)
++
++/* timeout waiting for I2C devices to respond (clock streching) */
++#define TIMEOUT_MS 1000
++#define DELAY_INTERVAL_US 100
++
++struct rt_i2c {
++ void __iomem *base;
++ struct clk *clk;
++ struct device *dev;
++ struct i2c_adapter adap;
++ u32 cur_clk;
++ u32 clk_div;
++ u32 flags;
++};
++
++static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)
++{
++ iowrite32(val, i2c->base + reg);
++}
++
++static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)
++{
++ return ioread32(i2c->base + reg);
++}
++
++static int poll_down_timeout(void __iomem *addr, u32 mask)
++{
++ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
++
++ do {
++ if (!(readl_relaxed(addr) & mask))
++ return 0;
++
++ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
++ } while (time_before(jiffies, timeout));
++
++ return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
++}
++
++static int rt_i2c_wait_idle(struct rt_i2c *i2c)
++{
++ int ret;
++
++ ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);
++ if (ret < 0)
++ dev_dbg(i2c->dev, "idle err(%d)\n", ret);
++
++ return ret;
++}
++
++static int poll_up_timeout(void __iomem *addr, u32 mask)
++{
++ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
++ u32 status;
++
++ do {
++ status = readl_relaxed(addr);
++
++ /* check error status */
++ if (status & I2C_STARTERR)
++ return -EAGAIN;
++ else if (status & I2C_ACKERR)
++ return -ENXIO;
++ else if (status & mask)
++ return 0;
++
++ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
++ } while (time_before(jiffies, timeout));
++
++ return -ETIMEDOUT;
++}
++
++static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)
++{
++ int ret;
++
++ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);
++ if (ret < 0)
++ dev_dbg(i2c->dev, "rx err(%d)\n", ret);
++
++ return ret;
++}
++
++static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)
++{
++ int ret;
++
++ ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);
++ if (ret < 0)
++ dev_dbg(i2c->dev, "tx err(%d)\n", ret);
++
++ return ret;
++}
++
++static void rt_i2c_reset(struct rt_i2c *i2c)
++{
++ int ret;
++
++ ret = device_reset(i2c->adap.dev.parent);
++ if (ret)
++ dev_err(i2c->dev, "Failed to reset device");
++
++ barrier();
++ rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);
++}
++
++static void rt_i2c_dump_reg(struct rt_i2c *i2c)
++{
++ dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \
++ "addr %08x, dataout %08x, datain %08x, " \
++ "status %08x, startxfr %08x, bytecnt %08x\n",
++ rt_i2c_r32(i2c, REG_CONFIG_REG),
++ rt_i2c_r32(i2c, REG_CLKDIV_REG),
++ rt_i2c_r32(i2c, REG_DEVADDR_REG),
++ rt_i2c_r32(i2c, REG_ADDR_REG),
++ rt_i2c_r32(i2c, REG_DATAOUT_REG),
++ rt_i2c_r32(i2c, REG_DATAIN_REG),
++ rt_i2c_r32(i2c, REG_STATUS_REG),
++ rt_i2c_r32(i2c, REG_STARTXFR_REG),
++ rt_i2c_r32(i2c, REG_BYTECNT_REG));
++}
++
++static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
++ int num)
++{
++ struct rt_i2c *i2c;
++ struct i2c_msg *pmsg;
++ unsigned char addr;
++ int i, j, ret;
++ u32 cmd;
++
++ i2c = i2c_get_adapdata(adap);
++
++ for (i = 0; i < num; i++) {
++ pmsg = &msgs[i];
++ if (i == (num - 1))
++ cmd = 0;
++ else
++ cmd = NOSTOP_CMD;
++
++ dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n",
++ pmsg->addr, pmsg->len, pmsg->flags,
++ (cmd == 0)? 1 : 0);
++
++ /* wait hardware idle */
++ if ((ret = rt_i2c_wait_idle(i2c)))
++ goto err_timeout;
++
++ if (pmsg->flags & I2C_M_TEN) {
++ rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);
++ /* 10 bits address */
++ addr = 0x78 | ((pmsg->addr >> 8) & 0x03);
++ rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,
++ REG_DEVADDR_REG);
++ rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,
++ REG_ADDR_REG);
++ } else {
++ rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,
++ REG_CONFIG_REG);
++ /* 7 bits address */
++ rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
++ REG_DEVADDR_REG);
++ }
++
++ /* buffer length */
++ if (pmsg->len == 0)
++ cmd |= NODATA_CMD;
++ else
++ rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
++ REG_BYTECNT_REG);
++
++ j = 0;
++ if (pmsg->flags & I2C_M_RD) {
++ cmd |= READ_CMD;
++ /* start transfer */
++ barrier();
++ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
++ do {
++ /* wait */
++ if ((ret = rt_i2c_wait_rx_done(i2c)))
++ goto err_timeout;
++ /* read data */
++ if (pmsg->len)
++ pmsg->buf[j] = rt_i2c_r32(i2c,
++ REG_DATAIN_REG);
++ j++;
++ } while (j < pmsg->len);
++ } else {
++ do {
++ /* write data */
++ if (pmsg->len)
++ rt_i2c_w32(i2c, pmsg->buf[j],
++ REG_DATAOUT_REG);
++ /* start transfer */
++ if (j == 0) {
++ barrier();
++ rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
++ }
++ /* wait */
++ if ((ret = rt_i2c_wait_tx_done(i2c)))
++ goto err_timeout;
++ j++;
++ } while (j < pmsg->len);
++ }
++ }
++ /* the return value is number of executed messages */
++ ret = i;
++
++ return ret;
++
++err_timeout:
++ rt_i2c_dump_reg(i2c);
++ rt_i2c_reset(i2c);
++ return ret;
++}
++
++static u32 rt_i2c_func(struct i2c_adapter *a)
++{
++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++static const struct i2c_algorithm rt_i2c_algo = {
++ .master_xfer = rt_i2c_master_xfer,
++ .functionality = rt_i2c_func,
++};
++
++static const struct of_device_id i2c_rt_dt_ids[] = {
++ { .compatible = "ralink,rt2880-i2c" },
++ { /* sentinel */ }
++};
++
++MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
++
++static struct i2c_adapter_quirks rt_i2c_quirks = {
++ .max_write_len = BYTECNT_MAX,
++ .max_read_len = BYTECNT_MAX,
++};
++
++static int rt_i2c_init(struct rt_i2c *i2c)
++{
++ u32 reg;
++
++ /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */
++ i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /
++ (2 * i2c->cur_clk);
++ if (i2c->clk_div < 8)
++ i2c->clk_div = 8;
++ if (i2c->clk_div > I2C_CLKDIV_MASK)
++ i2c->clk_div = I2C_CLKDIV_MASK;
++
++ /* check support combinde/repeated start message */
++ rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);
++ reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;
++
++ rt_i2c_reset(i2c);
++
++ return reg;
++}
++
++static int rt_i2c_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct rt_i2c *i2c;
++ struct i2c_adapter *adap;
++ int restart;
++
++ i2c = devm_kzalloc(dev, sizeof(struct rt_i2c), GFP_KERNEL);
++ if (!i2c) {
++ dev_err(dev, "failed to allocate i2c_adapter\n");
++ return -ENOMEM;
++ }
++
++ i2c->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(i2c->base))
++ return PTR_ERR(i2c->base);
++
++ i2c->clk = devm_clk_get_enabled(dev, NULL);
++ if (IS_ERR(i2c->clk))
++ return dev_err_probe(dev, PTR_ERR(i2c->clk), "no clock defined");
++
++ i2c->dev = dev;
++
++ if (of_property_read_u32(pdev->dev.of_node,
++ "clock-frequency", &i2c->cur_clk))
++ i2c->cur_clk = 100000;
++
++ adap = &i2c->adap;
++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
++ adap->algo = &rt_i2c_algo;
++ adap->retries = 3;
++ adap->dev.parent = dev;
++ i2c_set_adapdata(adap, i2c);
++ adap->dev.of_node = pdev->dev.of_node;
++ strlcpy(adap->name, dev_name(dev), sizeof(adap->name));
++ adap->quirks = &rt_i2c_quirks;
++
++ restart = rt_i2c_init(i2c);
++
++ dev_info(dev, "clock %uKHz, re-start %ssupport\n",
++ i2c->cur_clk/1000, restart ? "" : "not ");
++
++ return devm_i2c_add_adapter(dev, adap);
++}
++
++static struct platform_driver rt_i2c_driver = {
++ .probe = rt_i2c_probe,
++ .driver = {
++ .name = "i2c-ralink",
++ .of_match_table = i2c_rt_dt_ids,
++ },
++};
++
++module_platform_driver(rt_i2c_driver);
++
++MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
++MODULE_DESCRIPTION("Ralink I2c host driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:Ralink-I2C");
--- /dev/null
+From 23147af14531cbdada194b94120ef8774f46292d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 13 Nov 2014 19:08:40 +0100
+Subject: [PATCH 46/53] mmc: MIPS: ralink: add sdhci for mt7620a SoC
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mmc/host/Kconfig | 2 +
+ drivers/mmc/host/Makefile | 1 +
+ drivers/mmc/host/mtk-mmc/Kconfig | 16 +
+ drivers/mmc/host/mtk-mmc/Makefile | 42 +
+ drivers/mmc/host/mtk-mmc/board.h | 137 ++
+ drivers/mmc/host/mtk-mmc/dbg.c | 347 ++++
+ drivers/mmc/host/mtk-mmc/dbg.h | 156 ++
+ drivers/mmc/host/mtk-mmc/mt6575_sd.h | 1001 +++++++++++
+ drivers/mmc/host/mtk-mmc/sd.c | 3060 ++++++++++++++++++++++++++++++++++
+ 9 files changed, 4762 insertions(+)
+ create mode 100644 drivers/mmc/host/mtk-mmc/Kconfig
+ create mode 100644 drivers/mmc/host/mtk-mmc/Makefile
+ create mode 100644 drivers/mmc/host/mtk-mmc/board.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/dbg.c
+ create mode 100644 drivers/mmc/host/mtk-mmc/dbg.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/mt6575_sd.h
+ create mode 100644 drivers/mmc/host/mtk-mmc/sd.c
+
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -1059,6 +1059,8 @@ config MMC_OWL
+ config MMC_SDHCI_EXTERNAL_DMA
+ bool
+
++source "drivers/mmc/host/mtk-mmc/Kconfig"
++
+ config MMC_LITEX
+ tristate "LiteX MMC Host Controller support"
+ depends on ((PPC_MICROWATT || LITEX) && OF && HAVE_CLK) || COMPILE_TEST
+--- a/drivers/mmc/host/Makefile
++++ b/drivers/mmc/host/Makefile
+@@ -3,6 +3,7 @@
+ # Makefile for MMC/SD host controller drivers
+ #
+
++obj-$(CONFIG_MTK_MMC) += mtk-mmc/
+ obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o
+ armmmci-y := mmci.o
+ armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
--- /dev/null
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Wed, 10 Jul 2024 12:18:52 +0800
+Subject: [PATCH] mmc: mtk-sd: initialize the pad and tune registers
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/mmc/host/mtk-sd.c | 26 +++++++++++++++++++++++---
+ 1 file changed, 23 insertions(+), 3 deletions(-)
+
+--- a/drivers/mmc/host/mtk-sd.c
++++ b/drivers/mmc/host/mtk-sd.c
+@@ -75,8 +75,12 @@
+ #define MSDC_PATCH_BIT 0xb0
+ #define MSDC_PATCH_BIT1 0xb4
+ #define MSDC_PATCH_BIT2 0xb8
++#define MSDC_PAD_CTRL0 0xe0
++#define MSDC_PAD_CTRL1 0xe4
++#define MSDC_PAD_CTRL2 0xe8
+ #define MSDC_PAD_TUNE 0xec
+ #define MSDC_PAD_TUNE0 0xf0
++#define MSDC_PAD_TUNE1 0xf4
+ #define PAD_DS_TUNE 0x188
+ #define PAD_CMD_TUNE 0x18c
+ #define EMMC51_CFG0 0x204
+@@ -402,6 +406,7 @@ struct mtk_mmc_compatible {
+ bool enhance_rx;
+ bool support_64g;
+ bool use_internal_cd;
++ bool legacy_mt762x; /* for mt7620, mt7621 and mt76x8 */
+ };
+
+ struct msdc_tune_para {
+@@ -539,6 +544,7 @@ static const struct mtk_mmc_compatible m
+ .stop_clk_fix = false,
+ .enhance_rx = false,
+ .use_internal_cd = true,
++ .legacy_mt762x = true,
+ };
+
+ static const struct mtk_mmc_compatible mt7622_compat = {
+@@ -1731,9 +1737,11 @@ static void msdc_init_hw(struct msdc_hos
+ }
+ writel(0, host->base + MSDC_IOCON);
+ sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
+- writel(0x403c0046, host->base + MSDC_PATCH_BIT);
+- sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
+- writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
++ if(!host->dev_comp->legacy_mt762x) {
++ writel(0x403c0046, host->base + MSDC_PATCH_BIT);
++ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
++ writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
++ }
+ sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
+
+ if (host->dev_comp->stop_clk_fix) {
+@@ -1797,6 +1805,18 @@ static void msdc_init_hw(struct msdc_hos
+ MSDC_PAD_TUNE_RXDLYSEL);
+ }
+
++ if (host->dev_comp->legacy_mt762x) {
++ /* Set pins drive strength */
++ writel(0x000d0044, host->base + MSDC_PAD_CTRL0);
++ writel(0x000e0044, host->base + MSDC_PAD_CTRL1);
++ writel(0x000e0044, host->base + MSDC_PAD_CTRL2);
++
++ /* Set pad delay */
++ writel(0x84101010, host->base + MSDC_PAD_TUNE);
++ writel(0x10101010, host->base + MSDC_PAD_TUNE0);
++ writel(0x10101010, host->base + MSDC_PAD_TUNE1);
++ }
++
+ if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
+ sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
+ sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
--- /dev/null
+From 7f29222b1731e8182ba94a331531dec18865a1e4 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:31:47 +0100
+Subject: [PATCH 48/53] asoc: add mt7620 support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ sound/soc/Kconfig | 1 +
+ sound/soc/Makefile | 1 +
+ sound/soc/ralink/Kconfig | 15 ++
+ sound/soc/ralink/Makefile | 11 +
+ sound/soc/ralink/mt7620-i2s.c | 436 ++++++++++++++++++++++++++++++++++++++
+ sound/soc/ralink/mt7620-wm8960.c | 233 ++++++++++++++++++++
+ 7 files changed, 699 insertions(+)
+ create mode 100644 sound/soc/ralink/Kconfig
+ create mode 100644 sound/soc/ralink/Makefile
+ create mode 100644 sound/soc/ralink/mt7620-i2s.c
+ create mode 100644 sound/soc/ralink/mt7620-wm8960.c
+
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -99,6 +99,7 @@ source "sound/soc/mxs/Kconfig"
+ source "sound/soc/pxa/Kconfig"
+ source "sound/soc/qcom/Kconfig"
+ source "sound/soc/rockchip/Kconfig"
++source "sound/soc/ralink/Kconfig"
+ source "sound/soc/samsung/Kconfig"
+ source "sound/soc/sh/Kconfig"
+ source "sound/soc/sof/Kconfig"
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -56,6 +56,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
+ obj-$(CONFIG_SND_SOC) += pxa/
+ obj-$(CONFIG_SND_SOC) += qcom/
+ obj-$(CONFIG_SND_SOC) += rockchip/
++obj-$(CONFIG_SND_SOC) += ralink/
+ obj-$(CONFIG_SND_SOC) += samsung/
+ obj-$(CONFIG_SND_SOC) += sh/
+ obj-$(CONFIG_SND_SOC) += sof/
+--- /dev/null
++++ b/sound/soc/ralink/Kconfig
+@@ -0,0 +1,8 @@
++config SND_RALINK_SOC_I2S
++ depends on RALINK && SND_SOC && !SOC_RT288X
++ select SND_SOC_GENERIC_DMAENGINE_PCM
++ select REGMAP_MMIO
++ tristate "SoC Audio (I2S protocol) for Ralink SoC"
++ help
++ Say Y if you want to use I2S protocol and I2S codec on Ralink/MediaTek
++ based boards.
+--- /dev/null
++++ b/sound/soc/ralink/Makefile
+@@ -0,0 +1,6 @@
++#
++# Ralink/MediaTek Platform Support
++#
++snd-soc-ralink-i2s-objs := ralink-i2s.o
++
++obj-$(CONFIG_SND_RALINK_SOC_I2S) += snd-soc-ralink-i2s.o
+--- /dev/null
++++ b/sound/soc/ralink/ralink-i2s.c
+@@ -0,0 +1,921 @@
++/*
++ * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
++ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/debugfs.h>
++#include <linux/of_device.h>
++#include <sound/pcm_params.h>
++#include <sound/dmaengine_pcm.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define DRV_NAME "ralink-i2s"
++
++#define I2S_REG_CFG0 0x00
++#define I2S_REG_INT_STATUS 0x04
++#define I2S_REG_INT_EN 0x08
++#define I2S_REG_FF_STATUS 0x0c
++#define I2S_REG_WREG 0x10
++#define I2S_REG_RREG 0x14
++#define I2S_REG_CFG1 0x18
++#define I2S_REG_DIVCMP 0x20
++#define I2S_REG_DIVINT 0x24
++
++/* I2S_REG_CFG0 */
++#define I2S_REG_CFG0_EN BIT(31)
++#define I2S_REG_CFG0_DMA_EN BIT(30)
++#define I2S_REG_CFG0_BYTE_SWAP BIT(28)
++#define I2S_REG_CFG0_TX_EN BIT(24)
++#define I2S_REG_CFG0_RX_EN BIT(20)
++#define I2S_REG_CFG0_SLAVE BIT(16)
++#define I2S_REG_CFG0_RX_THRES 12
++#define I2S_REG_CFG0_TX_THRES 4
++#define I2S_REG_CFG0_THRES_MASK (0xf << I2S_REG_CFG0_RX_THRES) | \
++ (4 << I2S_REG_CFG0_TX_THRES)
++#define I2S_REG_CFG0_DFT_THRES (4 << I2S_REG_CFG0_RX_THRES) | \
++ (4 << I2S_REG_CFG0_TX_THRES)
++/* RT305x */
++#define I2S_REG_CFG0_CLK_DIS BIT(8)
++#define I2S_REG_CFG0_TXCH_SWAP BIT(3)
++#define I2S_REG_CFG0_TXCH1_OFF BIT(2)
++#define I2S_REG_CFG0_TXCH0_OFF BIT(1)
++#define I2S_REG_CFG0_SLAVE_EN BIT(0)
++/* RT3883 */
++#define I2S_REG_CFG0_RXCH_SWAP BIT(11)
++#define I2S_REG_CFG0_RXCH1_OFF BIT(10)
++#define I2S_REG_CFG0_RXCH0_OFF BIT(9)
++#define I2S_REG_CFG0_WS_INV BIT(0)
++/* MT7628 */
++#define I2S_REG_CFG0_FMT_LE BIT(29)
++#define I2S_REG_CFG0_SYS_BE BIT(28)
++#define I2S_REG_CFG0_NORM_24 BIT(18)
++#define I2S_REG_CFG0_DATA_24 BIT(17)
++
++/* I2S_REG_INT_STATUS */
++#define I2S_REG_INT_RX_FAULT BIT(7)
++#define I2S_REG_INT_RX_OVRUN BIT(6)
++#define I2S_REG_INT_RX_UNRUN BIT(5)
++#define I2S_REG_INT_RX_THRES BIT(4)
++#define I2S_REG_INT_TX_FAULT BIT(3)
++#define I2S_REG_INT_TX_OVRUN BIT(2)
++#define I2S_REG_INT_TX_UNRUN BIT(1)
++#define I2S_REG_INT_TX_THRES BIT(0)
++#define I2S_REG_INT_TX_MASK 0xf
++#define I2S_REG_INT_RX_MASK 0xf0
++
++/* I2S_REG_INT_STATUS */
++#define I2S_RX_AVCNT(x) ((x >> 4) & 0xf)
++#define I2S_TX_AVCNT(x) (x & 0xf)
++/* MT7628 */
++#define MT7628_I2S_RX_AVCNT(x) ((x >> 8) & 0x1f)
++#define MT7628_I2S_TX_AVCNT(x) (x & 0x1f)
++
++/* I2S_REG_CFG1 */
++#define I2S_REG_CFG1_LBK BIT(31)
++#define I2S_REG_CFG1_EXTLBK BIT(30)
++/* RT3883 */
++#define I2S_REG_CFG1_LEFT_J BIT(0)
++#define I2S_REG_CFG1_RIGHT_J BIT(1)
++#define I2S_REG_CFG1_FMT_MASK 0x3
++
++/* I2S_REG_DIVCMP */
++#define I2S_REG_DIVCMP_CLKEN BIT(31)
++#define I2S_REG_DIVCMP_DIVCOMP_MASK 0x1ff
++
++/* I2S_REG_DIVINT */
++#define I2S_REG_DIVINT_MASK 0x3ff
++
++/* BCLK dividers */
++#define RALINK_I2S_DIVCMP 0
++#define RALINK_I2S_DIVINT 1
++
++/* FIFO */
++#define RALINK_I2S_FIFO_SIZE 32
++
++/* feature flags */
++#define RALINK_FLAGS_TXONLY BIT(0)
++#define RALINK_FLAGS_LEFT_J BIT(1)
++#define RALINK_FLAGS_RIGHT_J BIT(2)
++#define RALINK_FLAGS_ENDIAN BIT(3)
++#define RALINK_FLAGS_24BIT BIT(4)
++
++#define RALINK_I2S_INT_EN 0
++
++struct ralink_i2s_stats {
++ u32 dmafault;
++ u32 overrun;
++ u32 underrun;
++ u32 belowthres;
++};
++
++struct ralink_i2s {
++ struct device *dev;
++ void __iomem *regs;
++ struct clk *clk;
++ struct regmap *regmap;
++ u32 flags;
++ unsigned int fmt;
++ u16 txdma_req;
++ u16 rxdma_req;
++
++ struct snd_dmaengine_dai_dma_data playback_dma_data;
++ struct snd_dmaengine_dai_dma_data capture_dma_data;
++
++ struct dentry *dbg_dir;
++ struct ralink_i2s_stats txstats;
++ struct ralink_i2s_stats rxstats;
++};
++
++static void ralink_i2s_dump_regs(struct ralink_i2s *i2s)
++{
++ u32 buf[10];
++ int ret;
++
++ ret = regmap_bulk_read(i2s->regmap, I2S_REG_CFG0,
++ buf, ARRAY_SIZE(buf));
++
++ dev_dbg(i2s->dev, "CFG0: %08x, INTSTAT: %08x, INTEN: %08x, " \
++ "FFSTAT: %08x, WREG: %08x, RREG: %08x, " \
++ "CFG1: %08x, DIVCMP: %08x, DIVINT: %08x\n",
++ buf[0], buf[1], buf[2], buf[3], buf[4],
++ buf[5], buf[6], buf[8], buf[9]);
++}
++
++static int ralink_i2s_set_sysclk(struct snd_soc_dai *dai,
++ int clk_id, unsigned int freq, int dir)
++{
++ return 0;
++}
++
++static int ralink_i2s_set_sys_bclk(struct snd_soc_dai *dai, int width, int rate)
++{
++ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ unsigned long clk = clk_get_rate(i2s->clk);
++ int div;
++ uint32_t data;
++
++ /* disable clock at slave mode */
++ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
++ SND_SOC_DAIFMT_CBM_CFM) {
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_CLK_DIS,
++ I2S_REG_CFG0_CLK_DIS);
++ return 0;
++ }
++
++ /* FREQOUT = FREQIN / (I2S_CLK_DIV + 1) */
++ div = (clk / rate ) - 1;
++
++ data = rt_sysc_r32(0x30);
++ data &= (0xff << 8);
++ data |= (0x1 << 15) | (div << 8);
++ rt_sysc_w32(data, 0x30);
++
++ /* enable clock */
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_CLK_DIS, 0);
++
++ dev_dbg(i2s->dev, "clk: %lu, rate: %u, div: %d\n",
++ clk, rate, div);
++
++ return 0;
++}
++
++static int ralink_i2s_set_bclk(struct snd_soc_dai *dai, int width, int rate)
++{
++ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ unsigned long clk = clk_get_rate(i2s->clk);
++ int divint, divcomp;
++
++ /* disable clock at slave mode */
++ if ((i2s->fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
++ SND_SOC_DAIFMT_CBM_CFM) {
++ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
++ I2S_REG_DIVCMP_CLKEN, 0);
++ return 0;
++ }
++
++ /* FREQOUT = FREQIN * (1/2) * (1/(DIVINT + DIVCOMP/512)) */
++ clk = clk / (2 * 2 * width);
++ divint = clk / rate;
++ divcomp = ((clk % rate) * 512) / rate;
++
++ if ((divint > I2S_REG_DIVINT_MASK) ||
++ (divcomp > I2S_REG_DIVCMP_DIVCOMP_MASK))
++ return -EINVAL;
++
++ regmap_update_bits(i2s->regmap, I2S_REG_DIVINT,
++ I2S_REG_DIVINT_MASK, divint);
++ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP,
++ I2S_REG_DIVCMP_DIVCOMP_MASK, divcomp);
++
++ /* enable clock */
++ regmap_update_bits(i2s->regmap, I2S_REG_DIVCMP, I2S_REG_DIVCMP_CLKEN,
++ I2S_REG_DIVCMP_CLKEN);
++
++ dev_dbg(i2s->dev, "clk: %lu, rate: %u, int: %d, comp: %d\n",
++ clk_get_rate(i2s->clk), rate, divint, divcomp);
++
++ return 0;
++}
++
++static int ralink_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ unsigned int cfg0 = 0, cfg1 = 0;
++
++ /* set master/slave audio interface */
++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++ case SND_SOC_DAIFMT_CBM_CFM:
++ if (i2s->flags & RALINK_FLAGS_TXONLY)
++ cfg0 |= I2S_REG_CFG0_SLAVE_EN;
++ else
++ cfg0 |= I2S_REG_CFG0_SLAVE;
++ break;
++ case SND_SOC_DAIFMT_CBS_CFS:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ /* interface format */
++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++ case SND_SOC_DAIFMT_I2S:
++ break;
++ case SND_SOC_DAIFMT_RIGHT_J:
++ if (i2s->flags & RALINK_FLAGS_RIGHT_J) {
++ cfg1 |= I2S_REG_CFG1_RIGHT_J;
++ break;
++ }
++ return -EINVAL;
++ case SND_SOC_DAIFMT_LEFT_J:
++ if (i2s->flags & RALINK_FLAGS_LEFT_J) {
++ cfg1 |= I2S_REG_CFG1_LEFT_J;
++ break;
++ }
++ return -EINVAL;
++ default:
++ return -EINVAL;
++ }
++
++ /* clock inversion */
++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++ case SND_SOC_DAIFMT_NB_NF:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (i2s->flags & RALINK_FLAGS_TXONLY) {
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_SLAVE_EN, cfg0);
++ } else {
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_SLAVE, cfg0);
++ }
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG1,
++ I2S_REG_CFG1_FMT_MASK, cfg1);
++ i2s->fmt = fmt;
++
++ return 0;
++}
++
++static int ralink_i2s_startup(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++
++ if (snd_soc_dai_active(dai))
++ return 0;
++
++ /* setup status interrupt */
++#if (RALINK_I2S_INT_EN)
++ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0xff);
++#else
++ regmap_write(i2s->regmap, I2S_REG_INT_EN, 0x0);
++#endif
++
++ /* enable */
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
++ I2S_REG_CFG0_THRES_MASK,
++ I2S_REG_CFG0_EN | I2S_REG_CFG0_DMA_EN |
++ I2S_REG_CFG0_DFT_THRES);
++
++ return 0;
++}
++
++static void ralink_i2s_shutdown(struct snd_pcm_substream *substream,
++ struct snd_soc_dai *dai)
++{
++ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++
++ /* If both streams are stopped, disable module and clock */
++ if (snd_soc_dai_active(dai))
++ return;
++
++ /*
++ * datasheet mention when disable all control regs are cleared
++ * to initial values. need reinit at startup.
++ */
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, I2S_REG_CFG0_EN, 0);
++}
++
++static int ralink_i2s_hw_params(struct snd_pcm_substream *substream,
++ struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
++{
++ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ int width;
++ int ret;
++
++ width = params_width(params);
++ switch (width) {
++ case 16:
++ if (i2s->flags & RALINK_FLAGS_24BIT)
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_DATA_24, 0);
++ break;
++ case 24:
++ if (i2s->flags & RALINK_FLAGS_24BIT) {
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_DATA_24,
++ I2S_REG_CFG0_DATA_24);
++ break;
++ }
++ return -EINVAL;
++ default:
++ return -EINVAL;
++ }
++
++ switch (params_channels(params)) {
++ case 2:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (i2s->flags & RALINK_FLAGS_ENDIAN) {
++ /* system endian */
++#ifdef SNDRV_LITTLE_ENDIAN
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_SYS_BE, 0);
++#else
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_SYS_BE,
++ I2S_REG_CFG0_SYS_BE);
++#endif
++
++ /* data endian */
++ switch (params_format(params)) {
++ case SNDRV_PCM_FORMAT_S16_LE:
++ case SNDRV_PCM_FORMAT_S24_LE:
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_FMT_LE,
++ I2S_REG_CFG0_FMT_LE);
++ break;
++ case SNDRV_PCM_FORMAT_S16_BE:
++ case SNDRV_PCM_FORMAT_S24_BE:
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0,
++ I2S_REG_CFG0_FMT_LE, 0);
++ break;
++ default:
++ return -EINVAL;
++ }
++ }
++
++ /* setup bclk rate */
++ if (i2s->flags & RALINK_FLAGS_TXONLY)
++ ret = ralink_i2s_set_sys_bclk(dai, width, params_rate(params));
++ else
++ ret = ralink_i2s_set_bclk(dai, width, params_rate(params));
++
++ return ret;
++}
++
++static int ralink_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
++ struct snd_soc_dai *dai)
++{
++ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++ unsigned int mask, val;
++
++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ mask = I2S_REG_CFG0_TX_EN;
++ else
++ mask = I2S_REG_CFG0_RX_EN;
++
++ switch (cmd) {
++ case SNDRV_PCM_TRIGGER_START:
++ case SNDRV_PCM_TRIGGER_RESUME:
++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++ val = mask;
++ break;
++ case SNDRV_PCM_TRIGGER_STOP:
++ case SNDRV_PCM_TRIGGER_SUSPEND:
++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++ val = 0;
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ regmap_update_bits(i2s->regmap, I2S_REG_CFG0, mask, val);
++
++ return 0;
++}
++
++static void ralink_i2s_init_dma_data(struct ralink_i2s *i2s,
++ struct resource *res)
++{
++ struct snd_dmaengine_dai_dma_data *dma_data;
++
++ /* Playback */
++ dma_data = &i2s->playback_dma_data;
++ dma_data->addr = res->start + I2S_REG_WREG;
++ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ dma_data->maxburst = 1;
++
++ if (i2s->flags & RALINK_FLAGS_TXONLY)
++ return;
++
++ /* Capture */
++ dma_data = &i2s->capture_dma_data;
++ dma_data->addr = res->start + I2S_REG_RREG;
++ dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++ dma_data->maxburst = 1;
++}
++
++static int ralink_i2s_dai_probe(struct snd_soc_dai *dai)
++{
++ struct ralink_i2s *i2s = snd_soc_dai_get_drvdata(dai);
++
++ snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
++ &i2s->capture_dma_data);
++
++ return 0;
++}
++
++static int ralink_i2s_dai_remove(struct snd_soc_dai *dai)
++{
++ return 0;
++}
++
++static const struct snd_soc_dai_ops ralink_i2s_dai_ops = {
++ .set_sysclk = ralink_i2s_set_sysclk,
++ .set_fmt = ralink_i2s_set_fmt,
++ .startup = ralink_i2s_startup,
++ .shutdown = ralink_i2s_shutdown,
++ .hw_params = ralink_i2s_hw_params,
++ .trigger = ralink_i2s_trigger,
++ .probe = ralink_i2s_dai_probe,
++ .remove = ralink_i2s_dai_remove,
++};
++
++static struct snd_soc_dai_driver ralink_i2s_dai = {
++ .name = DRV_NAME,
++ .ops = &ralink_i2s_dai_ops,
++ .capture = {
++ .stream_name = "I2S Capture",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rate_min = 5512,
++ .rate_max = 192000,
++ .rates = SNDRV_PCM_RATE_CONTINUOUS,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,
++ },
++ .playback = {
++ .stream_name = "I2S Playback",
++ .channels_min = 2,
++ .channels_max = 2,
++ .rate_min = 5512,
++ .rate_max = 192000,
++ .rates = SNDRV_PCM_RATE_CONTINUOUS,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,
++ },
++ .symmetric_rate = 1,
++};
++
++static struct snd_pcm_hardware ralink_pcm_hardware = {
++ .info = SNDRV_PCM_INFO_MMAP |
++ SNDRV_PCM_INFO_MMAP_VALID |
++ SNDRV_PCM_INFO_INTERLEAVED |
++ SNDRV_PCM_INFO_BLOCK_TRANSFER,
++ .formats = SNDRV_PCM_FMTBIT_S16_LE,
++ .channels_min = 2,
++ .channels_max = 2,
++ .period_bytes_min = PAGE_SIZE,
++ .period_bytes_max = PAGE_SIZE * 2,
++ .periods_min = 2,
++ .periods_max = 128,
++ .buffer_bytes_max = 128 * 1024,
++ .fifo_size = RALINK_I2S_FIFO_SIZE,
++};
++
++static const struct snd_dmaengine_pcm_config ralink_dmaengine_pcm_config = {
++ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
++ .pcm_hardware = &ralink_pcm_hardware,
++ .prealloc_buffer_size = 256 * PAGE_SIZE,
++};
++
++static const struct snd_soc_component_driver ralink_i2s_component = {
++ .name = DRV_NAME,
++};
++
++static bool ralink_i2s_readable_reg(struct device *dev, unsigned int reg)
++{
++ return true;
++}
++
++static bool ralink_i2s_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case I2S_REG_INT_STATUS:
++ case I2S_REG_FF_STATUS:
++ return true;
++ }
++ return false;
++}
++
++static bool ralink_i2s_writeable_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case I2S_REG_FF_STATUS:
++ case I2S_REG_RREG:
++ return false;
++ }
++ return true;
++}
++
++static const struct regmap_config ralink_i2s_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++ .writeable_reg = ralink_i2s_writeable_reg,
++ .readable_reg = ralink_i2s_readable_reg,
++ .volatile_reg = ralink_i2s_volatile_reg,
++ .max_register = I2S_REG_DIVINT,
++};
++
++#if (RALINK_I2S_INT_EN)
++static irqreturn_t ralink_i2s_irq(int irq, void *devid)
++{
++ struct ralink_i2s *i2s = devid;
++ u32 status;
++
++ regmap_read(i2s->regmap, I2S_REG_INT_STATUS, &status);
++ if (unlikely(!status))
++ return IRQ_NONE;
++
++ /* tx stats */
++ if (status & I2S_REG_INT_TX_MASK) {
++ if (status & I2S_REG_INT_TX_THRES)
++ i2s->txstats.belowthres++;
++ if (status & I2S_REG_INT_TX_UNRUN)
++ i2s->txstats.underrun++;
++ if (status & I2S_REG_INT_TX_OVRUN)
++ i2s->txstats.overrun++;
++ if (status & I2S_REG_INT_TX_FAULT)
++ i2s->txstats.dmafault++;
++ }
++
++ /* rx stats */
++ if (status & I2S_REG_INT_RX_MASK) {
++ if (status & I2S_REG_INT_RX_THRES)
++ i2s->rxstats.belowthres++;
++ if (status & I2S_REG_INT_RX_UNRUN)
++ i2s->rxstats.underrun++;
++ if (status & I2S_REG_INT_RX_OVRUN)
++ i2s->rxstats.overrun++;
++ if (status & I2S_REG_INT_RX_FAULT)
++ i2s->rxstats.dmafault++;
++ }
++
++ /* clean status bits */
++ regmap_write(i2s->regmap, I2S_REG_INT_STATUS, status);
++
++ return IRQ_HANDLED;
++}
++#endif
++
++#if IS_ENABLED(CONFIG_DEBUG_FS)
++static int ralink_i2s_stats_show(struct seq_file *s, void *unused)
++{
++ struct ralink_i2s *i2s = s->private;
++
++ seq_printf(s, "tx stats\n");
++ seq_printf(s, "\tbelow threshold\t%u\n", i2s->txstats.belowthres);
++ seq_printf(s, "\tunder run\t%u\n", i2s->txstats.underrun);
++ seq_printf(s, "\tover run\t%u\n", i2s->txstats.overrun);
++ seq_printf(s, "\tdma fault\t%u\n", i2s->txstats.dmafault);
++
++ seq_printf(s, "rx stats\n");
++ seq_printf(s, "\tbelow threshold\t%u\n", i2s->rxstats.belowthres);
++ seq_printf(s, "\tunder run\t%u\n", i2s->rxstats.underrun);
++ seq_printf(s, "\tover run\t%u\n", i2s->rxstats.overrun);
++ seq_printf(s, "\tdma fault\t%u\n", i2s->rxstats.dmafault);
++
++ ralink_i2s_dump_regs(i2s);
++
++ return 0;
++}
++
++static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
++{
++ i2s->dbg_dir = debugfs_create_dir(dev_name(i2s->dev), NULL);
++ if (!i2s->dbg_dir)
++ return -ENOMEM;
++
++ debugfs_create_devm_seqfile(i2s->dev, "stats", i2s->dbg_dir,
++ &ralink_i2s_stats_show);
++
++ return 0;
++}
++
++static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
++{
++ debugfs_remove(i2s->dbg_dir);
++}
++#else
++static inline int ralink_i2s_debugfs_create(struct ralink_i2s *i2s)
++{
++ return 0;
++}
++
++static inline void ralink_i2s_debugfs_remove(struct ralink_i2s *i2s)
++{
++}
++#endif
++
++/*
++ * TODO: these refclk setup functions should use
++ * clock framework instead. hardcode it now.
++ */
++static void rt3350_refclk_setup(void)
++{
++ uint32_t data;
++
++ /* set refclk output 12Mhz clock */
++ data = rt_sysc_r32(0x2c);
++ data |= (0x1 << 8);
++ rt_sysc_w32(data, 0x2c);
++}
++
++static void rt3883_refclk_setup(void)
++{
++ uint32_t data;
++
++ /* set refclk output 12Mhz clock */
++ data = rt_sysc_r32(0x2c);
++ data &= ~(0x3 << 13);
++ data |= (0x1 << 13);
++ rt_sysc_w32(data, 0x2c);
++}
++
++static void rt3552_refclk_setup(void)
++{
++ uint32_t data;
++
++ /* set refclk output 12Mhz clock */
++ data = rt_sysc_r32(0x2c);
++ data &= ~(0xf << 8);
++ data |= (0x3 << 8);
++ rt_sysc_w32(data, 0x2c);
++}
++
++static void mt7620_refclk_setup(void)
++{
++ uint32_t data;
++
++ /* set refclk output 12Mhz clock */
++ data = rt_sysc_r32(0x2c);
++ data &= ~(0x7 << 9);
++ data |= 0x1 << 9;
++ rt_sysc_w32(data, 0x2c);
++}
++
++static void mt7621_refclk_setup(void)
++{
++ uint32_t data;
++
++ /* set refclk output 12Mhz clock */
++ data = rt_sysc_r32(0x2c);
++ data &= ~(0x1f << 18);
++ data |= (0x19 << 18);
++ data &= ~(0x1f << 12);
++ data |= (0x1 << 12);
++ data &= ~(0x7 << 9);
++ data |= (0x5 << 9);
++ rt_sysc_w32(data, 0x2c);
++}
++
++static void mt7628_refclk_setup(void)
++{
++ uint32_t data;
++
++ /* set i2s and refclk digital pad */
++ data = rt_sysc_r32(0x3c);
++ data |= 0x1f;
++ rt_sysc_w32(data, 0x3c);
++
++ /* Adjust REFCLK0's driving strength */
++ data = rt_sysc_r32(0x1354);
++ data &= ~(0x1 << 5);
++ rt_sysc_w32(data, 0x1354);
++ data = rt_sysc_r32(0x1364);
++ data |= ~(0x1 << 5);
++ rt_sysc_w32(data, 0x1364);
++
++ /* set refclk output 12Mhz clock */
++ data = rt_sysc_r32(0x2c);
++ data &= ~(0x7 << 9);
++ data |= 0x1 << 9;
++ rt_sysc_w32(data, 0x2c);
++}
++
++struct rt_i2s_data {
++ u32 flags;
++ void (*refclk_setup)(void);
++};
++
++struct rt_i2s_data rt3050_i2s_data = { .flags = RALINK_FLAGS_TXONLY };
++struct rt_i2s_data rt3350_i2s_data = { .flags = RALINK_FLAGS_TXONLY,
++ .refclk_setup = rt3350_refclk_setup };
++struct rt_i2s_data rt3883_i2s_data = {
++ .flags = (RALINK_FLAGS_LEFT_J | RALINK_FLAGS_RIGHT_J),
++ .refclk_setup = rt3883_refclk_setup };
++struct rt_i2s_data rt3352_i2s_data = { .refclk_setup = rt3552_refclk_setup};
++struct rt_i2s_data mt7620_i2s_data = { .refclk_setup = mt7620_refclk_setup};
++struct rt_i2s_data mt7621_i2s_data = { .refclk_setup = mt7621_refclk_setup};
++struct rt_i2s_data mt7628_i2s_data = {
++ .flags = (RALINK_FLAGS_ENDIAN | RALINK_FLAGS_24BIT |
++ RALINK_FLAGS_LEFT_J),
++ .refclk_setup = mt7628_refclk_setup};
++
++static const struct of_device_id ralink_i2s_match_table[] = {
++ { .compatible = "ralink,rt3050-i2s",
++ .data = (void *)&rt3050_i2s_data },
++ { .compatible = "ralink,rt3350-i2s",
++ .data = (void *)&rt3350_i2s_data },
++ { .compatible = "ralink,rt3883-i2s",
++ .data = (void *)&rt3883_i2s_data },
++ { .compatible = "ralink,rt3352-i2s",
++ .data = (void *)&rt3352_i2s_data },
++ { .compatible = "mediatek,mt7620-i2s",
++ .data = (void *)&mt7620_i2s_data },
++ { .compatible = "mediatek,mt7621-i2s",
++ .data = (void *)&mt7621_i2s_data },
++ { .compatible = "mediatek,mt7628-i2s",
++ .data = (void *)&mt7628_i2s_data },
++ {},
++};
++MODULE_DEVICE_TABLE(of, ralink_i2s_match_table);
++
++static int ralink_i2s_probe(struct platform_device *pdev)
++{
++ const struct of_device_id *match;
++ struct device_node *np = pdev->dev.of_node;
++ struct device *dev = &pdev->dev;
++ struct resource *res;
++ struct ralink_i2s *i2s;
++ int irq, ret;
++ u32 dma_req;
++ struct rt_i2s_data *data;
++
++ i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
++ if (!i2s)
++ return -ENOMEM;
++
++ i2s->dev = dev;
++
++ match = of_match_device(ralink_i2s_match_table, dev);
++ if (!match)
++ return -EINVAL;
++ data = (struct rt_i2s_data *)match->data;
++ i2s->flags = data->flags;
++ /* setup out 12Mhz refclk to codec as mclk */
++ if (data->refclk_setup)
++ data->refclk_setup();
++
++ if (of_property_read_u32(np, "txdma-req", &dma_req)) {
++ dev_err(dev, "no txdma-req define\n");
++ return -EINVAL;
++ }
++ i2s->txdma_req = (u16)dma_req;
++ if (!(i2s->flags & RALINK_FLAGS_TXONLY)) {
++ if (of_property_read_u32(np, "rxdma-req", &dma_req)) {
++ dev_err(dev, "no rxdma-req define\n");
++ return -EINVAL;
++ }
++ i2s->rxdma_req = (u16)dma_req;
++ }
++
++ i2s->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
++ if (IS_ERR(i2s->regs))
++ return PTR_ERR(i2s->regs);
++
++ i2s->regmap = devm_regmap_init_mmio(dev, i2s->regs,
++ &ralink_i2s_regmap_config);
++ if (IS_ERR(i2s->regmap))
++ return dev_err_probe(dev, PTR_ERR(i2s->regmap), "regmap init failed");
++
++ irq = platform_get_irq(pdev, 0);
++ if (irq < 0) {
++ dev_err(dev, "failed to get irq\n");
++ return -EINVAL;
++ }
++
++#if (RALINK_I2S_INT_EN)
++ ret = devm_request_irq(dev, irq, ralink_i2s_irq,
++ 0, dev_name(dev), i2s);
++ if (ret)
++ return dev_err_probe(dev, ret, "failed to request irq");
++#endif
++
++ i2s->clk = devm_clk_get_enabled(dev, NULL);
++ if (IS_ERR(i2s->clk))
++ return dev_err_probe(dev, PTR_ERR(i2s->clk), "no clock defined");
++
++ ralink_i2s_init_dma_data(i2s, res);
++
++ ret = device_reset(dev);
++ if (ret)
++ return dev_err_probe(dev, ret, "failed to reset device\n");
++
++ /* enable 24bits support */
++ if (i2s->flags & RALINK_FLAGS_24BIT) {
++ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
++ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
++ }
++
++ /* enable big endian support */
++ if (i2s->flags & RALINK_FLAGS_ENDIAN) {
++ ralink_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S16_BE;
++ ralink_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S16_BE;
++ ralink_pcm_hardware.formats |= SNDRV_PCM_FMTBIT_S16_BE;
++ if (i2s->flags & RALINK_FLAGS_24BIT) {
++ ralink_i2s_dai.capture.formats |=
++ SNDRV_PCM_FMTBIT_S24_BE;
++ ralink_i2s_dai.playback.formats |=
++ SNDRV_PCM_FMTBIT_S24_BE;
++ ralink_pcm_hardware.formats |=
++ SNDRV_PCM_FMTBIT_S24_BE;
++ }
++ }
++
++ /* disable capture support */
++ if (i2s->flags & RALINK_FLAGS_TXONLY)
++ memset(&ralink_i2s_dai.capture, sizeof(ralink_i2s_dai.capture),
++ 0);
++
++ ret = devm_snd_soc_register_component(dev, &ralink_i2s_component,
++ &ralink_i2s_dai, 1);
++ if (ret)
++ return ret;
++
++ ret = devm_snd_dmaengine_pcm_register(dev,
++ &ralink_dmaengine_pcm_config,
++ SND_DMAENGINE_PCM_FLAG_COMPAT);
++ if (ret)
++ return ret;
++
++ dev_info(i2s->dev, "mclk %luMHz\n", clk_get_rate(i2s->clk) / 1000000);
++
++ platform_set_drvdata(pdev, i2s);
++ return ralink_i2s_debugfs_create(i2s);
++}
++
++static void ralink_i2s_remove(struct platform_device *pdev)
++{
++ struct ralink_i2s *i2s = platform_get_drvdata(pdev);
++
++ ralink_i2s_debugfs_remove(i2s);
++}
++
++static struct platform_driver ralink_i2s_driver = {
++ .probe = ralink_i2s_probe,
++ .remove_new = ralink_i2s_remove,
++ .driver = {
++ .name = DRV_NAME,
++ .of_match_table = ralink_i2s_match_table,
++ },
++};
++module_platform_driver(ralink_i2s_driver);
++
++MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
++MODULE_DESCRIPTION("Ralink/MediaTek I2S driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:" DRV_NAME);
--- /dev/null
+From a7eb46e0ea4a11e4dfb56ab129bf816d1059a6c5 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 7 Dec 2015 17:31:08 +0100
+Subject: [PATCH 51/53] serial: add ugly custom baud rate hack
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/serial_core.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/tty/serial/serial_core.c
++++ b/drivers/tty/serial/serial_core.c
+@@ -482,6 +482,9 @@ uart_get_baud_rate(struct uart_port *por
+ break;
+ }
+
++ if (tty_termios_baud_rate(termios) == 2500000)
++ return 250000;
++
+ for (try = 0; try < 2; try++) {
+ baud = tty_termios_baud_rate(termios);
+
--- /dev/null
+From fc8f96309c21c1bc3276427309cd7d361347d66e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 7 Dec 2015 17:16:50 +0100
+Subject: [PATCH 52/53] pwm: add mediatek support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/pwm/Kconfig | 9 +++
+ drivers/pwm/Makefile | 1 +
+ drivers/pwm/pwm-mediatek.c | 173 ++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 183 insertions(+)
+ create mode 100644 drivers/pwm/pwm-mediatek.c
+
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -415,6 +415,15 @@ config PWM_MICROCHIP_CORE
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-microchip-core.
+
++config PWM_MEDIATEK_RAMIPS
++ tristate "Mediatek PWM support"
++ depends on RALINK && OF
++ help
++ Generic PWM framework driver for Mediatek ARM SoC.
++
++ To compile this driver as a module, choose M here: the module
++ will be called pwm-mxs.
++
+ config PWM_MXS
+ tristate "Freescale MXS PWM support"
+ depends on ARCH_MXS || COMPILE_TEST
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p
+ obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
+ obj-$(CONFIG_PWM_MESON) += pwm-meson.o
+ obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
++obj-$(CONFIG_PWM_MEDIATEK_RAMIPS) += pwm-mediatek-ramips.o
+ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o
+ obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
+ obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
+--- /dev/null
++++ b/drivers/pwm/pwm-mediatek-ramips.c
+@@ -0,0 +1,185 @@
++/*
++ * Mediatek Pulse Width Modulator driver
++ *
++ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/ioport.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pwm.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++
++#define NUM_PWM 4
++
++/* PWM registers and bits definitions */
++#define PWMCON 0x00
++#define PWMHDUR 0x04
++#define PWMLDUR 0x08
++#define PWMGDUR 0x0c
++#define PWMWAVENUM 0x28
++#define PWMDWIDTH 0x2c
++#define PWMTHRES 0x30
++
++/**
++ * struct mtk_pwm_chip - struct representing pwm chip
++ *
++ * @mmio_base: base address of pwm chip
++ * @chip: linux pwm chip representation
++ */
++struct mtk_pwm_chip {
++ void __iomem *mmio_base;
++ struct pwm_chip chip;
++};
++
++static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
++{
++ return container_of(chip, struct mtk_pwm_chip, chip);
++}
++
++static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
++ unsigned long offset)
++{
++ return ioread32(chip->mmio_base + 0x10 + (num * 0x40) + offset);
++}
++
++static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
++ unsigned int num, unsigned long offset,
++ unsigned long val)
++{
++ iowrite32(val, chip->mmio_base + 0x10 + (num * 0x40) + offset);
++}
++
++static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++ int duty_ns, int period_ns)
++{
++ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++ u32 resolution = 100 / 4;
++ u32 clkdiv = 0;
++
++ while (period_ns / resolution > 8191) {
++ clkdiv++;
++ resolution *= 2;
++ }
++
++ if (clkdiv > 7)
++ return -1;
++
++ mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
++ mtk_pwm_writel(pc, pwm->hwpwm, PWMDWIDTH, period_ns / resolution);
++ mtk_pwm_writel(pc, pwm->hwpwm, PWMTHRES, duty_ns / resolution);
++ return 0;
++}
++
++static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++ u32 val;
++
++ val = ioread32(pc->mmio_base);
++ val |= BIT(pwm->hwpwm);
++ iowrite32(val, pc->mmio_base);
++
++ return 0;
++}
++
++static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++ struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip);
++ u32 val;
++
++ val = ioread32(pc->mmio_base);
++ val &= ~BIT(pwm->hwpwm);
++ iowrite32(val, pc->mmio_base);
++}
++
++static int mtk_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
++ const struct pwm_state *state)
++{
++ int err;
++ bool enabled = pwm->state.enabled;
++
++ if (!state->enabled) {
++ if (enabled)
++ mtk_pwm_disable(chip, pwm);
++
++ return 0;
++ }
++
++ err = mtk_pwm_config(pwm->chip, pwm,
++ state->duty_cycle, state->period);
++ if (err)
++ return err;
++
++ if (!enabled)
++ err = mtk_pwm_enable(chip, pwm);
++
++ return err;
++}
++
++static const struct pwm_ops mtk_pwm_ops = {
++ .apply = mtk_pwm_apply,
++ .owner = THIS_MODULE,
++};
++
++static int mtk_pwm_probe(struct platform_device *pdev)
++{
++ struct mtk_pwm_chip *pc;
++
++ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
++ if (!pc)
++ return -ENOMEM;
++
++ pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(pc->mmio_base))
++ return PTR_ERR(pc->mmio_base);
++
++ pc->chip.dev = &pdev->dev;
++ pc->chip.ops = &mtk_pwm_ops;
++ pc->chip.base = -1;
++ pc->chip.npwm = NUM_PWM;
++
++ platform_set_drvdata(pdev, pc);
++
++ return devm_pwmchip_add(&pdev->dev, &pc->chip);
++}
++
++static void mtk_pwm_remove(struct platform_device *pdev)
++{
++ struct mtk_pwm_chip *pc = platform_get_drvdata(pdev);
++ int i;
++
++ for (i = 0; i < NUM_PWM; i++)
++ pwm_disable(&pc->chip.pwms[i]);
++}
++
++static const struct of_device_id mtk_pwm_of_match[] = {
++ { .compatible = "mediatek,mt7628-pwm" },
++ { }
++};
++
++MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
++
++static struct platform_driver mtk_pwm_driver = {
++ .driver = {
++ .name = "mtk-pwm",
++ .of_match_table = mtk_pwm_of_match,
++ },
++ .probe = mtk_pwm_probe,
++ .remove_new = mtk_pwm_remove,
++};
++
++module_platform_driver(mtk_pwm_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
++MODULE_ALIAS("platform:mtk-pwm");
--- /dev/null
+--- a/drivers/usb/dwc2/platform.c
++++ b/drivers/usb/dwc2/platform.c
+@@ -481,6 +481,12 @@ static int dwc2_driver_probe(struct plat
+ if (retval)
+ return retval;
+
++ /* Enable USB port before any regs access */
++ if (readl(hsotg->regs + PCGCTL) & 0x0f) {
++ writel(0x00, hsotg->regs + PCGCTL);
++ /* TODO: mdelay(25) here? vendor driver don't use it */
++ }
++
+ hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg);
+
+ retval = dwc2_get_dr_mode(hsotg);
--- /dev/null
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/Kconfig
+@@ -0,0 +1,64 @@
++# SPDX-License-Identifier: GPL-2.0
++config CRYPTO_DEV_EIP93_SKCIPHER
++ tristate
++
++config CRYPTO_DEV_EIP93_HMAC
++ tristate
++
++config CRYPTO_DEV_EIP93
++ tristate "Support for EIP93 crypto HW accelerators"
++ depends on SOC_MT7621 || COMPILE_TEST
++ help
++ EIP93 have various crypto HW accelerators. Select this if
++ you want to use the EIP93 modules for any of the crypto algorithms.
++
++if CRYPTO_DEV_EIP93
++
++config CRYPTO_DEV_EIP93_AES
++ bool "Register AES algorithm implementations with the Crypto API"
++ default y
++ select CRYPTO_DEV_EIP93_SKCIPHER
++ select CRYPTO_LIB_AES
++ select CRYPTO_SKCIPHER
++ help
++ Selecting this will offload AES - ECB, CBC and CTR crypto
++ to the EIP-93 crypto engine.
++
++config CRYPTO_DEV_EIP93_DES
++ bool "Register legacy DES / 3DES algorithm with the Crypto API"
++ default y
++ select CRYPTO_DEV_EIP93_SKCIPHER
++ select CRYPTO_LIB_DES
++ select CRYPTO_SKCIPHER
++ help
++ Selecting this will offload DES and 3DES ECB and CBC
++ crypto to the EIP-93 crypto engine.
++
++config CRYPTO_DEV_EIP93_AEAD
++ bool "Register AEAD algorithm with the Crypto API"
++ default y
++ select CRYPTO_DEV_EIP93_HMAC
++ select CRYPTO_AEAD
++ select CRYPTO_AUTHENC
++ select CRYPTO_MD5
++ select CRYPTO_SHA1
++ select CRYPTO_SHA256
++ help
++ Selecting this will offload AEAD authenc(hmac(x), cipher(y))
++ crypto to the EIP-93 crypto engine.
++
++config CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN
++ int "Max skcipher software fallback length"
++ default 256
++ help
++ Max length of crypt request which
++ will fallback to software crypt of skcipher *except* AES-128.
++
++config CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN
++ int "Max AES-128 skcipher software fallback length"
++ default 512
++ help
++ Max length of crypt request which
++ will fallback to software crypt of AES-128 skcipher.
++
++endif
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/Makefile
+@@ -0,0 +1,7 @@
++obj-$(CONFIG_CRYPTO_DEV_EIP93) += crypto-hw-eip93.o
++
++crypto-hw-eip93-y += eip93-main.o eip93-common.o
++
++crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER) += eip93-cipher.o
++crypto-hw-eip93-$(CONFIG_CRYPTO_DEV_EIP93_AEAD) += eip93-aead.o
++
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-aead.c
+@@ -0,0 +1,768 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#include <crypto/aead.h>
++#include <crypto/aes.h>
++#include <crypto/authenc.h>
++#include <crypto/ctr.h>
++#include <crypto/hmac.h>
++#include <crypto/internal/aead.h>
++#include <crypto/md5.h>
++#include <crypto/null.h>
++#include <crypto/sha1.h>
++#include <crypto/sha2.h>
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++#include <crypto/internal/des.h>
++#endif
++
++#include <linux/crypto.h>
++#include <linux/dma-mapping.h>
++
++#include "eip93-aead.h"
++#include "eip93-cipher.h"
++#include "eip93-common.h"
++#include "eip93-regs.h"
++
++void mtk_aead_handle_result(struct crypto_async_request *async, int err)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
++ struct mtk_device *mtk = ctx->mtk;
++ struct aead_request *req = aead_request_cast(async);
++ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++
++ mtk_unmap_dma(mtk, rctx, req->src, req->dst);
++ mtk_handle_result(mtk, rctx, req->iv);
++
++ if (err == 1)
++ err = -EBADMSG;
++ /* let software handle anti-replay errors */
++ if (err == 4)
++ err = 0;
++
++ aead_request_complete(req, err);
++}
++
++static int mtk_aead_send_req(struct crypto_async_request *async)
++{
++ struct aead_request *req = aead_request_cast(async);
++ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++ int err;
++
++ err = check_valid_request(rctx);
++ if (err) {
++ aead_request_complete(req, err);
++ return err;
++ }
++
++ return mtk_send_req(async, req->iv, rctx);
++}
++
++/* Crypto aead API functions */
++static int mtk_aead_cra_init(struct crypto_tfm *tfm)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
++ struct mtk_alg_template, alg.aead.base);
++ u32 flags = tmpl->flags;
++ char *alg_base;
++
++ crypto_aead_set_reqsize(__crypto_aead_cast(tfm),
++ sizeof(struct mtk_cipher_reqctx));
++
++ ctx->mtk = tmpl->mtk;
++ ctx->in_first = true;
++ ctx->out_first = true;
++
++ ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
++ if (!ctx->sa_in)
++ return -ENOMEM;
++
++ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++ ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
++ if (!ctx->sa_out)
++ return -ENOMEM;
++
++ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++ /* software workaround for now */
++ if (IS_HASH_MD5(flags))
++ alg_base = "md5";
++ if (IS_HASH_SHA1(flags))
++ alg_base = "sha1";
++ if (IS_HASH_SHA224(flags))
++ alg_base = "sha224";
++ if (IS_HASH_SHA256(flags))
++ alg_base = "sha256";
++
++ ctx->shash = crypto_alloc_shash(alg_base, 0, CRYPTO_ALG_NEED_FALLBACK);
++
++ if (IS_ERR(ctx->shash)) {
++ dev_err(ctx->mtk->dev, "base driver %s could not be loaded.\n",
++ alg_base);
++ return PTR_ERR(ctx->shash);
++ }
++
++ return 0;
++}
++
++static void mtk_aead_cra_exit(struct crypto_tfm *tfm)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++
++ if (ctx->shash)
++ crypto_free_shash(ctx->shash);
++
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ kfree(ctx->sa_in);
++ kfree(ctx->sa_out);
++}
++
++static int mtk_aead_setkey(struct crypto_aead *ctfm, const u8 *key,
++ unsigned int len)
++{
++ struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
++ struct mtk_alg_template, alg.skcipher.base);
++ u32 flags = tmpl->flags;
++ u32 nonce = 0;
++ struct crypto_authenc_keys keys;
++ struct crypto_aes_ctx aes;
++ struct saRecord_s *saRecord = ctx->sa_out;
++ int sa_size = sizeof(struct saRecord_s);
++ int err = -EINVAL;
++
++
++ if (crypto_authenc_extractkeys(&keys, key, len))
++ return err;
++
++ if (IS_RFC3686(flags)) {
++ if (keys.enckeylen < CTR_RFC3686_NONCE_SIZE)
++ return err;
++
++ keys.enckeylen -= CTR_RFC3686_NONCE_SIZE;
++ memcpy(&nonce, keys.enckey + keys.enckeylen,
++ CTR_RFC3686_NONCE_SIZE);
++ }
++
++ switch ((flags & MTK_ALG_MASK)) {
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++ case MTK_ALG_DES:
++ err = verify_aead_des_key(ctfm, keys.enckey, keys.enckeylen);
++ break;
++ case MTK_ALG_3DES:
++ if (keys.enckeylen != DES3_EDE_KEY_SIZE)
++ return -EINVAL;
++
++ err = verify_aead_des3_key(ctfm, keys.enckey, keys.enckeylen);
++ break;
++#endif
++ case MTK_ALG_AES:
++ err = aes_expandkey(&aes, keys.enckey, keys.enckeylen);
++ }
++ if (err)
++ return err;
++
++ ctx->blksize = crypto_aead_blocksize(ctfm);
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size,
++ DMA_TO_DEVICE);
++
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size,
++ DMA_TO_DEVICE);
++ /* Encryption key */
++ mtk_set_saRecord(saRecord, keys.enckeylen, flags);
++ saRecord->saCmd0.bits.opCode = 1;
++ saRecord->saCmd0.bits.digestLength = ctx->authsize >> 2;
++
++ memcpy(saRecord->saKey, keys.enckey, keys.enckeylen);
++ ctx->saNonce = nonce;
++ saRecord->saNonce = nonce;
++
++ /* authentication key */
++ err = mtk_authenc_setkey(ctx->shash, saRecord, keys.authkey,
++ keys.authkeylen);
++
++ saRecord->saCmd0.bits.direction = 0;
++ memcpy(ctx->sa_in, saRecord, sa_size);
++ ctx->sa_in->saCmd0.bits.direction = 1;
++ ctx->sa_in->saCmd1.bits.copyDigest = 0;
++
++ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size,
++ DMA_TO_DEVICE);
++ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size,
++ DMA_TO_DEVICE);
++ ctx->in_first = true;
++ ctx->out_first = true;
++
++ return err;
++}
++
++static int mtk_aead_setauthsize(struct crypto_aead *ctfm,
++ unsigned int authsize)
++{
++ struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++ ctx->authsize = authsize;
++ ctx->sa_in->saCmd0.bits.digestLength = ctx->authsize >> 2;
++ ctx->sa_out->saCmd0.bits.digestLength = ctx->authsize >> 2;
++
++ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ return 0;
++}
++
++static void mtk_aead_setassoc(struct mtk_crypto_ctx *ctx,
++ struct aead_request *req, bool in)
++{
++ struct saRecord_s *saRecord;
++
++ if (in) {
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ saRecord = ctx->sa_in;
++ saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2;
++
++ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ ctx->assoclen_in = req->assoclen;
++ } else {
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ saRecord = ctx->sa_out;
++ saRecord->saCmd1.bits.hashCryptOffset = req->assoclen >> 2;
++
++ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ ctx->assoclen_out = req->assoclen;
++ }
++}
++
++static int mtk_aead_crypt(struct aead_request *req)
++{
++ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++ struct crypto_async_request *async = &req->base;
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++ struct crypto_aead *aead = crypto_aead_reqtfm(req);
++
++ rctx->textsize = req->cryptlen;
++ rctx->blksize = ctx->blksize;
++ rctx->assoclen = req->assoclen;
++ rctx->authsize = ctx->authsize;
++ rctx->sg_src = req->src;
++ rctx->sg_dst = req->dst;
++ rctx->ivsize = crypto_aead_ivsize(aead);
++ rctx->flags |= MTK_DESC_AEAD;
++
++ if IS_DECRYPT(rctx->flags)
++ rctx->textsize -= rctx->authsize;
++
++ return mtk_aead_send_req(async);
++}
++
++static int mtk_aead_encrypt(struct aead_request *req)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
++ struct mtk_alg_template, alg.aead.base);
++
++ rctx->flags = tmpl->flags;
++ rctx->flags |= MTK_ENCRYPT;
++ if (ctx->out_first) {
++ mtk_aead_setassoc(ctx, req, false);
++ ctx->out_first = false;
++ }
++
++ if (req->assoclen != ctx->assoclen_out) {
++ dev_err(ctx->mtk->dev, "Request AAD length error\n");
++ return -EINVAL;
++ }
++
++ rctx->saRecord_base = ctx->sa_base_out;
++
++ return mtk_aead_crypt(req);
++}
++
++static int mtk_aead_decrypt(struct aead_request *req)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++ struct mtk_cipher_reqctx *rctx = aead_request_ctx(req);
++ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
++ struct mtk_alg_template, alg.aead.base);
++
++ rctx->flags = tmpl->flags;
++ rctx->flags |= MTK_DECRYPT;
++ if (ctx->in_first) {
++ mtk_aead_setassoc(ctx, req, true);
++ ctx->in_first = false;
++ }
++
++ if (req->assoclen != ctx->assoclen_in) {
++ dev_err(ctx->mtk->dev, "Request AAD length error\n");
++ return -EINVAL;
++ }
++
++ rctx->saRecord_base = ctx->sa_base_in;
++
++ return mtk_aead_crypt(req);
++}
++
++/* Available authenc algorithms in this module */
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_AES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = AES_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = MD5_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(md5),cbc(aes))",
++ .cra_driver_name =
++ "authenc(hmac(md5-eip93), cbc(aes-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = AES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_AES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = AES_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA1_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha1),cbc(aes))",
++ .cra_driver_name =
++ "authenc(hmac(sha1-eip93),cbc(aes-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = AES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_AES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = AES_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA224_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha224),cbc(aes))",
++ .cra_driver_name =
++ "authenc(hmac(sha224-eip93),cbc(aes-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = AES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_AES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = AES_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA256_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha256),cbc(aes))",
++ .cra_driver_name =
++ "authenc(hmac(sha256-eip93),cbc(aes-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = AES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 |
++ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = CTR_RFC3686_IV_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = MD5_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(md5),rfc3686(ctr(aes)))",
++ .cra_driver_name =
++ "authenc(hmac(md5-eip93),rfc3686(ctr(aes-eip93)))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = 1,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 |
++ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = CTR_RFC3686_IV_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA1_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
++ .cra_driver_name =
++ "authenc(hmac(sha1-eip93),rfc3686(ctr(aes-eip93)))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = 1,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 |
++ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = CTR_RFC3686_IV_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA224_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha224),rfc3686(ctr(aes)))",
++ .cra_driver_name =
++ "authenc(hmac(sha224-eip93),rfc3686(ctr(aes-eip93)))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = 1,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 |
++ MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = CTR_RFC3686_IV_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA256_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
++ .cra_driver_name =
++ "authenc(hmac(sha256-eip93),rfc3686(ctr(aes-eip93)))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = 1,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_DES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = DES_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = MD5_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(md5),cbc(des))",
++ .cra_driver_name =
++ "authenc(hmac(md5-eip93),cbc(des-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_DES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = DES_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA1_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha1),cbc(des))",
++ .cra_driver_name =
++ "authenc(hmac(sha1-eip93),cbc(des-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_DES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = DES_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA224_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha224),cbc(des))",
++ .cra_driver_name =
++ "authenc(hmac(sha224-eip93),cbc(des-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_DES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = DES_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA256_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha256),cbc(des))",
++ .cra_driver_name =
++ "authenc(hmac(sha256-eip93),cbc(des-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_MD5 | MTK_MODE_CBC | MTK_ALG_3DES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = MD5_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
++ .cra_driver_name =
++ "authenc(hmac(md5-eip93),cbc(des3_ede-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0x0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA1 | MTK_MODE_CBC | MTK_ALG_3DES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA1_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
++ .cra_driver_name =
++ "authenc(hmac(sha1-eip93),cbc(des3_ede-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0x0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA224 | MTK_MODE_CBC | MTK_ALG_3DES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA224_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha224),cbc(des3_ede))",
++ .cra_driver_name =
++ "authenc(hmac(sha224-eip93),cbc(des3_ede-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0x0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede = {
++ .type = MTK_ALG_TYPE_AEAD,
++ .flags = MTK_HASH_HMAC | MTK_HASH_SHA256 | MTK_MODE_CBC | MTK_ALG_3DES,
++ .alg.aead = {
++ .setkey = mtk_aead_setkey,
++ .encrypt = mtk_aead_encrypt,
++ .decrypt = mtk_aead_decrypt,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ .setauthsize = mtk_aead_setauthsize,
++ .maxauthsize = SHA256_DIGEST_SIZE,
++ .base = {
++ .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
++ .cra_driver_name =
++ "authenc(hmac(sha256-eip93),cbc(des3_ede-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0x0,
++ .cra_init = mtk_aead_cra_init,
++ .cra_exit = mtk_aead_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++#endif
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-aead.h
+@@ -0,0 +1,31 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_AEAD_H_
++#define _EIP93_AEAD_H_
++
++extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_rfc3686_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_rfc3686_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_rfc3686_aes;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_rfc3686_aes;
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_md5_cbc_des3_ede;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha1_cbc_des3_ede;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha224_cbc_des3_ede;
++extern struct mtk_alg_template mtk_alg_authenc_hmac_sha256_cbc_des3_ede;
++#endif
++
++void mtk_aead_handle_result(struct crypto_async_request *async, int err);
++
++#endif /* _EIP93_AEAD_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-aes.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_AES_H_
++#define _EIP93_AES_H_
++
++extern struct mtk_alg_template mtk_alg_ecb_aes;
++extern struct mtk_alg_template mtk_alg_cbc_aes;
++extern struct mtk_alg_template mtk_alg_ctr_aes;
++extern struct mtk_alg_template mtk_alg_rfc3686_aes;
++
++#endif /* _EIP93_AES_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-cipher.c
+@@ -0,0 +1,483 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++#include <crypto/aes.h>
++#include <crypto/ctr.h>
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++#include <crypto/internal/des.h>
++#endif
++#include <linux/dma-mapping.h>
++
++#include "eip93-cipher.h"
++#include "eip93-common.h"
++#include "eip93-regs.h"
++
++void mtk_skcipher_handle_result(struct crypto_async_request *async, int err)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
++ struct mtk_device *mtk = ctx->mtk;
++ struct skcipher_request *req = skcipher_request_cast(async);
++ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++
++ mtk_unmap_dma(mtk, rctx, req->src, req->dst);
++ mtk_handle_result(mtk, rctx, req->iv);
++
++ skcipher_request_complete(req, err);
++}
++
++static inline bool mtk_skcipher_is_fallback(const struct crypto_tfm *tfm,
++ u32 flags)
++{
++ return (tfm->__crt_alg->cra_flags & CRYPTO_ALG_NEED_FALLBACK) &&
++ !IS_RFC3686(flags);
++}
++
++static int mtk_skcipher_send_req(struct crypto_async_request *async)
++{
++ struct skcipher_request *req = skcipher_request_cast(async);
++ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++ int err;
++
++ err = check_valid_request(rctx);
++
++ if (err) {
++ skcipher_request_complete(req, err);
++ return err;
++ }
++
++ return mtk_send_req(async, req->iv, rctx);
++}
++
++/* Crypto skcipher API functions */
++static int mtk_skcipher_cra_init(struct crypto_tfm *tfm)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
++ struct mtk_alg_template, alg.skcipher.base);
++ bool fallback = mtk_skcipher_is_fallback(tfm, tmpl->flags);
++
++ if (fallback) {
++ ctx->fallback = crypto_alloc_skcipher(
++ crypto_tfm_alg_name(tfm), 0, CRYPTO_ALG_NEED_FALLBACK);
++ if (IS_ERR(ctx->fallback))
++ return PTR_ERR(ctx->fallback);
++ }
++
++ crypto_skcipher_set_reqsize(
++ __crypto_skcipher_cast(tfm),
++ sizeof(struct mtk_cipher_reqctx) +
++ (fallback ? crypto_skcipher_reqsize(ctx->fallback) :
++ 0));
++
++ ctx->mtk = tmpl->mtk;
++
++ ctx->sa_in = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
++ if (!ctx->sa_in)
++ return -ENOMEM;
++
++ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++
++ ctx->sa_out = kzalloc(sizeof(struct saRecord_s), GFP_KERNEL);
++ if (!ctx->sa_out)
++ return -ENOMEM;
++
++ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ return 0;
++}
++
++static void mtk_skcipher_cra_exit(struct crypto_tfm *tfm)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out,
++ sizeof(struct saRecord_s), DMA_TO_DEVICE);
++ kfree(ctx->sa_in);
++ kfree(ctx->sa_out);
++
++ crypto_free_skcipher(ctx->fallback);
++}
++
++static int mtk_skcipher_setkey(struct crypto_skcipher *ctfm, const u8 *key,
++ unsigned int len)
++{
++ struct crypto_tfm *tfm = crypto_skcipher_tfm(ctfm);
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
++ struct mtk_alg_template *tmpl = container_of(tfm->__crt_alg,
++ struct mtk_alg_template, alg.skcipher.base);
++ struct saRecord_s *saRecord = ctx->sa_out;
++ u32 flags = tmpl->flags;
++ u32 nonce = 0;
++ unsigned int keylen = len;
++ int sa_size = sizeof(struct saRecord_s);
++ int err = -EINVAL;
++
++ if (!key || !keylen)
++ return err;
++
++ ctx->keylen = keylen;
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++ if (IS_RFC3686(flags)) {
++ if (len < CTR_RFC3686_NONCE_SIZE)
++ return err;
++
++ keylen = len - CTR_RFC3686_NONCE_SIZE;
++ memcpy(&nonce, key + keylen, CTR_RFC3686_NONCE_SIZE);
++ }
++#endif
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++ if (flags & MTK_ALG_DES) {
++ ctx->blksize = DES_BLOCK_SIZE;
++ err = verify_skcipher_des_key(ctfm, key);
++ }
++ if (flags & MTK_ALG_3DES) {
++ ctx->blksize = DES3_EDE_BLOCK_SIZE;
++ err = verify_skcipher_des3_key(ctfm, key);
++ }
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++ if (flags & MTK_ALG_AES) {
++ struct crypto_aes_ctx aes;
++ bool fallback = mtk_skcipher_is_fallback(tfm, flags);
++
++ if (fallback && !IS_RFC3686(flags)) {
++ err = crypto_skcipher_setkey(ctx->fallback, key,
++ keylen);
++ if (err)
++ return err;
++ }
++
++ ctx->blksize = AES_BLOCK_SIZE;
++ err = aes_expandkey(&aes, key, keylen);
++ }
++#endif
++ if (err)
++ return err;
++
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_in, sa_size,
++ DMA_TO_DEVICE);
++
++ dma_unmap_single(ctx->mtk->dev, ctx->sa_base_out, sa_size,
++ DMA_TO_DEVICE);
++
++ mtk_set_saRecord(saRecord, keylen, flags);
++
++ memcpy(saRecord->saKey, key, keylen);
++ ctx->saNonce = nonce;
++ saRecord->saNonce = nonce;
++ saRecord->saCmd0.bits.direction = 0;
++
++ memcpy(ctx->sa_in, saRecord, sa_size);
++ ctx->sa_in->saCmd0.bits.direction = 1;
++
++ ctx->sa_base_out = dma_map_single(ctx->mtk->dev, ctx->sa_out, sa_size,
++ DMA_TO_DEVICE);
++
++ ctx->sa_base_in = dma_map_single(ctx->mtk->dev, ctx->sa_in, sa_size,
++ DMA_TO_DEVICE);
++ return err;
++}
++
++static int mtk_skcipher_crypt(struct skcipher_request *req, bool encrypt)
++{
++ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++ struct crypto_async_request *async = &req->base;
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++ struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
++ bool fallback = mtk_skcipher_is_fallback(req->base.tfm, rctx->flags);
++
++ if (!req->cryptlen)
++ return 0;
++
++ /*
++ * ECB and CBC algorithms require message lengths to be
++ * multiples of block size.
++ */
++ if (IS_ECB(rctx->flags) || IS_CBC(rctx->flags))
++ if (!IS_ALIGNED(req->cryptlen,
++ crypto_skcipher_blocksize(skcipher)))
++ return -EINVAL;
++
++ if (fallback &&
++ req->cryptlen <= (AES_KEYSIZE_128 ?
++ CONFIG_CRYPTO_DEV_EIP93_AES_128_SW_MAX_LEN :
++ CONFIG_CRYPTO_DEV_EIP93_GENERIC_SW_MAX_LEN)) {
++ skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
++ skcipher_request_set_callback(&rctx->fallback_req,
++ req->base.flags,
++ req->base.complete,
++ req->base.data);
++ skcipher_request_set_crypt(&rctx->fallback_req, req->src,
++ req->dst, req->cryptlen, req->iv);
++ return encrypt ? crypto_skcipher_encrypt(&rctx->fallback_req) :
++ crypto_skcipher_decrypt(&rctx->fallback_req);
++ }
++
++ rctx->assoclen = 0;
++ rctx->textsize = req->cryptlen;
++ rctx->authsize = 0;
++ rctx->sg_src = req->src;
++ rctx->sg_dst = req->dst;
++ rctx->ivsize = crypto_skcipher_ivsize(skcipher);
++ rctx->blksize = ctx->blksize;
++ rctx->flags |= MTK_DESC_SKCIPHER;
++ if (!IS_ECB(rctx->flags))
++ rctx->flags |= MTK_DESC_DMA_IV;
++
++ return mtk_skcipher_send_req(async);
++}
++
++static int mtk_skcipher_encrypt(struct skcipher_request *req)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
++ struct mtk_alg_template, alg.skcipher.base);
++
++ rctx->flags = tmpl->flags;
++ rctx->flags |= MTK_ENCRYPT;
++ rctx->saRecord_base = ctx->sa_base_out;
++
++ return mtk_skcipher_crypt(req, true);
++}
++
++static int mtk_skcipher_decrypt(struct skcipher_request *req)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
++ struct mtk_cipher_reqctx *rctx = skcipher_request_ctx(req);
++ struct mtk_alg_template *tmpl = container_of(req->base.tfm->__crt_alg,
++ struct mtk_alg_template, alg.skcipher.base);
++
++ rctx->flags = tmpl->flags;
++ rctx->flags |= MTK_DECRYPT;
++ rctx->saRecord_base = ctx->sa_base_in;
++
++ return mtk_skcipher_crypt(req, false);
++}
++
++/* Available algorithms in this module */
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++struct mtk_alg_template mtk_alg_ecb_aes = {
++ .type = MTK_ALG_TYPE_SKCIPHER,
++ .flags = MTK_MODE_ECB | MTK_ALG_AES,
++ .alg.skcipher = {
++ .setkey = mtk_skcipher_setkey,
++ .encrypt = mtk_skcipher_encrypt,
++ .decrypt = mtk_skcipher_decrypt,
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = 0,
++ .base = {
++ .cra_name = "ecb(aes)",
++ .cra_driver_name = "ecb(aes-eip93)",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_NEED_FALLBACK |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = AES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0xf,
++ .cra_init = mtk_skcipher_cra_init,
++ .cra_exit = mtk_skcipher_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_cbc_aes = {
++ .type = MTK_ALG_TYPE_SKCIPHER,
++ .flags = MTK_MODE_CBC | MTK_ALG_AES,
++ .alg.skcipher = {
++ .setkey = mtk_skcipher_setkey,
++ .encrypt = mtk_skcipher_encrypt,
++ .decrypt = mtk_skcipher_decrypt,
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
++ .base = {
++ .cra_name = "cbc(aes)",
++ .cra_driver_name = "cbc(aes-eip93)",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_NEED_FALLBACK |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = AES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0xf,
++ .cra_init = mtk_skcipher_cra_init,
++ .cra_exit = mtk_skcipher_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_ctr_aes = {
++ .type = MTK_ALG_TYPE_SKCIPHER,
++ .flags = MTK_MODE_CTR | MTK_ALG_AES,
++ .alg.skcipher = {
++ .setkey = mtk_skcipher_setkey,
++ .encrypt = mtk_skcipher_encrypt,
++ .decrypt = mtk_skcipher_decrypt,
++ .min_keysize = AES_MIN_KEY_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE,
++ .ivsize = AES_BLOCK_SIZE,
++ .base = {
++ .cra_name = "ctr(aes)",
++ .cra_driver_name = "ctr(aes-eip93)",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_NEED_FALLBACK |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = 1,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0xf,
++ .cra_init = mtk_skcipher_cra_init,
++ .cra_exit = mtk_skcipher_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_rfc3686_aes = {
++ .type = MTK_ALG_TYPE_SKCIPHER,
++ .flags = MTK_MODE_CTR | MTK_MODE_RFC3686 | MTK_ALG_AES,
++ .alg.skcipher = {
++ .setkey = mtk_skcipher_setkey,
++ .encrypt = mtk_skcipher_encrypt,
++ .decrypt = mtk_skcipher_decrypt,
++ .min_keysize = AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
++ .max_keysize = AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE,
++ .ivsize = CTR_RFC3686_IV_SIZE,
++ .base = {
++ .cra_name = "rfc3686(ctr(aes))",
++ .cra_driver_name = "rfc3686(ctr(aes-eip93))",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_NEED_FALLBACK |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = 1,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0xf,
++ .cra_init = mtk_skcipher_cra_init,
++ .cra_exit = mtk_skcipher_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++struct mtk_alg_template mtk_alg_ecb_des = {
++ .type = MTK_ALG_TYPE_SKCIPHER,
++ .flags = MTK_MODE_ECB | MTK_ALG_DES,
++ .alg.skcipher = {
++ .setkey = mtk_skcipher_setkey,
++ .encrypt = mtk_skcipher_encrypt,
++ .decrypt = mtk_skcipher_decrypt,
++ .min_keysize = DES_KEY_SIZE,
++ .max_keysize = DES_KEY_SIZE,
++ .ivsize = 0,
++ .base = {
++ .cra_name = "ecb(des)",
++ .cra_driver_name = "ebc(des-eip93)",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_skcipher_cra_init,
++ .cra_exit = mtk_skcipher_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_cbc_des = {
++ .type = MTK_ALG_TYPE_SKCIPHER,
++ .flags = MTK_MODE_CBC | MTK_ALG_DES,
++ .alg.skcipher = {
++ .setkey = mtk_skcipher_setkey,
++ .encrypt = mtk_skcipher_encrypt,
++ .decrypt = mtk_skcipher_decrypt,
++ .min_keysize = DES_KEY_SIZE,
++ .max_keysize = DES_KEY_SIZE,
++ .ivsize = DES_BLOCK_SIZE,
++ .base = {
++ .cra_name = "cbc(des)",
++ .cra_driver_name = "cbc(des-eip93)",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_skcipher_cra_init,
++ .cra_exit = mtk_skcipher_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_ecb_des3_ede = {
++ .type = MTK_ALG_TYPE_SKCIPHER,
++ .flags = MTK_MODE_ECB | MTK_ALG_3DES,
++ .alg.skcipher = {
++ .setkey = mtk_skcipher_setkey,
++ .encrypt = mtk_skcipher_encrypt,
++ .decrypt = mtk_skcipher_decrypt,
++ .min_keysize = DES3_EDE_KEY_SIZE,
++ .max_keysize = DES3_EDE_KEY_SIZE,
++ .ivsize = 0,
++ .base = {
++ .cra_name = "ecb(des3_ede)",
++ .cra_driver_name = "ecb(des3_ede-eip93)",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_skcipher_cra_init,
++ .cra_exit = mtk_skcipher_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++
++struct mtk_alg_template mtk_alg_cbc_des3_ede = {
++ .type = MTK_ALG_TYPE_SKCIPHER,
++ .flags = MTK_MODE_CBC | MTK_ALG_3DES,
++ .alg.skcipher = {
++ .setkey = mtk_skcipher_setkey,
++ .encrypt = mtk_skcipher_encrypt,
++ .decrypt = mtk_skcipher_decrypt,
++ .min_keysize = DES3_EDE_KEY_SIZE,
++ .max_keysize = DES3_EDE_KEY_SIZE,
++ .ivsize = DES3_EDE_BLOCK_SIZE,
++ .base = {
++ .cra_name = "cbc(des3_ede)",
++ .cra_driver_name = "cbc(des3_ede-eip93)",
++ .cra_priority = MTK_CRA_PRIORITY,
++ .cra_flags = CRYPTO_ALG_ASYNC |
++ CRYPTO_ALG_KERN_DRIVER_ONLY,
++ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
++ .cra_ctxsize = sizeof(struct mtk_crypto_ctx),
++ .cra_alignmask = 0,
++ .cra_init = mtk_skcipher_cra_init,
++ .cra_exit = mtk_skcipher_cra_exit,
++ .cra_module = THIS_MODULE,
++ },
++ },
++};
++#endif
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-cipher.h
+@@ -0,0 +1,66 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_CIPHER_H_
++#define _EIP93_CIPHER_H_
++
++#include "eip93-main.h"
++
++struct mtk_crypto_ctx {
++ struct mtk_device *mtk;
++ struct saRecord_s *sa_in;
++ dma_addr_t sa_base_in;
++ struct saRecord_s *sa_out;
++ dma_addr_t sa_base_out;
++ uint32_t saNonce;
++ int blksize;
++ /* AEAD specific */
++ unsigned int authsize;
++ unsigned int assoclen_in;
++ unsigned int assoclen_out;
++ bool in_first;
++ bool out_first;
++ struct crypto_shash *shash;
++ unsigned int keylen;
++ struct crypto_skcipher *fallback;
++};
++
++struct mtk_cipher_reqctx {
++ unsigned long flags;
++ unsigned int blksize;
++ unsigned int ivsize;
++ unsigned int textsize;
++ unsigned int assoclen;
++ unsigned int authsize;
++ dma_addr_t saRecord_base;
++ struct saState_s *saState;
++ dma_addr_t saState_base;
++ uint32_t saState_idx;
++ struct eip93_descriptor_s *cdesc;
++ struct scatterlist *sg_src;
++ struct scatterlist *sg_dst;
++ int src_nents;
++ int dst_nents;
++ struct saState_s *saState_ctr;
++ dma_addr_t saState_base_ctr;
++ uint32_t saState_ctr_idx;
++ struct skcipher_request fallback_req; // keep at the end
++};
++
++int check_valid_request(struct mtk_cipher_reqctx *rctx);
++
++void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
++ struct scatterlist *reqsrc, struct scatterlist *reqdst);
++
++void mtk_skcipher_handle_result(struct crypto_async_request *async, int err);
++
++int mtk_send_req(struct crypto_async_request *async,
++ const u8 *reqiv, struct mtk_cipher_reqctx *rctx);
++
++void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
++ u8 *reqiv);
++
++#endif /* _EIP93_CIPHER_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-common.c
+@@ -0,0 +1,749 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#include <crypto/aes.h>
++#include <crypto/ctr.h>
++#include <crypto/hmac.h>
++#include <crypto/sha1.h>
++#include <crypto/sha2.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/scatterlist.h>
++
++#include "eip93-cipher.h"
++#include "eip93-common.h"
++#include "eip93-main.h"
++#include "eip93-regs.h"
++
++inline void *mtk_ring_next_wptr(struct mtk_device *mtk,
++ struct mtk_desc_ring *ring)
++{
++ void *ptr = ring->write;
++
++ if ((ring->write == ring->read - ring->offset) ||
++ (ring->read == ring->base && ring->write == ring->base_end))
++ return ERR_PTR(-ENOMEM);
++
++ if (ring->write == ring->base_end)
++ ring->write = ring->base;
++ else
++ ring->write += ring->offset;
++
++ return ptr;
++}
++
++inline void *mtk_ring_next_rptr(struct mtk_device *mtk,
++ struct mtk_desc_ring *ring)
++{
++ void *ptr = ring->read;
++
++ if (ring->write == ring->read)
++ return ERR_PTR(-ENOENT);
++
++ if (ring->read == ring->base_end)
++ ring->read = ring->base;
++ else
++ ring->read += ring->offset;
++
++ return ptr;
++}
++
++inline int mtk_put_descriptor(struct mtk_device *mtk,
++ struct eip93_descriptor_s *desc)
++{
++ struct eip93_descriptor_s *cdesc;
++ struct eip93_descriptor_s *rdesc;
++ unsigned long irqflags;
++
++ spin_lock_irqsave(&mtk->ring->write_lock, irqflags);
++
++ rdesc = mtk_ring_next_wptr(mtk, &mtk->ring->rdr);
++
++ if (IS_ERR(rdesc)) {
++ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
++ return -ENOENT;
++ }
++
++ cdesc = mtk_ring_next_wptr(mtk, &mtk->ring->cdr);
++
++ if (IS_ERR(cdesc)) {
++ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
++ return -ENOENT;
++ }
++
++ memset(rdesc, 0, sizeof(struct eip93_descriptor_s));
++ memcpy(cdesc, desc, sizeof(struct eip93_descriptor_s));
++
++ atomic_dec(&mtk->ring->free);
++ spin_unlock_irqrestore(&mtk->ring->write_lock, irqflags);
++
++ return 0;
++}
++
++inline void *mtk_get_descriptor(struct mtk_device *mtk)
++{
++ struct eip93_descriptor_s *cdesc;
++ void *ptr;
++ unsigned long irqflags;
++
++ spin_lock_irqsave(&mtk->ring->read_lock, irqflags);
++
++ cdesc = mtk_ring_next_rptr(mtk, &mtk->ring->cdr);
++
++ if (IS_ERR(cdesc)) {
++ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
++ return ERR_PTR(-ENOENT);
++ }
++
++ memset(cdesc, 0, sizeof(struct eip93_descriptor_s));
++
++ ptr = mtk_ring_next_rptr(mtk, &mtk->ring->rdr);
++ if (IS_ERR(ptr)) {
++ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
++ return ERR_PTR(-ENOENT);
++ }
++
++ atomic_inc(&mtk->ring->free);
++ spin_unlock_irqrestore(&mtk->ring->read_lock, irqflags);
++
++ return ptr;
++}
++
++inline int mtk_get_free_saState(struct mtk_device *mtk)
++{
++ struct mtk_state_pool *saState_pool;
++ int i;
++
++ for (i = 0; i < MTK_RING_SIZE; i++) {
++ saState_pool = &mtk->ring->saState_pool[i];
++ if (saState_pool->in_use == false) {
++ saState_pool->in_use = true;
++ return i;
++ }
++
++ }
++
++ return -ENOENT;
++}
++
++static inline void mtk_free_sg_copy(const int len, struct scatterlist **sg)
++{
++ if (!*sg || !len)
++ return;
++
++ free_pages((unsigned long)sg_virt(*sg), get_order(len));
++ kfree(*sg);
++ *sg = NULL;
++}
++
++static inline int mtk_make_sg_copy(struct scatterlist *src,
++ struct scatterlist **dst,
++ const uint32_t len, const bool copy)
++{
++ void *pages;
++
++ *dst = kmalloc(sizeof(**dst), GFP_KERNEL);
++ if (!*dst)
++ return -ENOMEM;
++
++
++ pages = (void *)__get_free_pages(GFP_KERNEL | GFP_DMA,
++ get_order(len));
++
++ if (!pages) {
++ kfree(*dst);
++ *dst = NULL;
++ return -ENOMEM;
++ }
++
++ sg_init_table(*dst, 1);
++ sg_set_buf(*dst, pages, len);
++
++ /* copy only as requested */
++ if (copy)
++ sg_copy_to_buffer(src, sg_nents(src), pages, len);
++
++ return 0;
++}
++
++static inline bool mtk_is_sg_aligned(struct scatterlist *sg, u32 len,
++ const int blksize)
++{
++ int nents;
++
++ for (nents = 0; sg; sg = sg_next(sg), ++nents) {
++ if (!IS_ALIGNED(sg->offset, 4))
++ return false;
++
++ if (len <= sg->length) {
++ if (!IS_ALIGNED(len, blksize))
++ return false;
++
++ return true;
++ }
++
++ if (!IS_ALIGNED(sg->length, blksize))
++ return false;
++
++ len -= sg->length;
++ }
++ return false;
++}
++
++int check_valid_request(struct mtk_cipher_reqctx *rctx)
++{
++ struct scatterlist *src = rctx->sg_src;
++ struct scatterlist *dst = rctx->sg_dst;
++ uint32_t src_nents, dst_nents;
++ u32 textsize = rctx->textsize;
++ u32 authsize = rctx->authsize;
++ u32 blksize = rctx->blksize;
++ u32 totlen_src = rctx->assoclen + rctx->textsize;
++ u32 totlen_dst = rctx->assoclen + rctx->textsize;
++ u32 copy_len;
++ bool src_align, dst_align;
++ int err = -EINVAL;
++
++ if (!IS_CTR(rctx->flags)) {
++ if (!IS_ALIGNED(textsize, blksize))
++ return err;
++ }
++
++ if (authsize) {
++ if (IS_ENCRYPT(rctx->flags))
++ totlen_dst += authsize;
++ else
++ totlen_src += authsize;
++ }
++
++ src_nents = sg_nents_for_len(src, totlen_src);
++ dst_nents = sg_nents_for_len(dst, totlen_dst);
++
++ if (src == dst) {
++ src_nents = max(src_nents, dst_nents);
++ dst_nents = src_nents;
++ if (unlikely((totlen_src || totlen_dst) && (src_nents <= 0)))
++ return err;
++
++ } else {
++ if (unlikely(totlen_src && (src_nents <= 0)))
++ return err;
++
++ if (unlikely(totlen_dst && (dst_nents <= 0)))
++ return err;
++ }
++
++ if (authsize) {
++ if (dst_nents == 1 && src_nents == 1) {
++ src_align = mtk_is_sg_aligned(src, totlen_src, blksize);
++ if (src == dst)
++ dst_align = src_align;
++ else
++ dst_align = mtk_is_sg_aligned(dst,
++ totlen_dst, blksize);
++ } else {
++ src_align = false;
++ dst_align = false;
++ }
++ } else {
++ src_align = mtk_is_sg_aligned(src, totlen_src, blksize);
++ if (src == dst)
++ dst_align = src_align;
++ else
++ dst_align = mtk_is_sg_aligned(dst, totlen_dst, blksize);
++ }
++
++ copy_len = max(totlen_src, totlen_dst);
++ if (!src_align) {
++ err = mtk_make_sg_copy(src, &rctx->sg_src, copy_len, true);
++ if (err)
++ return err;
++ }
++
++ if (!dst_align) {
++ err = mtk_make_sg_copy(dst, &rctx->sg_dst, copy_len, false);
++ if (err)
++ return err;
++ }
++
++ rctx->src_nents = sg_nents_for_len(rctx->sg_src, totlen_src);
++ rctx->dst_nents = sg_nents_for_len(rctx->sg_dst, totlen_dst);
++
++ return 0;
++}
++/*
++ * Set saRecord function:
++ * Even saRecord is set to "0", keep " = 0" for readability.
++ */
++void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen,
++ const u32 flags)
++{
++ saRecord->saCmd0.bits.ivSource = 2;
++ if (IS_ECB(flags))
++ saRecord->saCmd0.bits.saveIv = 0;
++ else
++ saRecord->saCmd0.bits.saveIv = 1;
++
++ saRecord->saCmd0.bits.opGroup = 0;
++ saRecord->saCmd0.bits.opCode = 0;
++
++ switch ((flags & MTK_ALG_MASK)) {
++ case MTK_ALG_AES:
++ saRecord->saCmd0.bits.cipher = 3;
++ saRecord->saCmd1.bits.aesKeyLen = keylen >> 3;
++ break;
++ case MTK_ALG_3DES:
++ saRecord->saCmd0.bits.cipher = 1;
++ break;
++ case MTK_ALG_DES:
++ saRecord->saCmd0.bits.cipher = 0;
++ break;
++ default:
++ saRecord->saCmd0.bits.cipher = 15;
++ }
++
++ switch ((flags & MTK_HASH_MASK)) {
++ case MTK_HASH_SHA256:
++ saRecord->saCmd0.bits.hash = 3;
++ break;
++ case MTK_HASH_SHA224:
++ saRecord->saCmd0.bits.hash = 2;
++ break;
++ case MTK_HASH_SHA1:
++ saRecord->saCmd0.bits.hash = 1;
++ break;
++ case MTK_HASH_MD5:
++ saRecord->saCmd0.bits.hash = 0;
++ break;
++ default:
++ saRecord->saCmd0.bits.hash = 15;
++ }
++
++ saRecord->saCmd0.bits.hdrProc = 0;
++ saRecord->saCmd0.bits.padType = 3;
++ saRecord->saCmd0.bits.extPad = 0;
++ saRecord->saCmd0.bits.scPad = 0;
++
++ switch ((flags & MTK_MODE_MASK)) {
++ case MTK_MODE_CBC:
++ saRecord->saCmd1.bits.cipherMode = 1;
++ break;
++ case MTK_MODE_CTR:
++ saRecord->saCmd1.bits.cipherMode = 2;
++ break;
++ case MTK_MODE_ECB:
++ saRecord->saCmd1.bits.cipherMode = 0;
++ break;
++ }
++
++ saRecord->saCmd1.bits.byteOffset = 0;
++ saRecord->saCmd1.bits.hashCryptOffset = 0;
++ saRecord->saCmd0.bits.digestLength = 0;
++ saRecord->saCmd1.bits.copyPayload = 0;
++
++ if (IS_HMAC(flags)) {
++ saRecord->saCmd1.bits.hmac = 1;
++ saRecord->saCmd1.bits.copyDigest = 1;
++ saRecord->saCmd1.bits.copyHeader = 1;
++ } else {
++ saRecord->saCmd1.bits.hmac = 0;
++ saRecord->saCmd1.bits.copyDigest = 0;
++ saRecord->saCmd1.bits.copyHeader = 0;
++ }
++
++ saRecord->saCmd1.bits.seqNumCheck = 0;
++ saRecord->saSpi = 0x0;
++ saRecord->saSeqNumMask[0] = 0xFFFFFFFF;
++ saRecord->saSeqNumMask[1] = 0x0;
++}
++
++/*
++ * Poor mans Scatter/gather function:
++ * Create a Descriptor for every segment to avoid copying buffers.
++ * For performance better to wait for hardware to perform multiple DMA
++ *
++ */
++static inline int mtk_scatter_combine(struct mtk_device *mtk,
++ struct mtk_cipher_reqctx *rctx,
++ u32 datalen, u32 split, int offsetin)
++{
++ struct eip93_descriptor_s *cdesc = rctx->cdesc;
++ struct scatterlist *sgsrc = rctx->sg_src;
++ struct scatterlist *sgdst = rctx->sg_dst;
++ unsigned int remainin = sg_dma_len(sgsrc);
++ unsigned int remainout = sg_dma_len(sgdst);
++ dma_addr_t saddr = sg_dma_address(sgsrc);
++ dma_addr_t daddr = sg_dma_address(sgdst);
++ dma_addr_t stateAddr;
++ u32 srcAddr, dstAddr, len, n;
++ bool nextin = false;
++ bool nextout = false;
++ int offsetout = 0;
++ int ndesc_cdr = 0, err;
++
++ if (IS_ECB(rctx->flags))
++ rctx->saState_base = 0;
++
++ if (split < datalen) {
++ stateAddr = rctx->saState_base_ctr;
++ n = split;
++ } else {
++ stateAddr = rctx->saState_base;
++ n = datalen;
++ }
++
++ do {
++ if (nextin) {
++ sgsrc = sg_next(sgsrc);
++ remainin = sg_dma_len(sgsrc);
++ if (remainin == 0)
++ continue;
++
++ saddr = sg_dma_address(sgsrc);
++ offsetin = 0;
++ nextin = false;
++ }
++
++ if (nextout) {
++ sgdst = sg_next(sgdst);
++ remainout = sg_dma_len(sgdst);
++ if (remainout == 0)
++ continue;
++
++ daddr = sg_dma_address(sgdst);
++ offsetout = 0;
++ nextout = false;
++ }
++ srcAddr = saddr + offsetin;
++ dstAddr = daddr + offsetout;
++
++ if (remainin == remainout) {
++ len = remainin;
++ if (len > n) {
++ len = n;
++ remainin -= n;
++ remainout -= n;
++ offsetin += n;
++ offsetout += n;
++ } else {
++ nextin = true;
++ nextout = true;
++ }
++ } else if (remainin < remainout) {
++ len = remainin;
++ if (len > n) {
++ len = n;
++ remainin -= n;
++ remainout -= n;
++ offsetin += n;
++ offsetout += n;
++ } else {
++ offsetout += len;
++ remainout -= len;
++ nextin = true;
++ }
++ } else {
++ len = remainout;
++ if (len > n) {
++ len = n;
++ remainin -= n;
++ remainout -= n;
++ offsetin += n;
++ offsetout += n;
++ } else {
++ offsetin += len;
++ remainin -= len;
++ nextout = true;
++ }
++ }
++ n -= len;
++
++ cdesc->srcAddr = srcAddr;
++ cdesc->dstAddr = dstAddr;
++ cdesc->stateAddr = stateAddr;
++ cdesc->peLength.bits.peReady = 0;
++ cdesc->peLength.bits.byPass = 0;
++ cdesc->peLength.bits.length = len;
++ cdesc->peLength.bits.hostReady = 1;
++
++ if (n == 0) {
++ n = datalen - split;
++ split = datalen;
++ stateAddr = rctx->saState_base;
++ }
++
++ if (n == 0)
++ cdesc->userId |= MTK_DESC_LAST;
++
++ /* Loop - Delay - No need to rollback
++ * Maybe refine by slowing down at MTK_RING_BUSY
++ */
++again:
++ err = mtk_put_descriptor(mtk, cdesc);
++ if (err) {
++ udelay(500);
++ goto again;
++ }
++ /* Writing new descriptor count starts DMA action */
++ writel(1, mtk->base + EIP93_REG_PE_CD_COUNT);
++
++ ndesc_cdr++;
++ } while (n);
++
++ return -EINPROGRESS;
++}
++
++int mtk_send_req(struct crypto_async_request *async,
++ const u8 *reqiv, struct mtk_cipher_reqctx *rctx)
++{
++ struct mtk_crypto_ctx *ctx = crypto_tfm_ctx(async->tfm);
++ struct mtk_device *mtk = ctx->mtk;
++ struct scatterlist *src = rctx->sg_src;
++ struct scatterlist *dst = rctx->sg_dst;
++ struct saState_s *saState;
++ struct mtk_state_pool *saState_pool;
++ struct eip93_descriptor_s cdesc;
++ u32 flags = rctx->flags;
++ int idx;
++ int offsetin = 0, err = -ENOMEM;
++ u32 datalen = rctx->assoclen + rctx->textsize;
++ u32 split = datalen;
++ u32 start, end, ctr, blocks;
++ u32 iv[AES_BLOCK_SIZE / sizeof(u32)];
++
++ rctx->saState_ctr = NULL;
++ rctx->saState = NULL;
++
++ if (IS_ECB(flags))
++ goto skip_iv;
++
++ memcpy(iv, reqiv, rctx->ivsize);
++
++ if (!IS_ALIGNED((u32)reqiv, rctx->ivsize) || IS_RFC3686(flags)) {
++ rctx->flags &= ~MTK_DESC_DMA_IV;
++ flags = rctx->flags;
++ }
++
++ if (IS_DMA_IV(flags)) {
++ rctx->saState = (void *)reqiv;
++ } else {
++ idx = mtk_get_free_saState(mtk);
++ if (idx < 0)
++ goto send_err;
++ saState_pool = &mtk->ring->saState_pool[idx];
++ rctx->saState_idx = idx;
++ rctx->saState = saState_pool->base;
++ rctx->saState_base = saState_pool->base_dma;
++ memcpy(rctx->saState->stateIv, iv, rctx->ivsize);
++ }
++
++ saState = rctx->saState;
++
++ if (IS_RFC3686(flags)) {
++ saState->stateIv[0] = ctx->saNonce;
++ saState->stateIv[1] = iv[0];
++ saState->stateIv[2] = iv[1];
++ saState->stateIv[3] = cpu_to_be32(1);
++ } else if (!IS_HMAC(flags) && IS_CTR(flags)) {
++ /* Compute data length. */
++ blocks = DIV_ROUND_UP(rctx->textsize, AES_BLOCK_SIZE);
++ ctr = be32_to_cpu(iv[3]);
++ /* Check 32bit counter overflow. */
++ start = ctr;
++ end = start + blocks - 1;
++ if (end < start) {
++ split = AES_BLOCK_SIZE * -start;
++ /*
++ * Increment the counter manually to cope with
++ * the hardware counter overflow.
++ */
++ iv[3] = 0xffffffff;
++ crypto_inc((u8 *)iv, AES_BLOCK_SIZE);
++ idx = mtk_get_free_saState(mtk);
++ if (idx < 0)
++ goto free_state;
++ saState_pool = &mtk->ring->saState_pool[idx];
++ rctx->saState_ctr_idx = idx;
++ rctx->saState_ctr = saState_pool->base;
++ rctx->saState_base_ctr = saState_pool->base_dma;
++
++ memcpy(rctx->saState_ctr->stateIv, reqiv, rctx->ivsize);
++ memcpy(saState->stateIv, iv, rctx->ivsize);
++ }
++ }
++
++ if (IS_DMA_IV(flags)) {
++ rctx->saState_base = dma_map_single(mtk->dev, (void *)reqiv,
++ rctx->ivsize, DMA_TO_DEVICE);
++ if (dma_mapping_error(mtk->dev, rctx->saState_base))
++ goto free_state;
++ }
++skip_iv:
++ cdesc.peCrtlStat.bits.hostReady = 1;
++ cdesc.peCrtlStat.bits.prngMode = 0;
++ cdesc.peCrtlStat.bits.hashFinal = 0;
++ cdesc.peCrtlStat.bits.padCrtlStat = 0;
++ cdesc.peCrtlStat.bits.peReady = 0;
++ cdesc.saAddr = rctx->saRecord_base;
++ cdesc.arc4Addr = (uint32_t)async;
++ cdesc.userId = flags;
++ rctx->cdesc = &cdesc;
++
++ /* map DMA_BIDIRECTIONAL to invalidate cache on destination
++ * implies __dma_cache_wback_inv
++ */
++ dma_map_sg(mtk->dev, dst, rctx->dst_nents, DMA_BIDIRECTIONAL);
++ if (src != dst)
++ dma_map_sg(mtk->dev, src, rctx->src_nents, DMA_TO_DEVICE);
++
++ err = mtk_scatter_combine(mtk, rctx, datalen, split, offsetin);
++
++ return err;
++
++free_state:
++ if (rctx->saState) {
++ saState_pool = &mtk->ring->saState_pool[rctx->saState_idx];
++ saState_pool->in_use = false;
++ }
++
++ if (rctx->saState_ctr) {
++ saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx];
++ saState_pool->in_use = false;
++ }
++send_err:
++ return err;
++}
++
++void mtk_unmap_dma(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
++ struct scatterlist *reqsrc, struct scatterlist *reqdst)
++{
++ u32 len = rctx->assoclen + rctx->textsize;
++ u32 authsize = rctx->authsize;
++ u32 flags = rctx->flags;
++ u32 *otag;
++ int i;
++
++ if (rctx->sg_src == rctx->sg_dst) {
++ dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents,
++ DMA_BIDIRECTIONAL);
++ goto process_tag;
++ }
++
++ dma_unmap_sg(mtk->dev, rctx->sg_src, rctx->src_nents,
++ DMA_TO_DEVICE);
++
++ if (rctx->sg_src != reqsrc)
++ mtk_free_sg_copy(len + rctx->authsize, &rctx->sg_src);
++
++ dma_unmap_sg(mtk->dev, rctx->sg_dst, rctx->dst_nents,
++ DMA_BIDIRECTIONAL);
++
++ /* SHA tags need conversion from net-to-host */
++process_tag:
++ if (IS_DECRYPT(flags))
++ authsize = 0;
++
++ if (authsize) {
++ if (!IS_HASH_MD5(flags)) {
++ otag = sg_virt(rctx->sg_dst) + len;
++ for (i = 0; i < (authsize / 4); i++)
++ otag[i] = ntohl(otag[i]);
++ }
++ }
++
++ if (rctx->sg_dst != reqdst) {
++ sg_copy_from_buffer(reqdst, sg_nents(reqdst),
++ sg_virt(rctx->sg_dst), len + authsize);
++ mtk_free_sg_copy(len + rctx->authsize, &rctx->sg_dst);
++ }
++}
++
++void mtk_handle_result(struct mtk_device *mtk, struct mtk_cipher_reqctx *rctx,
++ u8 *reqiv)
++{
++ struct mtk_state_pool *saState_pool;
++
++ if (IS_DMA_IV(rctx->flags))
++ dma_unmap_single(mtk->dev, rctx->saState_base, rctx->ivsize,
++ DMA_TO_DEVICE);
++
++ if (!IS_ECB(rctx->flags))
++ memcpy(reqiv, rctx->saState->stateIv, rctx->ivsize);
++
++ if ((rctx->saState) && !(IS_DMA_IV(rctx->flags))) {
++ saState_pool = &mtk->ring->saState_pool[rctx->saState_idx];
++ saState_pool->in_use = false;
++ }
++
++ if (rctx->saState_ctr) {
++ saState_pool = &mtk->ring->saState_pool[rctx->saState_ctr_idx];
++ saState_pool->in_use = false;
++ }
++}
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
++/* basically this is set hmac - key */
++int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa,
++ const u8 *authkey, unsigned int authkeylen)
++{
++ int bs = crypto_shash_blocksize(cshash);
++ int ds = crypto_shash_digestsize(cshash);
++ int ss = crypto_shash_statesize(cshash);
++ u8 *ipad, *opad;
++ unsigned int i, err;
++
++ SHASH_DESC_ON_STACK(shash, cshash);
++
++ shash->tfm = cshash;
++
++ /* auth key
++ *
++ * EIP93 can only authenticate with hash of the key
++ * do software shash until EIP93 hash function complete.
++ */
++ ipad = kcalloc(2, SHA256_BLOCK_SIZE + ss, GFP_KERNEL);
++ if (!ipad)
++ return -ENOMEM;
++
++ opad = ipad + SHA256_BLOCK_SIZE + ss;
++
++ if (authkeylen > bs) {
++ err = crypto_shash_digest(shash, authkey,
++ authkeylen, ipad);
++ if (err)
++ return err;
++
++ authkeylen = ds;
++ } else
++ memcpy(ipad, authkey, authkeylen);
++
++ memset(ipad + authkeylen, 0, bs - authkeylen);
++ memcpy(opad, ipad, bs);
++
++ for (i = 0; i < bs; i++) {
++ ipad[i] ^= HMAC_IPAD_VALUE;
++ opad[i] ^= HMAC_OPAD_VALUE;
++ }
++
++ err = crypto_shash_init(shash) ?:
++ crypto_shash_update(shash, ipad, bs) ?:
++ crypto_shash_export(shash, ipad) ?:
++ crypto_shash_init(shash) ?:
++ crypto_shash_update(shash, opad, bs) ?:
++ crypto_shash_export(shash, opad);
++
++ if (err)
++ return err;
++
++ /* add auth key */
++ memcpy(&sa->saIDigest, ipad, SHA256_DIGEST_SIZE);
++ memcpy(&sa->saODigest, opad, SHA256_DIGEST_SIZE);
++
++ kfree(ipad);
++ return 0;
++}
++#endif
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-common.h
+@@ -0,0 +1,28 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#ifndef _EIP93_COMMON_H_
++#define _EIP93_COMMON_H_
++
++#include "eip93-main.h"
++
++inline int mtk_put_descriptor(struct mtk_device *mtk,
++ struct eip93_descriptor_s *desc);
++
++inline void *mtk_get_descriptor(struct mtk_device *mtk);
++
++inline int mtk_get_free_saState(struct mtk_device *mtk);
++
++void mtk_set_saRecord(struct saRecord_s *saRecord, const unsigned int keylen,
++ const u32 flags);
++
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
++int mtk_authenc_setkey(struct crypto_shash *cshash, struct saRecord_s *sa,
++ const u8 *authkey, unsigned int authkeylen);
++#endif
++
++#endif /* _EIP93_COMMON_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-des.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_DES_H_
++#define _EIP93_DES_H_
++
++extern struct mtk_alg_template mtk_alg_ecb_des;
++extern struct mtk_alg_template mtk_alg_cbc_des;
++extern struct mtk_alg_template mtk_alg_ecb_des3_ede;
++extern struct mtk_alg_template mtk_alg_cbc_des3_ede;
++
++#endif /* _EIP93_DES_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-main.c
+@@ -0,0 +1,463 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++
++#include <linux/atomic.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/dma-mapping.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++
++#include "eip93-main.h"
++#include "eip93-regs.h"
++#include "eip93-common.h"
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER)
++#include "eip93-cipher.h"
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++#include "eip93-aes.h"
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++#include "eip93-des.h"
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
++#include "eip93-aead.h"
++#endif
++
++static struct mtk_alg_template *mtk_algs[] = {
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++ &mtk_alg_ecb_des,
++ &mtk_alg_cbc_des,
++ &mtk_alg_ecb_des3_ede,
++ &mtk_alg_cbc_des3_ede,
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++ &mtk_alg_ecb_aes,
++ &mtk_alg_cbc_aes,
++ &mtk_alg_ctr_aes,
++ &mtk_alg_rfc3686_aes,
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++ &mtk_alg_authenc_hmac_md5_cbc_des,
++ &mtk_alg_authenc_hmac_sha1_cbc_des,
++ &mtk_alg_authenc_hmac_sha224_cbc_des,
++ &mtk_alg_authenc_hmac_sha256_cbc_des,
++ &mtk_alg_authenc_hmac_md5_cbc_des3_ede,
++ &mtk_alg_authenc_hmac_sha1_cbc_des3_ede,
++ &mtk_alg_authenc_hmac_sha224_cbc_des3_ede,
++ &mtk_alg_authenc_hmac_sha256_cbc_des3_ede,
++#endif
++ &mtk_alg_authenc_hmac_md5_cbc_aes,
++ &mtk_alg_authenc_hmac_sha1_cbc_aes,
++ &mtk_alg_authenc_hmac_sha224_cbc_aes,
++ &mtk_alg_authenc_hmac_sha256_cbc_aes,
++ &mtk_alg_authenc_hmac_md5_rfc3686_aes,
++ &mtk_alg_authenc_hmac_sha1_rfc3686_aes,
++ &mtk_alg_authenc_hmac_sha224_rfc3686_aes,
++ &mtk_alg_authenc_hmac_sha256_rfc3686_aes,
++#endif
++};
++
++inline void mtk_irq_disable(struct mtk_device *mtk, u32 mask)
++{
++ __raw_writel(mask, mtk->base + EIP93_REG_MASK_DISABLE);
++}
++
++inline void mtk_irq_enable(struct mtk_device *mtk, u32 mask)
++{
++ __raw_writel(mask, mtk->base + EIP93_REG_MASK_ENABLE);
++}
++
++inline void mtk_irq_clear(struct mtk_device *mtk, u32 mask)
++{
++ __raw_writel(mask, mtk->base + EIP93_REG_INT_CLR);
++}
++
++static void mtk_unregister_algs(unsigned int i)
++{
++ unsigned int j;
++
++ for (j = 0; j < i; j++) {
++ switch (mtk_algs[j]->type) {
++ case MTK_ALG_TYPE_SKCIPHER:
++ crypto_unregister_skcipher(&mtk_algs[j]->alg.skcipher);
++ break;
++ case MTK_ALG_TYPE_AEAD:
++ crypto_unregister_aead(&mtk_algs[j]->alg.aead);
++ break;
++ }
++ }
++}
++
++static int mtk_register_algs(struct mtk_device *mtk)
++{
++ unsigned int i;
++ int err = 0;
++
++ for (i = 0; i < ARRAY_SIZE(mtk_algs); i++) {
++ mtk_algs[i]->mtk = mtk;
++
++ switch (mtk_algs[i]->type) {
++ case MTK_ALG_TYPE_SKCIPHER:
++ err = crypto_register_skcipher(&mtk_algs[i]->alg.skcipher);
++ break;
++ case MTK_ALG_TYPE_AEAD:
++ err = crypto_register_aead(&mtk_algs[i]->alg.aead);
++ break;
++ }
++ if (err)
++ goto fail;
++ }
++
++ return 0;
++
++fail:
++ mtk_unregister_algs(i);
++
++ return err;
++}
++
++static void mtk_handle_result_descriptor(struct mtk_device *mtk)
++{
++ struct crypto_async_request *async;
++ struct eip93_descriptor_s *rdesc;
++ bool last_entry;
++ u32 flags;
++ int handled, ready, err;
++ union peCrtlStat_w done1;
++ union peLength_w done2;
++
++get_more:
++ handled = 0;
++
++ ready = readl(mtk->base + EIP93_REG_PE_RD_COUNT) & GENMASK(10, 0);
++
++ if (!ready) {
++ mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++ mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++ return;
++ }
++
++ last_entry = false;
++
++ while (ready) {
++ rdesc = mtk_get_descriptor(mtk);
++ if (IS_ERR(rdesc)) {
++ dev_err(mtk->dev, "Ndesc: %d nreq: %d\n",
++ handled, ready);
++ err = -EIO;
++ break;
++ }
++ /* make sure DMA is finished writing */
++ do {
++ done1.word = READ_ONCE(rdesc->peCrtlStat.word);
++ done2.word = READ_ONCE(rdesc->peLength.word);
++ } while ((!done1.bits.peReady) || (!done2.bits.peReady));
++
++ err = rdesc->peCrtlStat.bits.errStatus;
++
++ flags = rdesc->userId;
++ async = (struct crypto_async_request *)rdesc->arc4Addr;
++
++ writel(1, mtk->base + EIP93_REG_PE_RD_COUNT);
++ mtk_irq_clear(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++
++ handled++;
++ ready--;
++
++ if (flags & MTK_DESC_LAST) {
++ last_entry = true;
++ break;
++ }
++ }
++
++ if (!last_entry)
++ goto get_more;
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_SKCIPHER)
++ if (flags & MTK_DESC_SKCIPHER)
++ mtk_skcipher_handle_result(async, err);
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AEAD)
++ if (flags & MTK_DESC_AEAD)
++ mtk_aead_handle_result(async, err);
++#endif
++ goto get_more;
++}
++
++static void mtk_done_task(unsigned long data)
++{
++ struct mtk_device *mtk = (struct mtk_device *)data;
++
++ mtk_handle_result_descriptor(mtk);
++}
++
++static irqreturn_t mtk_irq_handler(int irq, void *dev_id)
++{
++ struct mtk_device *mtk = (struct mtk_device *)dev_id;
++ u32 irq_status;
++
++ irq_status = readl(mtk->base + EIP93_REG_INT_MASK_STAT);
++
++ if (irq_status & EIP93_INT_PE_RDRTHRESH_REQ) {
++ mtk_irq_disable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++ tasklet_schedule(&mtk->ring->done_task);
++ return IRQ_HANDLED;
++ }
++
++ mtk_irq_clear(mtk, irq_status);
++ if (irq_status)
++ mtk_irq_disable(mtk, irq_status);
++
++ return IRQ_NONE;
++}
++
++static void mtk_initialize(struct mtk_device *mtk)
++{
++ union peConfig_w peConfig;
++ union peEndianCfg_w peEndianCfg;
++ union peIntCfg_w peIntCfg;
++ union peClockCfg_w peClockCfg;
++ union peBufThresh_w peBufThresh;
++ union peRingThresh_w peRingThresh;
++
++ /* Reset Engine and setup Mode */
++ peConfig.word = 0;
++ peConfig.bits.resetPE = 1;
++ peConfig.bits.resetRing = 1;
++ peConfig.bits.peMode = 3;
++ peConfig.bits.enCDRupdate = 1;
++
++ writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG);
++
++ udelay(10);
++
++ peConfig.bits.resetPE = 0;
++ peConfig.bits.resetRing = 0;
++
++ writel(peConfig.word, mtk->base + EIP93_REG_PE_CONFIG);
++
++ /* Initialize the BYTE_ORDER_CFG register */
++ peEndianCfg.word = 0;
++ writel(peEndianCfg.word, mtk->base + EIP93_REG_PE_ENDIAN_CONFIG);
++
++ /* Initialize the INT_CFG register */
++ peIntCfg.word = 0;
++ writel(peIntCfg.word, mtk->base + EIP93_REG_INT_CFG);
++
++ /* Config Clocks */
++ peClockCfg.word = 0;
++ peClockCfg.bits.enPEclk = 1;
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_DES)
++ peClockCfg.bits.enDESclk = 1;
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_AES)
++ peClockCfg.bits.enAESclk = 1;
++#endif
++#if IS_ENABLED(CONFIG_CRYPTO_DEV_EIP93_HMAC)
++ peClockCfg.bits.enHASHclk = 1;
++#endif
++ writel(peClockCfg.word, mtk->base + EIP93_REG_PE_CLOCK_CTRL);
++
++ /* Config DMA thresholds */
++ peBufThresh.word = 0;
++ peBufThresh.bits.inputBuffer = 128;
++ peBufThresh.bits.outputBuffer = 128;
++
++ writel(peBufThresh.word, mtk->base + EIP93_REG_PE_BUF_THRESH);
++
++ /* Clear/ack all interrupts before disable all */
++ mtk_irq_clear(mtk, 0xFFFFFFFF);
++ mtk_irq_disable(mtk, 0xFFFFFFFF);
++
++ /* Config Ring Threshold */
++ peRingThresh.word = 0;
++ peRingThresh.bits.CDRThresh = MTK_RING_SIZE - MTK_RING_BUSY;
++ peRingThresh.bits.RDRThresh = 0;
++ peRingThresh.bits.RDTimeout = 5;
++ peRingThresh.bits.enTimeout = 1;
++
++ writel(peRingThresh.word, mtk->base + EIP93_REG_PE_RING_THRESH);
++}
++
++static void mtk_desc_free(struct mtk_device *mtk)
++{
++ writel(0, mtk->base + EIP93_REG_PE_RING_CONFIG);
++ writel(0, mtk->base + EIP93_REG_PE_CDR_BASE);
++ writel(0, mtk->base + EIP93_REG_PE_RDR_BASE);
++}
++
++static int mtk_set_ring(struct mtk_device *mtk, struct mtk_desc_ring *ring,
++ int Offset)
++{
++ ring->offset = Offset;
++ ring->base = dmam_alloc_coherent(mtk->dev, Offset * MTK_RING_SIZE,
++ &ring->base_dma, GFP_KERNEL);
++ if (!ring->base)
++ return -ENOMEM;
++
++ ring->write = ring->base;
++ ring->base_end = ring->base + Offset * (MTK_RING_SIZE - 1);
++ ring->read = ring->base;
++
++ return 0;
++}
++
++static int mtk_desc_init(struct mtk_device *mtk)
++{
++ struct mtk_state_pool *saState_pool;
++ struct mtk_desc_ring *cdr = &mtk->ring->cdr;
++ struct mtk_desc_ring *rdr = &mtk->ring->rdr;
++ union peRingCfg_w peRingCfg;
++ int RingOffset, err, i;
++
++ RingOffset = sizeof(struct eip93_descriptor_s);
++
++ err = mtk_set_ring(mtk, cdr, RingOffset);
++ if (err)
++ return err;
++
++ err = mtk_set_ring(mtk, rdr, RingOffset);
++ if (err)
++ return err;
++
++ writel((u32)cdr->base_dma, mtk->base + EIP93_REG_PE_CDR_BASE);
++ writel((u32)rdr->base_dma, mtk->base + EIP93_REG_PE_RDR_BASE);
++
++ peRingCfg.word = 0;
++ peRingCfg.bits.ringSize = MTK_RING_SIZE - 1;
++ peRingCfg.bits.ringOffset = RingOffset / 4;
++
++ writel(peRingCfg.word, mtk->base + EIP93_REG_PE_RING_CONFIG);
++
++ atomic_set(&mtk->ring->free, MTK_RING_SIZE - 1);
++ /* Create State record DMA pool */
++ RingOffset = sizeof(struct saState_s);
++ mtk->ring->saState = dmam_alloc_coherent(mtk->dev,
++ RingOffset * MTK_RING_SIZE,
++ &mtk->ring->saState_dma, GFP_KERNEL);
++ if (!mtk->ring->saState)
++ return -ENOMEM;
++
++ mtk->ring->saState_pool = devm_kcalloc(mtk->dev, 1,
++ sizeof(struct mtk_state_pool) * MTK_RING_SIZE,
++ GFP_KERNEL);
++
++ for (i = 0; i < MTK_RING_SIZE; i++) {
++ saState_pool = &mtk->ring->saState_pool[i];
++ saState_pool->base = mtk->ring->saState + (i * RingOffset);
++ saState_pool->base_dma = mtk->ring->saState_dma + (i * RingOffset);
++ saState_pool->in_use = false;
++ }
++
++ return 0;
++}
++
++static void mtk_cleanup(struct mtk_device *mtk)
++{
++ tasklet_kill(&mtk->ring->done_task);
++
++ /* Clear/ack all interrupts before disable all */
++ mtk_irq_clear(mtk, 0xFFFFFFFF);
++ mtk_irq_disable(mtk, 0xFFFFFFFF);
++
++ writel(0, mtk->base + EIP93_REG_PE_CLOCK_CTRL);
++
++ mtk_desc_free(mtk);
++}
++
++static int mtk_crypto_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct mtk_device *mtk;
++ int err;
++
++ mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
++ if (!mtk)
++ return -ENOMEM;
++
++ mtk->dev = dev;
++ platform_set_drvdata(pdev, mtk);
++
++ mtk->base = devm_platform_ioremap_resource(pdev, 0);
++
++ if (IS_ERR(mtk->base))
++ return PTR_ERR(mtk->base);
++
++ mtk->irq = platform_get_irq(pdev, 0);
++
++ if (mtk->irq < 0)
++ return mtk->irq;
++
++ err = devm_request_threaded_irq(mtk->dev, mtk->irq, mtk_irq_handler,
++ NULL, IRQF_ONESHOT,
++ dev_name(mtk->dev), mtk);
++
++ mtk->ring = devm_kcalloc(mtk->dev, 1, sizeof(*mtk->ring), GFP_KERNEL);
++
++ if (!mtk->ring)
++ return -ENOMEM;
++
++ err = mtk_desc_init(mtk);
++ if (err)
++ return err;
++
++ tasklet_init(&mtk->ring->done_task, mtk_done_task, (unsigned long)mtk);
++
++ spin_lock_init(&mtk->ring->read_lock);
++ spin_lock_init(&mtk->ring->write_lock);
++
++ mtk_initialize(mtk);
++
++ /* Init. finished, enable RDR interupt */
++ mtk_irq_enable(mtk, EIP93_INT_PE_RDRTHRESH_REQ);
++
++ err = mtk_register_algs(mtk);
++ if (err) {
++ mtk_cleanup(mtk);
++ return err;
++ }
++
++ dev_info(mtk->dev, "EIP93 Crypto Engine Initialized.");
++
++ return 0;
++}
++
++static void mtk_crypto_remove(struct platform_device *pdev)
++{
++ struct mtk_device *mtk = platform_get_drvdata(pdev);
++
++ mtk_unregister_algs(ARRAY_SIZE(mtk_algs));
++ mtk_cleanup(mtk);
++ dev_info(mtk->dev, "EIP93 removed.\n");
++}
++
++#if defined(CONFIG_OF)
++static const struct of_device_id mtk_crypto_of_match[] = {
++ { .compatible = "mediatek,mtk-eip93", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, mtk_crypto_of_match);
++#endif
++
++static struct platform_driver mtk_crypto_driver = {
++ .probe = mtk_crypto_probe,
++ .remove_new = mtk_crypto_remove,
++ .driver = {
++ .name = "mtk-eip93",
++ .of_match_table = of_match_ptr(mtk_crypto_of_match),
++ },
++};
++module_platform_driver(mtk_crypto_driver);
++
++MODULE_AUTHOR("Richard van Schagen <vschagen@cs.com>");
++MODULE_ALIAS("platform:" KBUILD_MODNAME);
++MODULE_DESCRIPTION("Mediatek EIP-93 crypto engine driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-main.h
+@@ -0,0 +1,146 @@
++/* SPDX-License-Identifier: GPL-2.0
++ *
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef _EIP93_MAIN_H_
++#define _EIP93_MAIN_H_
++
++#include <crypto/internal/aead.h>
++#include <crypto/internal/hash.h>
++#include <crypto/internal/rng.h>
++#include <crypto/internal/skcipher.h>
++#include <linux/device.h>
++#include <linux/interrupt.h>
++
++#define MTK_RING_SIZE 512
++#define MTK_RING_BUSY 32
++#define MTK_CRA_PRIORITY 1500
++
++/* cipher algorithms */
++#define MTK_ALG_DES BIT(0)
++#define MTK_ALG_3DES BIT(1)
++#define MTK_ALG_AES BIT(2)
++#define MTK_ALG_MASK GENMASK(2, 0)
++/* hash and hmac algorithms */
++#define MTK_HASH_MD5 BIT(3)
++#define MTK_HASH_SHA1 BIT(4)
++#define MTK_HASH_SHA224 BIT(5)
++#define MTK_HASH_SHA256 BIT(6)
++#define MTK_HASH_HMAC BIT(7)
++#define MTK_HASH_MASK GENMASK(6, 3)
++/* cipher modes */
++#define MTK_MODE_CBC BIT(8)
++#define MTK_MODE_ECB BIT(9)
++#define MTK_MODE_CTR BIT(10)
++#define MTK_MODE_RFC3686 BIT(11)
++#define MTK_MODE_MASK GENMASK(10, 8)
++
++/* cipher encryption/decryption operations */
++#define MTK_ENCRYPT BIT(12)
++#define MTK_DECRYPT BIT(13)
++
++#define MTK_BUSY BIT(14)
++
++/* descriptor flags */
++#define MTK_DESC_ASYNC BIT(31)
++#define MTK_DESC_SKCIPHER BIT(30)
++#define MTK_DESC_AEAD BIT(29)
++#define MTK_DESC_AHASH BIT(28)
++#define MTK_DESC_PRNG BIT(27)
++#define MTK_DESC_FAKE_HMAC BIT(26)
++#define MTK_DESC_LAST BIT(25)
++#define MTK_DESC_FINISH BIT(24)
++#define MTK_DESC_IPSEC BIT(23)
++#define MTK_DESC_DMA_IV BIT(22)
++
++#define IS_DES(flags) (flags & MTK_ALG_DES)
++#define IS_3DES(flags) (flags & MTK_ALG_3DES)
++#define IS_AES(flags) (flags & MTK_ALG_AES)
++
++#define IS_HASH_MD5(flags) (flags & MTK_HASH_MD5)
++#define IS_HASH_SHA1(flags) (flags & MTK_HASH_SHA1)
++#define IS_HASH_SHA224(flags) (flags & MTK_HASH_SHA224)
++#define IS_HASH_SHA256(flags) (flags & MTK_HASH_SHA256)
++#define IS_HMAC(flags) (flags & MTK_HASH_HMAC)
++
++#define IS_CBC(mode) (mode & MTK_MODE_CBC)
++#define IS_ECB(mode) (mode & MTK_MODE_ECB)
++#define IS_CTR(mode) (mode & MTK_MODE_CTR)
++#define IS_RFC3686(mode) (mode & MTK_MODE_RFC3686)
++
++#define IS_BUSY(flags) (flags & MTK_BUSY)
++#define IS_DMA_IV(flags) (flags & MTK_DESC_DMA_IV)
++
++#define IS_ENCRYPT(dir) (dir & MTK_ENCRYPT)
++#define IS_DECRYPT(dir) (dir & MTK_DECRYPT)
++
++#define IS_CIPHER(flags) (flags & (MTK_ALG_DES || \
++ MTK_ALG_3DES || \
++ MTK_ALG_AES))
++
++#define IS_HASH(flags) (flags & (MTK_HASH_MD5 || \
++ MTK_HASH_SHA1 || \
++ MTK_HASH_SHA224 || \
++ MTK_HASH_SHA256))
++
++/**
++ * struct mtk_device - crypto engine device structure
++ */
++struct mtk_device {
++ void __iomem *base;
++ struct device *dev;
++ struct clk *clk;
++ int irq;
++ struct mtk_ring *ring;
++ struct mtk_state_pool *saState_pool;
++};
++
++struct mtk_desc_ring {
++ void *base;
++ void *base_end;
++ dma_addr_t base_dma;
++ /* write and read pointers */
++ void *read;
++ void *write;
++ /* descriptor element offset */
++ u32 offset;
++};
++
++struct mtk_state_pool {
++ void *base;
++ dma_addr_t base_dma;
++ bool in_use;
++};
++
++struct mtk_ring {
++ struct tasklet_struct done_task;
++ /* command/result rings */
++ struct mtk_desc_ring cdr;
++ struct mtk_desc_ring rdr;
++ spinlock_t write_lock;
++ spinlock_t read_lock;
++ atomic_t free;
++ /* saState */
++ struct mtk_state_pool *saState_pool;
++ void *saState;
++ dma_addr_t saState_dma;
++};
++
++enum mtk_alg_type {
++ MTK_ALG_TYPE_AEAD,
++ MTK_ALG_TYPE_SKCIPHER,
++};
++
++struct mtk_alg_template {
++ struct mtk_device *mtk;
++ enum mtk_alg_type type;
++ u32 flags;
++ union {
++ struct aead_alg aead;
++ struct skcipher_alg skcipher;
++ } alg;
++};
++
++#endif /* _EIP93_MAIN_H_ */
+--- /dev/null
++++ b/drivers/crypto/mtk-eip93/eip93-regs.h
+@@ -0,0 +1,382 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/*
++ * Copyright (C) 2019 - 2021
++ *
++ * Richard van Schagen <vschagen@icloud.com>
++ */
++#ifndef REG_EIP93_H
++#define REG_EIP93_H
++
++#define EIP93_REG_WIDTH 4
++/*-----------------------------------------------------------------------------
++ * Register Map
++ */
++#define DESP_BASE 0x0000000
++#define EIP93_REG_PE_CTRL_STAT ((DESP_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_SOURCE_ADDR ((DESP_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_DEST_ADDR ((DESP_BASE)+(0x02 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_SA_ADDR ((DESP_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_ADDR ((DESP_BASE)+(0x04 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_USER_ID ((DESP_BASE)+(0x06 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_LENGTH ((DESP_BASE)+(0x07 * EIP93_REG_WIDTH))
++
++//PACKET ENGINE RING configuration registers
++#define PE_RNG_BASE 0x0000080
++
++#define EIP93_REG_PE_CDR_BASE ((PE_RNG_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RDR_BASE ((PE_RNG_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RING_CONFIG ((PE_RNG_BASE)+(0x02 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RING_THRESH ((PE_RNG_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_CD_COUNT ((PE_RNG_BASE)+(0x04 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RD_COUNT ((PE_RNG_BASE)+(0x05 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_RING_RW_PNTR ((PE_RNG_BASE)+(0x06 * EIP93_REG_WIDTH))
++
++//PACKET ENGINE configuration registers
++#define PE_CFG_BASE 0x0000100
++#define EIP93_REG_PE_CONFIG ((PE_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_STATUS ((PE_CFG_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_BUF_THRESH ((PE_CFG_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_INBUF_COUNT ((PE_CFG_BASE)+(0x04 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_OUTBUF_COUNT ((PE_CFG_BASE)+(0x05 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_BUF_RW_PNTR ((PE_CFG_BASE)+(0x06 * EIP93_REG_WIDTH))
++
++//PACKET ENGINE endian config
++#define EN_CFG_BASE 0x00001CC
++#define EIP93_REG_PE_ENDIAN_CONFIG ((EN_CFG_BASE)+(0x00 * EIP93_REG_WIDTH))
++
++//EIP93 CLOCK control registers
++#define CLOCK_BASE 0x01E8
++#define EIP93_REG_PE_CLOCK_CTRL ((CLOCK_BASE)+(0x00 * EIP93_REG_WIDTH))
++
++//EIP93 Device Option and Revision Register
++#define REV_BASE 0x01F4
++#define EIP93_REG_PE_OPTION_1 ((REV_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_OPTION_0 ((REV_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PE_REVISION ((REV_BASE)+(0x02 * EIP93_REG_WIDTH))
++
++//EIP93 Interrupt Control Register
++#define INT_BASE 0x0200
++#define EIP93_REG_INT_UNMASK_STAT ((INT_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_INT_MASK_STAT ((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_INT_CLR ((INT_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_INT_MASK ((INT_BASE)+(0x02 * EIP93_REG_WIDTH))
++#define EIP93_REG_INT_CFG ((INT_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_MASK_ENABLE ((INT_BASE)+(0X04 * EIP93_REG_WIDTH))
++#define EIP93_REG_MASK_DISABLE ((INT_BASE)+(0X05 * EIP93_REG_WIDTH))
++
++//EIP93 SA Record register
++#define SA_BASE 0x0400
++#define EIP93_REG_SA_CMD_0 ((SA_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_SA_CMD_1 ((SA_BASE)+(0x01 * EIP93_REG_WIDTH))
++
++//#define EIP93_REG_SA_READY ((SA_BASE)+(31 * EIP93_REG_WIDTH))
++
++//State save register
++#define STATE_BASE 0x0500
++#define EIP93_REG_STATE_IV_0 ((STATE_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_STATE_IV_1 ((STATE_BASE)+(0x01 * EIP93_REG_WIDTH))
++
++#define EIP93_PE_ARC4STATE_BASEADDR_REG 0x0700
++
++//RAM buffer start address
++#define EIP93_INPUT_BUFFER 0x0800
++#define EIP93_OUTPUT_BUFFER 0x0800
++
++//EIP93 PRNG Configuration Register
++#define PRNG_BASE 0x0300
++#define EIP93_REG_PRNG_STAT ((PRNG_BASE)+(0x00 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_CTRL ((PRNG_BASE)+(0x01 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_SEED_0 ((PRNG_BASE)+(0x02 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_SEED_1 ((PRNG_BASE)+(0x03 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_SEED_2 ((PRNG_BASE)+(0x04 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_SEED_3 ((PRNG_BASE)+(0x05 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_KEY_0 ((PRNG_BASE)+(0x06 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_KEY_1 ((PRNG_BASE)+(0x07 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_KEY_2 ((PRNG_BASE)+(0x08 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_KEY_3 ((PRNG_BASE)+(0x09 * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_RES_0 ((PRNG_BASE)+(0x0A * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_RES_1 ((PRNG_BASE)+(0x0B * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_RES_2 ((PRNG_BASE)+(0x0C * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_RES_3 ((PRNG_BASE)+(0x0D * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_LFSR_0 ((PRNG_BASE)+(0x0E * EIP93_REG_WIDTH))
++#define EIP93_REG_PRNG_LFSR_1 ((PRNG_BASE)+(0x0F * EIP93_REG_WIDTH))
++
++/*-----------------------------------------------------------------------------
++ * Constants & masks
++ */
++
++#define EIP93_SUPPORTED_INTERRUPTS_MASK 0xffff7f00
++#define EIP93_PRNG_DT_TEXT_LOWERHALF 0xDEAD
++#define EIP93_PRNG_DT_TEXT_UPPERHALF 0xC0DE
++#define EIP93_10BITS_MASK 0X3FF
++#define EIP93_12BITS_MASK 0XFFF
++#define EIP93_4BITS_MASK 0X04
++#define EIP93_20BITS_MASK 0xFFFFF
++
++#define EIP93_MIN_DESC_DONE_COUNT 0
++#define EIP93_MAX_DESC_DONE_COUNT 15
++
++#define EIP93_MIN_DESC_PENDING_COUNT 0
++#define EIP93_MAX_DESC_PENDING_COUNT 1023
++
++#define EIP93_MIN_TIMEOUT_COUNT 0
++#define EIP93_MAX_TIMEOUT_COUNT 15
++
++#define EIP93_MIN_PE_INPUT_THRESHOLD 1
++#define EIP93_MAX_PE_INPUT_THRESHOLD 511
++
++#define EIP93_MIN_PE_OUTPUT_THRESHOLD 1
++#define EIP93_MAX_PE_OUTPUT_THRESHOLD 432
++
++#define EIP93_MIN_PE_RING_SIZE 1
++#define EIP93_MAX_PE_RING_SIZE 1023
++
++#define EIP93_MIN_PE_DESCRIPTOR_SIZE 7
++#define EIP93_MAX_PE_DESCRIPTOR_SIZE 15
++
++//3DES keys,seed,known data and its result
++#define EIP93_KEY_0 0x133b3454
++#define EIP93_KEY_1 0x5e5b890b
++#define EIP93_KEY_2 0x5eb30757
++#define EIP93_KEY_3 0x93ab15f7
++#define EIP93_SEED_0 0x62c4bf5e
++#define EIP93_SEED_1 0x972667c8
++#define EIP93_SEED_2 0x6345bf67
++#define EIP93_SEED_3 0xcb3482bf
++#define EIP93_LFSR_0 0xDEADC0DE
++#define EIP93_LFSR_1 0xBEEFF00D
++
++/*-----------------------------------------------------------------------------
++ * EIP93 device initialization specifics
++ */
++
++/*----------------------------------------------------------------------------
++ * Byte Order Reversal Mechanisms Supported in EIP93
++ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
++ * EIP93_BO_REVERSE_WORD : reverse the byte order within a word
++ * EIP93_BO_REVERSE_DUAL_WORD : reverse the byte order within a dual-word
++ * EIP93_BO_REVERSE_QUAD_WORD : reverse the byte order within a quad-word
++ */
++enum EIP93_Byte_Order_Value_t {
++ EIP93_BO_REVERSE_HALF_WORD = 1,
++ EIP93_BO_REVERSE_WORD = 2,
++ EIP93_BO_REVERSE_DUAL_WORD = 4,
++ EIP93_BO_REVERSE_QUAD_WORD = 8,
++};
++
++/*----------------------------------------------------------------------------
++ * Byte Order Reversal Mechanisms Supported in EIP93 for Target Data
++ * EIP93_BO_REVERSE_HALF_WORD : reverse the byte order within a half-word
++ * EIP93_BO_REVERSE_WORD : reverse the byte order within a word
++ */
++enum EIP93_Byte_Order_Value_TD_t {
++ EIP93_BO_REVERSE_HALF_WORD_TD = 1,
++ EIP93_BO_REVERSE_WORD_TD = 2,
++};
++
++// BYTE_ORDER_CFG register values
++#define EIP93_BYTE_ORDER_PD EIP93_BO_REVERSE_WORD
++#define EIP93_BYTE_ORDER_SA EIP93_BO_REVERSE_WORD
++#define EIP93_BYTE_ORDER_DATA EIP93_BO_REVERSE_WORD
++#define EIP93_BYTE_ORDER_TD EIP93_BO_REVERSE_WORD_TD
++
++// INT_CFG register values
++#define EIP93_INT_HOST_OUTPUT_TYPE 0
++#define EIP93_INT_PULSE_CLEAR 0
++
++/*
++ * Interrupts of EIP93
++ */
++
++enum EIP93_InterruptSource_t {
++ EIP93_INT_PE_CDRTHRESH_REQ = BIT(0),
++ EIP93_INT_PE_RDRTHRESH_REQ = BIT(1),
++ EIP93_INT_PE_OPERATION_DONE = BIT(9),
++ EIP93_INT_PE_INBUFTHRESH_REQ = BIT(10),
++ EIP93_INT_PE_OUTBURTHRSH_REQ = BIT(11),
++ EIP93_INT_PE_PRNG_IRQ = BIT(12),
++ EIP93_INT_PE_ERR_REG = BIT(13),
++ EIP93_INT_PE_RD_DONE_IRQ = BIT(16),
++};
++
++union peConfig_w {
++ u32 word;
++ struct {
++ u32 resetPE :1;
++ u32 resetRing :1;
++ u32 reserved :6;
++ u32 peMode :2;
++ u32 enCDRupdate :1;
++ u32 reserved2 :5;
++ u32 swapCDRD :1;
++ u32 swapSA :1;
++ u32 swapData :1;
++ u32 reserved3 :13;
++ } bits;
++} __packed;
++
++union peEndianCfg_w {
++ u32 word;
++ struct {
++ u32 masterByteSwap :8;
++ u32 reserved :8;
++ u32 targetByteSwap :8;
++ u32 reserved2 :8;
++ } bits;
++} __packed;
++
++union peIntCfg_w {
++ u32 word;
++ struct {
++ u32 PulseClear :1;
++ u32 IntType :1;
++ u32 reserved :30;
++ } bits;
++} __packed;
++
++union peClockCfg_w {
++ u32 word;
++ struct {
++ u32 enPEclk :1;
++ u32 enDESclk :1;
++ u32 enAESclk :1;
++ u32 reserved :1;
++ u32 enHASHclk :1;
++ u32 reserved2 :27;
++ } bits;
++} __packed;
++
++union peBufThresh_w {
++ u32 word;
++ struct {
++ u32 inputBuffer :8;
++ u32 reserved :8;
++ u32 outputBuffer :8;
++ u32 reserved2 :8;
++ } bits;
++} __packed;
++
++union peRingThresh_w {
++ u32 word;
++ struct {
++ u32 CDRThresh :10;
++ u32 reserved :6;
++ u32 RDRThresh :10;
++ u32 RDTimeout :4;
++ u32 reserved2 :1;
++ u32 enTimeout :1;
++ } bits;
++} __packed;
++
++union peRingCfg_w {
++ u32 word;
++ struct {
++ u32 ringSize :10;
++ u32 reserved :6;
++ u32 ringOffset :8;
++ u32 reserved2 :8;
++ } bits;
++} __packed;
++
++union saCmd0 {
++ u32 word;
++ struct {
++ u32 opCode :3;
++ u32 direction :1;
++ u32 opGroup :2;
++ u32 padType :2;
++ u32 cipher :4;
++ u32 hash :4;
++ u32 reserved2 :1;
++ u32 scPad :1;
++ u32 extPad :1;
++ u32 hdrProc :1;
++ u32 digestLength :4;
++ u32 ivSource :2;
++ u32 hashSource :2;
++ u32 saveIv :1;
++ u32 saveHash :1;
++ u32 reserved1 :2;
++ } bits;
++} __packed;
++
++union saCmd1 {
++ u32 word;
++ struct {
++ u32 copyDigest :1;
++ u32 copyHeader :1;
++ u32 copyPayload :1;
++ u32 copyPad :1;
++ u32 reserved4 :4;
++ u32 cipherMode :2;
++ u32 reserved3 :1;
++ u32 sslMac :1;
++ u32 hmac :1;
++ u32 byteOffset :1;
++ u32 reserved2 :2;
++ u32 hashCryptOffset :8;
++ u32 aesKeyLen :3;
++ u32 reserved1 :1;
++ u32 aesDecKey :1;
++ u32 seqNumCheck :1;
++ u32 reserved0 :2;
++ } bits;
++} __packed;
++
++struct saRecord_s {
++ union saCmd0 saCmd0;
++ union saCmd1 saCmd1;
++ u32 saKey[8];
++ u32 saIDigest[8];
++ u32 saODigest[8];
++ u32 saSpi;
++ u32 saSeqNum[2];
++ u32 saSeqNumMask[2];
++ u32 saNonce;
++} __packed;
++
++struct saState_s {
++ u32 stateIv[4];
++ u32 stateByteCnt[2];
++ u32 stateIDigest[8];
++} __packed;
++
++union peCrtlStat_w {
++ u32 word;
++ struct {
++ u32 hostReady :1;
++ u32 peReady :1;
++ u32 reserved :1;
++ u32 initArc4 :1;
++ u32 hashFinal :1;
++ u32 haltMode :1;
++ u32 prngMode :2;
++ u32 padValue :8;
++ u32 errStatus :8;
++ u32 padCrtlStat :8;
++ } bits;
++} __packed;
++
++union peLength_w {
++ u32 word;
++ struct {
++ u32 length :20;
++ u32 reserved :2;
++ u32 hostReady :1;
++ u32 peReady :1;
++ u32 byPass :8;
++ } bits;
++} __packed;
++
++struct eip93_descriptor_s {
++ union peCrtlStat_w peCrtlStat;
++ u32 srcAddr;
++ u32 dstAddr;
++ u32 saAddr;
++ u32 stateAddr;
++ u32 arc4Addr;
++ u32 userId;
++ union peLength_w peLength;
++} __packed;
++
++#endif
+--- a/drivers/crypto/Kconfig
++++ b/drivers/crypto/Kconfig
+@@ -797,4 +797,6 @@ config CRYPTO_DEV_SA2UL
+ source "drivers/crypto/aspeed/Kconfig"
+ source "drivers/crypto/starfive/Kconfig"
+
++source "drivers/crypto/mtk-eip93/Kconfig"
++
+ endif # CRYPTO_HW
+--- a/drivers/crypto/Makefile
++++ b/drivers/crypto/Makefile
+@@ -51,3 +51,4 @@ obj-y += hisilicon/
+ obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
+ obj-y += intel/
+ obj-y += starfive/
++obj-$(CONFIG_CRYPTO_DEV_EIP93) += mtk-eip93/
--- /dev/null
+From ba92c0187006e2a6eae9573a569d275b0bd31732 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 2 May 2025 23:04:27 +0200
+Subject: [PATCH] Input sx951x: add Semtech SX9512/SX9513 driver
+
+The Semtech SX9512/SX9513 is a family of capacitive touch-keyboard
+controllers.
+
+All chips offer 8 channel touch sensitive inputs with one LED driver per
+output channel.
+
+The also SX9512 supports proximity detection which is currently not
+supported with the driver.
+
+This chip can be found on the Genexis Pulse EX400 repeater platform.
+
+Link: https://www.mouser.com/datasheet/2/761/SEMTS05226_1-2575172.pdf
+Link: https://www.spinics.net/lists/kernel/msg5669349.html
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/input/keyboard/Kconfig | 11 +
+ drivers/input/keyboard/Makefile | 1 +
+ drivers/input/keyboard/sx951x.c | 490 ++++++++++++++++++++++++++++++++
+ 3 files changed, 502 insertions(+)
+ create mode 100644 drivers/input/keyboard/sx951x.c
+
+--- a/drivers/input/keyboard/Kconfig
++++ b/drivers/input/keyboard/Kconfig
+@@ -616,6 +616,17 @@ config KEYBOARD_SUNKBD
+ To compile this driver as a module, choose M here: the
+ module will be called sunkbd.
+
++config KEYBOARD_SX951X
++ tristate "Semtech SX951X capacitive touch controller"
++ depends on OF && I2C
++ select REGMAP_I2C
++ help
++ Say Y here to enable the Semtech SX9512/SX9153 capacitive
++ touch controller driver.
++
++ To compile this driver as a module, choose M here: the
++ module will be called sx951x.
++
+ config KEYBOARD_SH_KEYSC
+ tristate "SuperH KEYSC keypad support"
+ depends on ARCH_SHMOBILE || COMPILE_TEST
+--- a/drivers/input/keyboard/Makefile
++++ b/drivers/input/keyboard/Makefile
+@@ -66,6 +66,7 @@ obj-$(CONFIG_KEYBOARD_STOWAWAY) += stow
+ obj-$(CONFIG_KEYBOARD_ST_KEYSCAN) += st-keyscan.o
+ obj-$(CONFIG_KEYBOARD_SUN4I_LRADC) += sun4i-lradc-keys.o
+ obj-$(CONFIG_KEYBOARD_SUNKBD) += sunkbd.o
++obj-$(CONFIG_KEYBOARD_SX951X) += sx951x.o
+ obj-$(CONFIG_KEYBOARD_TC3589X) += tc3589x-keypad.o
+ obj-$(CONFIG_KEYBOARD_TEGRA) += tegra-kbc.o
+ obj-$(CONFIG_KEYBOARD_TM2_TOUCHKEY) += tm2-touchkey.o
+--- /dev/null
++++ b/drivers/input/keyboard/sx951x.c
+@@ -0,0 +1,490 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Input driver for Semtech SX9512/SX9513 capacitive touch sensors.
++ *
++ * The difference between SX9512 and SX9513 is the presence of proximity
++ * sensing capabilities on the SX9512.
++ *
++ * SX951xB is the identical chip but with a different I2C address.
++ *
++ * (c) 2025 David Bauer <mail@david-bauer.net>
++ */
++
++ #include <linux/kernel.h>
++ #include <linux/module.h>
++ #include <linux/input.h>
++ #include <linux/leds.h>
++ #include <linux/of.h>
++ #include <linux/regmap.h>
++ #include <linux/i2c.h>
++ #include <linux/gpio/consumer.h>
++ #include <linux/bitfield.h>
++
++ /* Generic properties */
++#define SX951X_I2C_ADDRESS 0x2b
++#define SX951XB_I2C_ADDRESS_ 0x2d
++#define SX951X_NUM_CHANNELS 8
++#define SX951X_POLL_INTERVAL 100
++
++/* Registers*/
++#define SX951X_REG_IRQ_SRC 0x00
++#define SX951X_REG_TOUCH_STATUS 0x01
++#define SX951X_REG_PROXIMITY_STATUS 0x02
++#define SX951X_REG_COMPENSATION_STATUS 0x03
++#define SX951X_REG_IRQ_NVM_CTRL 0x04
++#define SX951X_REG_SPO2_MODE_CTRL 0x07
++#define SX951X_REG_PWR_KEY_CTRL 0x08
++#define SX951X_REG_IRQ_MASK 0x09
++
++/* LED registers */
++#define SX951X_REG_LED_MAP_ENG1 0x0c
++#define SX951X_REG_LED_MAP_ENG2 0x0d
++#define SX951X_REG_LED_PWM_FREQ 0x0e
++#define SX951X_REG_LED_MODE 0x0f
++#define SX951X_REG_LED_IDLE 0x10
++#define SX951X_REG_LED_OFF_DELAY 0x11
++#define SX951X_REG_LED_ON_ENG1 0x12
++#define SX951X_REG_LED_FADE_ENG1 0x13
++#define SX951X_REG_LED_ON_ENG2 0x14
++#define SX951X_REG_LED_FADE_ENG2 0x15
++#define SX951X_REG_LED_POWER_IDLE 0x16
++#define SX951X_REG_LED_POWER_ON 0x17
++#define SX951X_REG_LED_POWER_OFF 0x18
++#define SX951X_REG_LED_POWER_FADE 0x19
++#define SX951X_REG_LED_POWER_ON_PULSE 0x1a
++#define SX951X_REG_LED_POWER_MODE 0x1b
++
++/* Capacitive touch sensing registers*/
++#define SX951X_REG_CAP_SENSE_ENABLE 0x1e
++
++#define SX951X_REG_CAP_SENSE_RANGE(x) (0x1f + (x))
++#define SX951X_REG_CAP_SENSE_RANGE_CIN_DELTA_MASK GENMASK(1, 0)
++
++#define SX951X_REG_CAP_SENSE_THRESH(x) (0x28 + (x))
++#define SX951X_REG_CAP_SENSE_THRESH_ALL 0x30
++
++#define SX951X_REG_CAP_SENSE_OP 0x31
++#define SX951X_REG_CAP_SENSE_MODE 0x32
++#define SX951X_REG_CAP_SENSE_DEBOUNCE 0x33
++
++/* Reset register*/
++#define SX951X_REG_SOFT_RESET 0xff
++
++/* Default properties (keys)*/
++#define SX951X_KEY_DEFAULT_CIN_DELTA 0x03
++#define SX951X_KEY_DEFAULT_SENSE_THRESHOLD 0x04
++
++struct sx951x_key_data {
++ u32 cin_delta;
++ u32 sense_threshold;
++};
++
++struct sx951x_led {
++#ifdef CONFIG_LEDS_CLASS
++ struct led_classdev cdev;
++ struct sx951x_priv *priv;
++
++ u32 reg;
++ bool registered;
++#endif
++};
++
++struct sx951x_priv {
++ struct regmap *regmap;
++ struct device *dev;
++ struct input_dev *idev;
++ const struct sx951x_hw_data *hw;
++
++ struct sx951x_led leds[SX951X_NUM_CHANNELS];
++
++ /* device-config */
++ u32 poll_interval;
++
++ /* key-config */
++ u32 keycodes[SX951X_NUM_CHANNELS];
++ struct sx951x_key_data key_data[SX951X_NUM_CHANNELS];
++};
++
++struct sx951x_hw_data {
++ bool has_proximity_sensing;
++};
++
++static const struct reg_default sx951x_reg_defaults[] = {
++ { SX951X_REG_LED_MAP_ENG1, 0x00 },
++ { SX951X_REG_LED_MAP_ENG2, 0x00 },
++ { SX951X_REG_LED_PWM_FREQ, 0x10 },
++ { SX951X_REG_LED_IDLE, 0xff },
++ { SX951X_REG_LED_ON_ENG1, 0xff },
++ { SX951X_REG_LED_ON_ENG2, 0xff },
++ { SX951X_REG_LED_POWER_IDLE, 0xff },
++ { SX951X_REG_LED_POWER_ON, 0xff },
++ { SX951X_REG_CAP_SENSE_ENABLE, 0x00 },
++ { SX951X_REG_CAP_SENSE_RANGE(0), 0x40 },
++ { SX951X_REG_CAP_SENSE_RANGE(1), 0x40 },
++ { SX951X_REG_CAP_SENSE_RANGE(2), 0x40 },
++ { SX951X_REG_CAP_SENSE_RANGE(3), 0x40 },
++ { SX951X_REG_CAP_SENSE_RANGE(4), 0x40 },
++ { SX951X_REG_CAP_SENSE_RANGE(5), 0x40 },
++ { SX951X_REG_CAP_SENSE_RANGE(6), 0x40 },
++ { SX951X_REG_CAP_SENSE_RANGE(7), 0x40 },
++ { SX951X_REG_CAP_SENSE_THRESH(0), 0x0f },
++ { SX951X_REG_CAP_SENSE_THRESH(1), 0x0f },
++ { SX951X_REG_CAP_SENSE_THRESH(2), 0x0f },
++ { SX951X_REG_CAP_SENSE_THRESH(3), 0x0f },
++ { SX951X_REG_CAP_SENSE_THRESH(4), 0x0f },
++ { SX951X_REG_CAP_SENSE_THRESH(5), 0x0f },
++ { SX951X_REG_CAP_SENSE_THRESH(6), 0x0f },
++ { SX951X_REG_CAP_SENSE_THRESH(7), 0x0f },
++ { SX951X_REG_CAP_SENSE_THRESH_ALL, 0x0f },
++ { SX951X_REG_CAP_SENSE_OP, 0x14 },
++ { SX951X_REG_CAP_SENSE_MODE, 0x70 },
++ { SX951X_REG_CAP_SENSE_DEBOUNCE, 0xff },
++};
++
++static bool sx951x_volatile_reg(struct device *dev, unsigned int reg)
++{
++ switch (reg) {
++ case SX951X_REG_TOUCH_STATUS:
++ return true;
++ default:
++ return false;
++ }
++}
++
++static const struct regmap_config sx951x_regmap_config = {
++ .reg_bits = 8,
++ .val_bits = 8,
++
++ .max_register = SX951X_REG_SOFT_RESET,
++
++ .reg_defaults = sx951x_reg_defaults,
++ .num_reg_defaults = ARRAY_SIZE(sx951x_reg_defaults),
++
++ .cache_type = REGCACHE_MAPLE,
++ .volatile_reg = sx951x_volatile_reg,
++};
++
++#ifdef CONFIG_LEDS_CLASS
++static int sx951x_led_set(struct led_classdev *cdev, enum led_brightness value)
++{
++ struct sx951x_led *led = container_of(cdev, struct sx951x_led, cdev);
++ struct sx951x_priv *priv = led->priv;
++
++ return regmap_update_bits(priv->regmap,
++ SX951X_REG_LED_MAP_ENG2,
++ BIT(led->reg),
++ value ? BIT(led->reg) : 0);
++}
++
++static int sx951x_led_init(struct sx951x_priv *priv,
++ struct device_node *channel_node, u32 reg)
++{
++ struct device_node *led_node;
++ struct sx951x_led *led = &priv->leds[reg];
++ struct led_init_data init_data = {};
++ int error;
++
++ if (led->registered) {
++ dev_err(priv->dev,
++ "LED %d already registered\n", reg);
++ return -EINVAL;
++ }
++
++ led_node = of_get_child_by_name(channel_node, "led");
++ if (!led_node) {
++ /* No LED */
++ return 0;
++ }
++
++ led->cdev.flags = 0;
++ led->cdev.brightness_set_blocking = sx951x_led_set;
++ led->cdev.max_brightness = 1;
++ led->cdev.brightness = LED_OFF;
++
++ init_data.default_label = of_get_property(led_node, "label", NULL);
++ init_data.fwnode = of_fwnode_handle(led_node);
++
++ led->reg = reg;
++ led->priv = priv;
++
++ error = devm_led_classdev_register_ext(priv->dev, &led->cdev, &init_data);
++ if (error)
++ return error;
++
++ return 0;
++}
++#endif
++
++static void sx951x_poll(struct input_dev *input)
++{
++ struct sx951x_priv *priv = input_get_drvdata(input);
++ struct device *dev = priv->dev;
++ unsigned int val;
++ int error;
++ int i;
++
++ error = regmap_read(priv->regmap, SX951X_REG_TOUCH_STATUS, &val);
++ if (error) {
++ dev_err(dev, "Failed to read touch status: %d\n", error);
++ return;
++ }
++
++ for (i = 0; i < SX951X_NUM_CHANNELS; i++) {
++ if (priv->keycodes[i] == KEY_RESERVED)
++ continue;
++
++ input_report_key(input, priv->keycodes[i], !!(val & BIT(i)));
++ input_sync(input);
++ }
++}
++
++static int sx951x_channel_init(struct sx951x_priv *priv, struct device_node *of_node,
++ u32 chan_idx)
++{
++ struct sx951x_key_data *key_data;
++ struct device *dev = priv->dev;
++ int error;
++
++ key_data = &priv->key_data[chan_idx];
++
++ /* Defaults */
++ key_data->cin_delta = SX951X_KEY_DEFAULT_CIN_DELTA;
++ key_data->sense_threshold = SX951X_KEY_DEFAULT_SENSE_THRESHOLD;
++
++ error = of_property_read_u32(of_node, "linux,keycodes",
++ &priv->keycodes[chan_idx]);
++ if (error) {
++ /* Not configured */
++ return 0;
++ }
++
++ error = of_property_read_u32(of_node, "semtech,cin-delta",
++ &key_data->cin_delta);
++ if (key_data->cin_delta > 0x03) {
++ dev_err(dev, "Failed to read cin-delta for channel %d: %d\n",
++ chan_idx, error);
++ return error;
++ }
++
++ error = of_property_read_u32(of_node, "semtech,sense-threshold",
++ &key_data->sense_threshold);
++ if (key_data->sense_threshold > 0xff) {
++ dev_err(dev, "Failed to read sense-threshold for channel %d: %d\n",
++ chan_idx, error);
++ return error;
++ }
++
++ error = regmap_update_bits(priv->regmap,
++ SX951X_REG_CAP_SENSE_RANGE(chan_idx),
++ SX951X_REG_CAP_SENSE_RANGE_CIN_DELTA_MASK,
++ key_data->cin_delta);
++
++ if (error) {
++ dev_err(dev, "Failed to set cin-delta for channel %d: %d\n",
++ chan_idx, error);
++ return error;
++ }
++
++ error = regmap_write(priv->regmap,
++ SX951X_REG_CAP_SENSE_THRESH(chan_idx),
++ key_data->sense_threshold);
++ if (error) {
++ dev_err(dev, "Failed to set sense-threshold for channel %d: %d\n",
++ chan_idx, error);
++ return error;
++ }
++
++ return 0;
++}
++
++static int sx951x_channels_init(struct sx951x_priv *priv)
++{
++ struct device *dev = priv->dev;
++ unsigned int channels = 0;
++ int error;
++ u32 reg;
++
++ for_each_child_of_node_scoped(dev->of_node, child) {
++ error = of_property_read_u32(child, "reg", ®);
++ if (error != 0 || reg >= SX951X_NUM_CHANNELS) {
++ dev_err(dev, "Invalid channel %d\n", reg);
++ return -EINVAL;
++ }
++
++ priv->keycodes[reg] = KEY_RESERVED;
++
++ error = sx951x_channel_init(priv, child, reg);
++ if (error) {
++ dev_err(dev, "Failed to initialize channel %d: %d\n",
++ reg, error);
++ return error;
++ }
++
++ if (priv->keycodes[reg] != KEY_RESERVED)
++ channels |= BIT(reg);
++
++#ifdef CONFIG_LEDS_CLASS
++ error = sx951x_led_init(priv, child, reg);
++ if (error) {
++ dev_err(dev, "Failed to initialize LED %d: %d\n",
++ reg, error);
++ return error;
++ }
++#endif
++ }
++
++ /* Enable sensing on channels with keycode configured */
++ error = regmap_write(priv->regmap,
++ SX951X_REG_CAP_SENSE_ENABLE,
++ channels);
++
++ return 0;
++}
++
++static int sx951x_input_init(struct sx951x_priv *priv)
++{
++ struct device *dev = priv->dev;
++ int i, error;
++
++ priv->idev = devm_input_allocate_device(dev);
++ if (!priv->idev)
++ return -ENOMEM;
++
++ priv->idev->name = "SX9512/SX9513 capacitive touch sensor";
++ priv->idev->id.bustype = BUS_I2C;
++ __set_bit(EV_KEY, priv->idev->evbit);
++
++ for (i = 0; i < SX951X_NUM_CHANNELS; i++)
++ __set_bit(priv->keycodes[i], priv->idev->keybit);
++
++ __clear_bit(KEY_RESERVED, priv->idev->keybit);
++
++ priv->idev->keycode = priv->keycodes;
++ priv->idev->keycodesize = sizeof(priv->keycodes[0]);
++ priv->idev->keycodemax = SX951X_NUM_CHANNELS;
++
++ input_set_drvdata(priv->idev, priv);
++
++ error = input_setup_polling(priv->idev, sx951x_poll);
++ if (error) {
++ dev_err(dev, "Unable to set up polling: %d\n", error);
++ return error;
++ }
++
++ input_set_poll_interval(priv->idev, priv->poll_interval);
++
++ error = input_register_device(priv->idev);
++ if (error) {
++ dev_err(dev, "Unable to register polled device: %d\n",
++ error);
++ return error;
++ }
++
++ return 0;
++}
++
++static int sx951x_probe(struct i2c_client *i2c_client)
++{
++ const struct i2c_device_id *id;
++ const struct sx951x_hw_data *hw;
++ struct device *dev = &i2c_client->dev;
++ struct sx951x_priv *priv;
++ int error;
++
++ if (i2c_client->addr != SX951X_I2C_ADDRESS &&
++ i2c_client->addr != SX951XB_I2C_ADDRESS_) {
++ dev_err(dev, "Invalid I2C address: 0x%02x\n",
++ i2c_client->addr);
++ return -ENODEV;
++ }
++
++ id = i2c_client_get_device_id(i2c_client);
++ hw = i2c_get_match_data(i2c_client);
++ if (!id || !hw) {
++ dev_err(dev, "Invalid device configuration\n");
++ return -EINVAL;
++ }
++
++ priv = devm_kzalloc(dev,
++ sizeof(struct sx951x_priv),
++ GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ priv->dev = dev;
++ priv->hw = hw;
++
++ priv->regmap = devm_regmap_init_i2c(i2c_client, &sx951x_regmap_config);
++ if (IS_ERR(priv->regmap))
++ return PTR_ERR(priv->regmap);
++
++ /* Parse device configuration */
++ if (of_property_read_u32(dev->of_node, "poll-interval",
++ &priv->poll_interval))
++ priv->poll_interval = SX951X_POLL_INTERVAL;
++
++ /* Register LED and input channels */
++ error = sx951x_channels_init(priv);
++ if (error) {
++ dev_err(dev, "Failed to initialize channels: %d\n", error);
++ return error;
++ }
++
++ /* Register input device */
++ error = sx951x_input_init(priv);
++ if (error) {
++ dev_err(dev, "Failed to register input device: %d\n", error);
++ return error;
++ }
++
++ return 0;
++}
++
++static void sx951x_remove(struct i2c_client *i2c_client)
++{
++ struct sx951x_priv *priv = i2c_get_clientdata(i2c_client);
++
++ /* Disable sensing */
++ regmap_write(priv->regmap, SX951X_REG_CAP_SENSE_ENABLE, 0x00);
++
++ /* Turn off all LEDs */
++ regmap_write(priv->regmap, SX951X_REG_LED_MAP_ENG2, 0x00);
++}
++
++static const struct sx951x_hw_data sx9512_hw_data = {
++ .has_proximity_sensing = true,
++};
++
++static const struct sx951x_hw_data sx9513_hw_data = {
++ .has_proximity_sensing = false,
++};
++
++static const struct of_device_id sx951x_dt_ids[] = {
++ { .compatible = "semtech,sx9512", .data = &sx9512_hw_data },
++ { .compatible = "semtech,sx9513", .data = &sx9513_hw_data },
++ { }
++};
++MODULE_DEVICE_TABLE(of, sx951x_dt_ids);
++
++static const struct i2c_device_id sx951x_i2c_ids[] = {
++ { "sx9512", (kernel_ulong_t)&sx9512_hw_data },
++ { "sx9513", (kernel_ulong_t)&sx9513_hw_data },
++ { }
++};
++MODULE_DEVICE_TABLE(i2c, sx951x_i2c_ids);
++
++static struct i2c_driver sx951x_i2c_driver = {
++ .driver = {
++ .name = "sx951x",
++ .of_match_table = sx951x_dt_ids,
++ },
++ .id_table = sx951x_i2c_ids,
++ .probe = sx951x_probe,
++ .remove = sx951x_remove,
++};
++
++module_i2c_driver(sx951x_i2c_driver);
++
++MODULE_DESCRIPTION("Semtech SX9512/SX9513 driver");
++MODULE_AUTHOR("David Bauer <mail@david-bauer.net>");
++MODULE_LICENSE("GPL");
--- /dev/null
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT2880_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FORCE_NR_CPUS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_RALINK=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IP17XX_PHY=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_AUTO_PFN_OFFSET=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=4
+CONFIG_MIPS_L1_CACHE_SHIFT_4=y
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_LZMA_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_SPLIT_WRGG_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MDIO_RT2880=y
+CONFIG_NET_RALINK_RT2880=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=m
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+# CONFIG_PHY_RALINK_USB is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_MTK_MTMIPS=y
+CONFIG_PINCTRL_RT2880=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+CONFIG_SOC_RT288X=y
+# CONFIG_SOC_RT305X is not set
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB=m
+CONFIG_USB_COMMON=m
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_HCD_PLATFORM=m
+CONFIG_USB_OHCI_HCD=m
+CONFIG_USB_OHCI_HCD_PLATFORM=m
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
--- /dev/null
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_CEVT_R4K=y
+CONFIG_CEVT_SYSTICK_QUIRK=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT305X_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FORCE_NR_CPUS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_RALINK=y
+CONFIG_GPIO_WATCHDOG=y
+# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_JIMAGE_FW=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_RALINK_ESW_RT3050=y
+CONFIG_NET_RALINK_RT3050=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_MTK_MTMIPS=y
+CONFIG_PINCTRL_RT305X=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+# CONFIG_RALINK_ILL_ACC is not set
+CONFIG_RALINK_TIMER=y
+CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+CONFIG_SOC_RT305X=y
+# CONFIG_SOC_RT3883 is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
--- /dev/null
+CONFIG_AR8216_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLK_MTMIPS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_DIEI=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_RIXI=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_CPU_MIPSR2=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CPU_SUPPORTS_MSA=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_PINCTRL=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_DTB_RT3883_EVAL is not set
+CONFIG_DTB_RT_NONE=y
+CONFIG_DTC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FORCE_NR_CPUS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_RALINK=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_INTC=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_MIPS_CMDLINE_FROM_DTB=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+# CONFIG_MIPS_NO_APPENDED_DTB is not set
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_MIPS_SPRAM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
+CONFIG_MTD_SPLIT_SEAMA_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_RALINK_MDIO=y
+CONFIG_NET_RALINK_MDIO_RT2880=y
+CONFIG_NET_RALINK_RT3883=y
+CONFIG_NET_RALINK_SOC=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_SWITCHDEV is not set
+CONFIG_NET_VENDOR_RALINK=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+# CONFIG_PHY_MT7621_PCI is not set
+CONFIG_PHY_RALINK_USB=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_AW9523 is not set
+CONFIG_PINCTRL_MTK_MTMIPS=y
+CONFIG_PINCTRL_RT3883=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RALINK=y
+CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RTL8366_SMI=y
+CONFIG_RTL8367B_PHY=y
+CONFIG_RTL8367_PHY=y
+CONFIG_SERIAL_8250_RT288X=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_MT7620 is not set
+# CONFIG_SOC_MT7621 is not set
+# CONFIG_SOC_RT288X is not set
+# CONFIG_SOC_RT305X is not set
+CONFIG_SOC_RT3883=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_MT7621 is not set
+CONFIG_SPI_RT2880=y
+# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SWCONFIG=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
projects / thirdparty / openwrt.git / commitdiff
