arm64: dts: freescale: imx95-toradex-smarc: Add SER2 interface

The Toradex SMARC iMX95 has four exposed serial interfaces, one of these
is SER2, which supports RTS/CTS.

Add UART support for SMARC SER2.

Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts
index 5b05f256fd52ec45a546e779c3f91e0bd2e0dd8d..7437e523ff639b739dc6cb324836c1b8b7eb9b08 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc-dev.dts
@@ -210,6 +210,11 @@
        status = "okay";
 };
 
+/* SMARC SER2 */
+&lpuart6 {
+       status = "okay";
+};
+
 /* SMARC MDIO, shared between all ethernet ports */
 &netc_emdio {
        status = "okay";

diff --git a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
index 7a73958f6eecc3775b04fe0348c0186386d891df..1d369983cf7ddbeaa0b6ff5e68c59814f310580d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95-toradex-smarc.dtsi
@@ -22,6 +22,7 @@
                rtc1 = &scmi_bbm;
                serial0 = &lpuart2;
                serial1 = &lpuart1;
+               serial2 = &lpuart6;
                serial3 = &lpuart3;
        };
 
@@ -615,6 +616,13 @@
        pinctrl-0 = <&pinctrl_uart3>;
 };
 
+/* SMARC SER2 */
+&lpuart6 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_uart6>;
+       uart-has-rtscts;
+};
+
 &mu7 {
        status = "okay";
 };
@@ -1105,6 +1113,14 @@
                           <IMX95_PAD_GPIO_IO15__LPUART3_RX     0x31e>; /* SMARC P141 - SER3_RX */
        };
 
+       /* SMARC SER2 */
+       pinctrl_uart6: uart6grp {
+               fsl,pins = <IMX95_PAD_GPIO_IO34__LPUART6_CTS_B  0x31e>, /* SMARC P139 - SER2_CTS# */
+                          <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B  0x31e>, /* SMARC P138 - SER2_RTS# */
+                          <IMX95_PAD_GPIO_IO05__LPUART6_RX     0x31e>, /* SMARC P137 - SER2_RX   */
+                          <IMX95_PAD_GPIO_IO04__LPUART6_TX     0x31e>; /* SMARC P136 - SER2_TX   */
+       };
+
        /* On-module eMMC */
        pinctrl_usdhc1: usdhc1grp {
                fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK       0x158e>, /* SD1_CLK    */