arm/arm64: dts: marvell: Drop unused .dtsi

These .dtsi files are not included anywhere in the tree and can't be
tested.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Elad Nachman <enachman@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

diff --git a/arch/arm/boot/dts/marvell/armada-380.dtsi b/arch/arm/boot/dts/marvell/armada-380.dtsi
deleted file mode 100644 (file)
index e94f22b..0000000
--- a/arch/arm/boot/dts/marvell/armada-380.dtsi
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree Include file for Marvell Armada 380 SoC.
- *
- * Copyright (C) 2014 Marvell
- *
- * Lior Amsalem <alior@marvell.com>
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- */
-
-#include "armada-38x.dtsi"
-
-/ {
-       model = "Marvell Armada 380 family SoC";
-       compatible = "marvell,armada380";
-
-       cpus {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               enable-method = "marvell,armada-380-smp";
-
-               cpu@0 {
-                       device_type = "cpu";
-                       compatible = "arm,cortex-a9";
-                       reg = <0>;
-               };
-       };
-
-       soc {
-               internal-regs {
-                       pinctrl@18000 {
-                               compatible = "marvell,mv88f6810-pinctrl";
-                       };
-               };
-
-               pcie {
-                       compatible = "marvell,armada-370-pcie";
-                       status = "disabled";
-                       device_type = "pci";
-
-                       #address-cells = <3>;
-                       #size-cells = <2>;
-
-                       msi-parent = <&mpic>;
-                       bus-range = <0x00 0xff>;
-
-                       ranges =
-                              <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
-                               0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
-                               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
-                               0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
-                               0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
-                               0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
-                               0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
-                               0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
-                               0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
-                               0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */>;
-
-                       /* x1 port */
-                       pcie@1,0 {
-                               device_type = "pci";
-                               assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
-                               reg = <0x0800 0 0 0 0>;
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-                               interrupt-names = "intx";
-                               interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-                               #interrupt-cells = <1>;
-                               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
-                                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
-                               bus-range = <0x00 0xff>;
-                               interrupt-map-mask = <0 0 0 7>;
-                               interrupt-map = <0 0 0 1 &pcie1_intc 0>,
-                                               <0 0 0 2 &pcie1_intc 1>,
-                                               <0 0 0 3 &pcie1_intc 2>,
-                                               <0 0 0 4 &pcie1_intc 3>;
-                               marvell,pcie-port = <0>;
-                               marvell,pcie-lane = <0>;
-                               clocks = <&gateclk 8>;
-                               status = "disabled";
-
-                               pcie1_intc: interrupt-controller {
-                                       interrupt-controller;
-                                       #interrupt-cells = <1>;
-                               };
-                       };
-
-                       /* x1 port */
-                       pcie@2,0 {
-                               device_type = "pci";
-                               assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
-                               reg = <0x1000 0 0 0 0>;
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-                               interrupt-names = "intx";
-                               interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-                               #interrupt-cells = <1>;
-                               ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
-                                         0x81000000 0 0 0x81000000 0x2 0 1 0>;
-                               bus-range = <0x00 0xff>;
-                               interrupt-map-mask = <0 0 0 7>;
-                               interrupt-map = <0 0 0 1 &pcie2_intc 0>,
-                                               <0 0 0 2 &pcie2_intc 1>,
-                                               <0 0 0 3 &pcie2_intc 2>,
-                                               <0 0 0 4 &pcie2_intc 3>;
-                               marvell,pcie-port = <1>;
-                               marvell,pcie-lane = <0>;
-                               clocks = <&gateclk 5>;
-                               status = "disabled";
-
-                               pcie2_intc: interrupt-controller {
-                                       interrupt-controller;
-                                       #interrupt-cells = <1>;
-                               };
-                       };
-
-                       /* x1 port */
-                       pcie@3,0 {
-                               device_type = "pci";
-                               assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
-                               reg = <0x1800 0 0 0 0>;
-                               #address-cells = <3>;
-                               #size-cells = <2>;
-                               interrupt-names = "intx";
-                               interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
-                               #interrupt-cells = <1>;
-                               ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
-                                         0x81000000 0 0 0x81000000 0x3 0 1 0>;
-                               bus-range = <0x00 0xff>;
-                               interrupt-map-mask = <0 0 0 7>;
-                               interrupt-map = <0 0 0 1 &pcie3_intc 0>,
-                                               <0 0 0 2 &pcie3_intc 1>,
-                                               <0 0 0 3 &pcie3_intc 2>,
-                                               <0 0 0 4 &pcie3_intc 3>;
-                               marvell,pcie-port = <2>;
-                               marvell,pcie-lane = <0>;
-                               clocks = <&gateclk 6>;
-                               status = "disabled";
-
-                               pcie3_intc: interrupt-controller {
-                                       interrupt-controller;
-                                       #interrupt-cells = <1>;
-                               };
-                       };
-               };
-       };
-};

diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
deleted file mode 100644 (file)
index b6fc188..0000000
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ /dev/null
@@ -1,20 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
- * two CP110.
- */
-
-#include "armada-ap806-dual.dtsi"
-#include "armada-80x0.dtsi"
-
-/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
- * in CP master is not connected (by package) to the oscillator. So
- * disable it. However, the RTC clock in CP slave is connected to the
- * oscillator so this one is let enabled.
- */
-
-&cp0_rtc {
-       status = "disabled";
-};

diff --git a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
deleted file mode 100644 (file)
index 028496e..0000000
--- a/arch/arm64/boot/dts/marvell/cn9130-db-comexpress.dtsi
+++ /dev/null
@@ -1,96 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (C) 2023 Marvell International Ltd.
- *
- * Device tree for the CN9130-DB Com Express CPU module board.
- */
-
-#include "cn9130-db.dtsi"
-
-/ {
-       model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board";
-       compatible = "marvell,cn9130-cpu-module", "marvell,cn9130",
-                    "marvell,armada-ap807-quad", "marvell,armada-ap807";
-
-};
-
-&ap0_reg_sd_vccq {
-       regulator-max-microvolt = <1800000>;
-       states = <1800000 0x1 1800000 0x0>;
-       /delete-property/ gpios;
-};
-
-&cp0_reg_usb3_vbus0 {
-       /delete-property/ gpio;
-};
-
-&cp0_reg_usb3_vbus1 {
-       /delete-property/ gpio;
-};
-
-&cp0_reg_sd_vcc {
-       status = "disabled";
-};
-
-&cp0_reg_sd_vccq {
-       status = "disabled";
-};
-
-&cp0_sdhci0 {
-       status = "disabled";
-};
-
-&cp0_eth0 {
-       status = "disabled";
-};
-
-&cp0_eth1 {
-       status = "okay";
-       phy = <&phy0>;
-       phy-mode = "rgmii-id";
-};
-
-&cp0_eth2 {
-       status = "disabled";
-};
-
-&cp0_mdio {
-       status = "okay";
-       pinctrl-0 = <&cp0_ge_mdio_pins>;
-       phy0: ethernet-phy@0 {
-               status = "okay";
-       };
-};
-
-&cp0_syscon0 {
-       cp0_pinctrl: pinctrl {
-               compatible = "marvell,cp115-standalone-pinctrl";
-
-               cp0_ge_mdio_pins: ge-mdio-pins {
-                       marvell,pins = "mpp40", "mpp41";
-                       marvell,function = "ge";
-               };
-       };
-};
-
-&cp0_sdhci0 {
-       status = "disabled";
-};
-
-&cp0_spi1 {
-       status = "okay";
-};
-
-&cp0_usb3_0 {
-       status = "okay";
-       usb-phy = <&cp0_usb3_0_phy0>;
-       phy-names = "usb";
-       /delete-property/ phys;
-};
-
-&cp0_usb3_1 {
-       status = "okay";
-       usb-phy = <&cp0_usb3_0_phy1>;
-       phy-names = "usb";
-       /delete-property/ phys;
-};