net: stmmac: dwmac-loongson: Set clk_csr_i to 100-150MHz

Current clk_csr_i setting of Loongson STMMAC (including LS7A1000/2000
and LS2K1000/2000/3000) are copy & paste from other drivers. In fact,
Loongson STMMAC use 125MHz clocks and need 62 freq division to within
2.5MHz, meeting most PHY MDC requirement. So fix by setting clk_csr_i
to 100-150MHz, otherwise some PHYs may link fail.

Cc: stable@vger.kernel.org
Fixes: 30bba69d7db40e7 ("stmmac: pci: Add dwmac support for Loongson")
Signed-off-by: Hongliang Wang <wanghongliang@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Link: https://patch.msgid.link/20260203062901.2158236-1-chenhuacai@loongson.cn
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
index 107a7c84ace803f08dc739db9cc4afd9901ad22c..c05e3e7a539cfe92e943574ca5c9b660e7971267 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
@@ -91,8 +91,8 @@ static void loongson_default_data(struct pci_dev *pdev,
        /* Get bus_id, this can be overwritten later */
        plat->bus_id = pci_dev_id(pdev);
 
-       /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
-       plat->clk_csr = STMMAC_CSR_20_35M;
+       /* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */
+       plat->clk_csr = STMMAC_CSR_100_150M;
        plat->core_type = DWMAC_CORE_GMAC;
        plat->force_sf_dma_mode = 1;