Adjust rtx_cost for DF/SFmode AND/IOR/XOR/ANDN operations.

They should have same cost as vector mode since both generate
pand/pandn/pxor/por instruction.

gcc/ChangeLog:

	* config/i386/i386.cc (ix86_rtx_costs): Adjust rtx_cost for
	DF/SFmode AND/IOR/XOR/ANDN operations.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr110170-2.c: New test.

diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc
index a9da66da072f2c380bb0b62a82804ab3a2a38001..0cc4b329b9966ba4fb1ccdd3687fc361bcb569ac 100644 (file)
--- a/gcc/config/i386/i386.cc
+++ b/gcc/config/i386/i386.cc
@@ -21179,7 +21179,8 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
       return false;
 
     case IOR:
-      if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
+      if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+         || SSE_FLOAT_MODE_P (mode))
        {
          /* (ior (not ...) ...) can be a single insn in AVX512.  */
          if (GET_CODE (XEXP (x, 0)) == NOT && TARGET_AVX512F
@@ -21206,7 +21207,8 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
       return false;
 
     case XOR:
-      if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
+      if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+         || SSE_FLOAT_MODE_P (mode))
        *total = ix86_vec_cost (mode, cost->sse_op);
       else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
        *total = cost->add * 2;
@@ -21220,7 +21222,8 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
          *total = cost->lea;
          return true;
        }
-      else if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
+      else if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
+              || SSE_FLOAT_MODE_P (mode))
        {
          /* pandn is a single instruction.  */
          if (GET_CODE (XEXP (x, 0)) == NOT)

diff --git a/gcc/testsuite/gcc.target/i386/pr110170-2.c b/gcc/testsuite/gcc.target/i386/pr110170-2.c
new file mode 100644 (file)
index 0000000..d43e322
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr110170-2.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-msse2 -O2 -mfpmath=sse" } */
+/* { dg-final { scan-assembler-not "comi" } }  */
+
+double
+foo (double* a, double* b, double c, double d)
+{
+  return *a < *b ? c : d;
+}
+
+float
+foo1 (float* a, float* b, float c, float d)
+{
+  return *a < *b ? c : d;
+}
+