Move the decoding of SFENCE out of the SSE only part of disInstr as it

exists on Athlon's that have MMXEXT support and those don't have SSE state
so won't decode it where it was.

CCMAIL: 85947-done@bugs.kde.org

git-svn-id: svn://svn.valgrind.org/valgrind/trunk@2524

diff --git a/coregrind/vg_to_ucode.c b/coregrind/vg_to_ucode.c
index 4f5bf95f52c39a7407001a95a5bbc91cf5f0c03c..f05e3f32af1f0ca2634aec658b66b4ce4b5e1df4 100644 (file)
--- a/coregrind/vg_to_ucode.c
+++ b/coregrind/vg_to_ucode.c
@@ -3984,17 +3984,17 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
       goto decode_success;
    }
 
-   /* LFENCE/MFENCE/SFENCE -- flush pending operations to memory */
+   /* LFENCE/MFENCE -- flush pending operations to memory */
    if (insn[0] == 0x0F && insn[1] == 0xAE
        && (epartIsReg(insn[2]))
-       && (gregOfRM(insn[2]) >= 5 && gregOfRM(insn[2]) <= 7))
+       && (gregOfRM(insn[2]) >= 5 && gregOfRM(insn[2]) <= 6))
    {
       vg_assert(sz == 4);
       eip += 3;
       uInstr2(cb, SSE3, 0,  /* ignore sz for internal ops */
                   Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
                   Lit16, (UShort)insn[2] );
-      DIP("sfence\n");
+      DIP("%sfence\n", gregOfRM(insn[2]) == 5 ? "l" : "m");
       goto decode_success;
    }
 
@@ -6852,6 +6852,22 @@ static Addr disInstr ( UCodeBlock* cb, Addr eip, Bool* isEnd )
          }
          break;
 
+      case 0xAE: /* SFENCE */
+         vg_assert(sz == 4);
+         modrm = getUChar(eip);
+         if (!epartIsReg(modrm)) {
+            goto decode_failure;
+         }
+         if (gregOfRM(modrm) != 7) {
+            goto decode_failure;
+         }
+         eip += lengthAMode(eip);
+         uInstr2(cb, SSE3, 0,  /* ignore sz for internal ops */
+                     Lit16, (((UShort)0x0F) << 8) | (UShort)0xAE,
+                     Lit16, (UShort)modrm );
+         DIP("sfence\n");
+         break;
+
       case 0x71: case 0x72: case 0x73: {
          /* (sz==4): PSLL/PSRA/PSRL mmxreg by imm8 */
          /* (sz==2): PSLL/PSRA/PSRL xmmreg by imm8 */