rs6000: wz -> d+p7

	* config/rs6000/constraints.md (define_register_constraint "wz"):
	Delete.
	* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
	RS6000_CONSTRAINT_wz.
	* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
	(rs6000_init_hard_regno_mode_ok): Adjust.
	* config/rs6000/rs6000.md: Replace "wz" constraint by "d" with "p7".
	* doc/md.texi (Machine Constraints): Adjust.

From-SVN: r271488

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ec57efc278ed91a7e451f9f3a4e3bba7a98ac9a2..592cecd529e07ec5696ae89bf8a63c0921d81ce3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2019-05-21  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/constraints.md (define_register_constraint "wz"):
+       Delete.
+       * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
+       RS6000_CONSTRAINT_wz.
+       * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
+       (rs6000_init_hard_regno_mode_ok): Adjust.
+       * config/rs6000/rs6000.md: Replace "wz" constraint by "d" with "p7".
+       * doc/md.texi (Machine Constraints): Adjust.
+
 2019-05-21  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/constraints.md (define_register_constraint "wl"):

diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 802ce44ff20b764992a34fb8c2e121a701739696..fd8be343f09be866c43d5b553459ce3cdf3afec5 100644 (file)
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -103,9 +103,6 @@
 (define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
   "Floating point register if the STFIWX instruction is enabled or NO_REGS.")
 
-(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
-  "Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
-
 (define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]"
   "BASE_REGS if 64-bit instructions are enabled or NO_REGS.")
 

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 244fb5c7362269b5562841a5797a2b035b5b1148..97378c4139dc392a181460f08420748c6af913e8 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -2521,7 +2521,6 @@ rs6000_debug_reg_global (void)
           "wv reg_class = %s\n"
           "ww reg_class = %s\n"
           "wx reg_class = %s\n"
-          "wz reg_class = %s\n"
           "wA reg_class = %s\n"
           "\n",
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
@@ -2541,7 +2540,6 @@ rs6000_debug_reg_global (void)
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
-          reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
           reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
 
   nl = "\n";
@@ -3160,8 +3158,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
        wt - VSX register for TImode in VSX registers.
        wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
        ww - Register class to do SF conversions in with VSX operations.
-       wx - Float register if we can do 32-bit int stores.
-       wz - Float register if we can do 32-bit unsigned int loads.  */
+       wx - Float register if we can do 32-bit int stores.  */
 
   if (TARGET_HARD_FLOAT)
     {
@@ -3202,9 +3199,6 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
   if (TARGET_STFIWX)
     rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS;     /* DImode  */
 
-  if (TARGET_LFIWZX)
-    rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS;     /* DImode  */
-
   if (TARGET_FLOAT128_TYPE)
     {
       rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS;     /* KFmode  */

diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 176f34d94d463a740668bdcea396f91009f184dc..fb94901249dfefe52da26899c33a5ea588b44eb2 100644 (file)
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1262,7 +1262,6 @@ enum r6000_reg_class_enum {
   RS6000_CONSTRAINT_wv,                /* Altivec register for double load/stores.  */
   RS6000_CONSTRAINT_ww,                /* FP or VSX register for vsx float ops.  */
   RS6000_CONSTRAINT_wx,                /* FPR register for STFIWX */
-  RS6000_CONSTRAINT_wz,                /* FPR register for LFIWZX */
   RS6000_CONSTRAINT_wA,                /* BASE_REGS if 64-bit.  */
   RS6000_CONSTRAINT_MAX
 };

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 454518e7e043efd7f75719ea1559c7c709cd2a39..32c41f37127d9287a577dd67b67047612bcc0b82 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -834,7 +834,7 @@
 
 
 (define_insn "zero_extendsi<mode>2"
-  [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,wz,wa,wi,r,wa")
+  [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wi,r,wa")
        (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))]
   ""
   "@
@@ -846,7 +846,7 @@
    mfvsrwz %0,%x1
    xxextractuw %x0,%x1,4"
   [(set_attr "type" "load,shift,fpload,fpload,mffgpr,mftgpr,vecexts")
-   (set_attr "isa" "*,*,*,p8v,p8v,p8v,p9v")])
+   (set_attr "isa" "*,*,p7,p8v,p8v,p8v,p9v")])
 
 (define_insn_and_split "*zero_extendsi<mode>2_dot"
   [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
@@ -7349,7 +7349,7 @@
 ;;     FMR          MR         MT%0       MF%1       NOP
 (define_insn "movsd_hardfloat"
   [(set (match_operand:SD 0 "nonimmediate_operand"
-        "=!r,       wz,        m,         Z,         ?d,        ?r,
+        "=!r,       d,         m,         Z,         ?d,        ?r,
          f,         !r,        *c*l,      !r,        *h")
        (match_operand:SD 1 "input_operand"
         "m,         Z,         r,         wx,        r,         d,
@@ -7373,7 +7373,7 @@
        "load,       fpload,    store,     fpstore,   mffgpr,    mftgpr,
         fpsimple,   *,         mtjmpr,    mfjmpr,    *")
    (set_attr "isa"
-       "*,          *,         *,         *,         p8v,       p8v,
+       "*,          p7,        *,         *,         p8v,       p8v,
         *,          *,         *,         *,         *")])
 
 ;;     MR           MT%0       MF%0       LWZ        STW        LI

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 2d531cc5a1535a5af58c9ae42a77bf417a6ecad3..db9c210edb87dbcf9fb102b41235bfca59c8c047 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3289,9 +3289,6 @@ FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
 @item wx
 Floating point register if the STFIWX instruction is enabled or NO_REGS.
 
-@item wz
-Floating point register if the LFIWZX instruction is enabled or NO_REGS.
-
 @item wA
 Address base register if 64-bit instructions are enabled or NO_REGS.