]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclk
authorKaustabh Chakraborty <kauschluss@disroot.org>
Sat, 8 Feb 2025 18:59:30 +0000 (00:29 +0530)
committerVinod Koul <vkoul@kernel.org>
Mon, 10 Feb 2025 16:57:15 +0000 (22:27 +0530)
In exynos5_usbdrd_{pipe3,utmi}_set_refclk(), the masks
PHYCLKRST_MPLL_MULTIPLIER_MASK and PHYCLKRST_SSC_REFCLKSEL_MASK are not
inverted when applied to the register values. Fix it.

Cc: stable@vger.kernel.org
Fixes: 59025887fb08 ("phy: Add new Exynos5 USB 3.0 PHY driver")
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Anand Moon <linux.amoon@gmail.com>
Link: https://lore.kernel.org/r/20250209-exynos5-usbdrd-masks-v1-1-4f7f83f323d7@disroot.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/samsung/phy-exynos5-usbdrd.c

index c421b495eb0fe4396d76f8c9d7c198ad7cd08869..4a108fdab118c0edd76bd88dc9dbf6a498e064b3 100644 (file)
@@ -488,9 +488,9 @@ exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
        reg |=  PHYCLKRST_REFCLKSEL_EXT_REFCLK;
 
        /* FSEL settings corresponding to reference clock */
-       reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
-               PHYCLKRST_MPLL_MULTIPLIER_MASK |
-               PHYCLKRST_SSC_REFCLKSEL_MASK;
+       reg &= ~(PHYCLKRST_FSEL_PIPE_MASK |
+                PHYCLKRST_MPLL_MULTIPLIER_MASK |
+                PHYCLKRST_SSC_REFCLKSEL_MASK);
        switch (phy_drd->extrefclk) {
        case EXYNOS5_FSEL_50MHZ:
                reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
@@ -532,9 +532,9 @@ exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
        reg &= ~PHYCLKRST_REFCLKSEL_MASK;
        reg |=  PHYCLKRST_REFCLKSEL_EXT_REFCLK;
 
-       reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
-               PHYCLKRST_MPLL_MULTIPLIER_MASK |
-               PHYCLKRST_SSC_REFCLKSEL_MASK;
+       reg &= ~(PHYCLKRST_FSEL_UTMI_MASK |
+                PHYCLKRST_MPLL_MULTIPLIER_MASK |
+                PHYCLKRST_SSC_REFCLKSEL_MASK);
        reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
 
        return reg;