riscv: dts: spacemit: enable QSPI for OrangePi RV2

Enable the QSPI controller and the XM25QU128C SPI NOR flash on the
OrangePi RV2 board. Add a flash partition layout from vendor UBoot.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Link: https://patch.msgid.link/20260516080030.1736836-1-amadeus@jmu.edu.cn
Signed-off-by: Yixun Lan <dlan@kernel.org>

diff --git a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
index bd40bc9011e298fcba5f66de1625c75d7fa659c6..7c49bce427f307a51efb7426662492de784660e0 100644 (file)
--- a/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-orangepi-rv2.dts
@@ -290,6 +290,51 @@
        status = "okay";
 };
 
+&qspi {
+       pinctrl-names = "default";
+       pinctrl-0 = <&qspi_cfg>;
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <26500000>;
+               spi-rx-bus-width = <4>;
+               spi-tx-bus-width = <4>;
+               vcc-supply = <&buck3_1v8>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       bootinfo@0 {
+                               reg = <0x00000 0x010000>;
+                       };
+
+                       private@10000 {
+                               reg = <0x10000 0x010000>;
+                       };
+
+                       fsbl@20000 {
+                               reg = <0x20000 0x040000>;
+                       };
+
+                       env@60000 {
+                               reg = <0x60000 0x010000>;
+                       };
+
+                       opensbi@70000 {
+                               reg = <0x70000 0x030000>;
+                       };
+
+                       uboot@a0000 {
+                               reg = <0xa0000 0x760000>;
+                       };
+               };
+       };
+};
+
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_2_cfg>;