[AArch64] Fix PR87511

As mentioned in PR87511, the shift used in aarch64_mask_and_shift_for_ubfiz_p
should be evaluated as a HOST_WIDE_INT rather than int.

Backported from mainline

    gcc/
	PR target/87511
	* config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
	Use HOST_WIDE_INT_1U for shift.

    testsuite/
	PR target/87511
	* gcc.target/aarch64/pr87511.c: Add new test.

From-SVN: r265195

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8c9c434fd4876c9778a92eaf3472fa2cb4379bc6..88a9ba475eb9889f53ba3bc7f40bb75698333491 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2018-10-16  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       Backported from mainline
+       PR target/87511
+       * config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
+       Use HOST_WIDE_INT_1U for shift.
+
 2018-10-12  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from mainline

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 3a29ea8f47c9f262f50c86b9f5dda87db1f76670..4e94be3b0b4d3633daea2e55260ba2d9e5449a3c 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -6536,7 +6536,8 @@ aarch64_mask_and_shift_for_ubfiz_p (machine_mode mode, rtx mask, rtx shft_amnt)
   return CONST_INT_P (mask) && CONST_INT_P (shft_amnt)
         && INTVAL (shft_amnt) < GET_MODE_BITSIZE (mode)
         && exact_log2 ((INTVAL (mask) >> INTVAL (shft_amnt)) + 1) >= 0
-        && (INTVAL (mask) & ((1 << INTVAL (shft_amnt)) - 1)) == 0;
+        && (INTVAL (mask)
+            & ((HOST_WIDE_INT_1U << INTVAL (shft_amnt)) - 1)) == 0;
 }
 
 /* Calculate the cost of calculating X, storing it in *COST.  Result

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7f82d57e5cea126e02ff7016f3702423dceeee0e..188615a3347b93c53925d72901ffee1990756340 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-16  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       Backported from mainline
+       PR target/87511
+       * gcc.target/aarch64/pr87511.c: Add new test.
+
 2018-10-12  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from mainline

diff --git a/gcc/testsuite/gcc.target/aarch64/pr87511.c b/gcc/testsuite/gcc.target/aarch64/pr87511.c
new file mode 100644 (file)
index 0000000..9806470
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr87511.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os" } */
+
+int a, d;
+struct {
+  signed f5 : 26;
+  signed f6 : 12;
+} b;
+signed char c;
+void fn1() {
+  signed char *e = &c;
+  d = a * 10;
+  *e = d;
+  b.f6 = c;
+  b.f5 = 8 <= 3;
+}