perf/amd/ibs: Add new MSRs and CPUID bits definitions

IBS on upcoming microarch introduced two new control MSRs and couple of
new features. Define macros for them.

New capabilities:

 o IBS_CAPS_DIS: Alternate Fetch and Op IBS disable bits
 o IBS_CAPS_FETCHLAT: Fetch Latency filter
 o IBS_CAPS_BIT63_FILTER: Virtual address bit 63 based filters for Fetch
   and Op
 o IBS_CAPS_STRMST_RMTSOCKET: Streaming store filter and indicator,
   remote socket indicator

New control MSRs for above features:

 o MSR_AMD64_IBSFETCHCTL2
 o MSR_AMD64_IBSOPCTL2

Also do cosmetic alignment changes.

Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Link: https://patch.msgid.link/20260216042530.1546-3-ravi.bangoria@amd.com

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index da5275d8eda63e196ce2604a679aecfc7b2870d6..e25434d21159eb552b1fe18997eb7f87abdb2798 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -698,6 +698,8 @@
 #define MSR_AMD64_IBSBRTARGET          0xc001103b
 #define MSR_AMD64_ICIBSEXTDCTL         0xc001103c
 #define MSR_AMD64_IBSOPDATA4           0xc001103d
+#define MSR_AMD64_IBSOPCTL2            0xc001103e
+#define MSR_AMD64_IBSFETCHCTL2         0xc001103f
 #define MSR_AMD64_IBS_REG_COUNT_MAX    8 /* includes MSR_AMD64_IBSBRTARGET */
 #define MSR_AMD64_SVM_AVIC_DOORBELL    0xc001011b
 #define MSR_AMD64_VM_PAGE_FLUSH                0xc001011e

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 67ecb989408edbe19db3227ecfaf19127762aabf..752cb319d5eaba2c60fbc846bf432c2e673718a7 100644 (file)
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -643,6 +643,10 @@ struct arch_pebs_cntr_header {
 #define IBS_CAPS_OPDATA4               (1U<<10)
 #define IBS_CAPS_ZEN4                  (1U<<11)
 #define IBS_CAPS_OPLDLAT               (1U<<12)
+#define IBS_CAPS_DIS                   (1U<<13)
+#define IBS_CAPS_FETCHLAT              (1U<<14)
+#define IBS_CAPS_BIT63_FILTER          (1U<<15)
+#define IBS_CAPS_STRMST_RMTSOCKET      (1U<<16)
 #define IBS_CAPS_OPDTLBPGSIZE          (1U<<19)
 
 #define IBS_CAPS_DEFAULT               (IBS_CAPS_AVAIL         \
@@ -657,32 +661,44 @@ struct arch_pebs_cntr_header {
 #define IBSCTL_LVT_OFFSET_MASK         0x0F
 
 /* IBS fetch bits/masks */
-#define IBS_FETCH_L3MISSONLY   (1ULL<<59)
-#define IBS_FETCH_RAND_EN      (1ULL<<57)
-#define IBS_FETCH_VAL          (1ULL<<49)
-#define IBS_FETCH_ENABLE       (1ULL<<48)
-#define IBS_FETCH_CNT          0xFFFF0000ULL
-#define IBS_FETCH_MAX_CNT      0x0000FFFFULL
+#define IBS_FETCH_L3MISSONLY                 (1ULL << 59)
+#define IBS_FETCH_RAND_EN                    (1ULL << 57)
+#define IBS_FETCH_VAL                        (1ULL << 49)
+#define IBS_FETCH_ENABLE                     (1ULL << 48)
+#define IBS_FETCH_CNT                       0xFFFF0000ULL
+#define IBS_FETCH_MAX_CNT                   0x0000FFFFULL
+
+#define IBS_FETCH_2_DIS                              (1ULL <<  0)
+#define IBS_FETCH_2_FETCHLAT_FILTER        (0xFULL <<  1)
+#define IBS_FETCH_2_FETCHLAT_FILTER_SHIFT             (1)
+#define IBS_FETCH_2_EXCL_RIP_63_EQ_1         (1ULL <<  5)
+#define IBS_FETCH_2_EXCL_RIP_63_EQ_0         (1ULL <<  6)
 
 /*
  * IBS op bits/masks
  * The lower 7 bits of the current count are random bits
  * preloaded by hardware and ignored in software
  */
-#define IBS_OP_LDLAT_EN                (1ULL<<63)
-#define IBS_OP_LDLAT_THRSH     (0xFULL<<59)
-#define IBS_OP_LDLAT_THRSH_SHIFT       (59)
-#define IBS_OP_CUR_CNT         (0xFFF80ULL<<32)
-#define IBS_OP_CUR_CNT_RAND    (0x0007FULL<<32)
-#define IBS_OP_CUR_CNT_EXT_MASK        (0x7FULL<<52)
-#define IBS_OP_CNT_CTL         (1ULL<<19)
-#define IBS_OP_VAL             (1ULL<<18)
-#define IBS_OP_ENABLE          (1ULL<<17)
-#define IBS_OP_L3MISSONLY      (1ULL<<16)
-#define IBS_OP_MAX_CNT         0x0000FFFFULL
-#define IBS_OP_MAX_CNT_EXT     0x007FFFFFULL   /* not a register bit mask */
-#define IBS_OP_MAX_CNT_EXT_MASK        (0x7FULL<<20)   /* separate upper 7 bits */
-#define IBS_RIP_INVALID                (1ULL<<38)
+#define IBS_OP_LDLAT_EN                              (1ULL << 63)
+#define IBS_OP_LDLAT_THRSH                 (0xFULL << 59)
+#define IBS_OP_LDLAT_THRSH_SHIFT                     (59)
+#define IBS_OP_CUR_CNT                 (0xFFF80ULL << 32)
+#define IBS_OP_CUR_CNT_RAND            (0x0007FULL << 32)
+#define IBS_OP_CUR_CNT_EXT_MASK                   (0x7FULL << 52)
+#define IBS_OP_CNT_CTL                       (1ULL << 19)
+#define IBS_OP_VAL                           (1ULL << 18)
+#define IBS_OP_ENABLE                        (1ULL << 17)
+#define IBS_OP_L3MISSONLY                    (1ULL << 16)
+#define IBS_OP_MAX_CNT                      0x0000FFFFULL
+#define IBS_OP_MAX_CNT_EXT                  0x007FFFFFULL      /* not a register bit mask */
+#define IBS_OP_MAX_CNT_EXT_MASK                   (0x7FULL << 20)      /* separate upper 7 bits */
+#define IBS_RIP_INVALID                              (1ULL << 38)
+
+#define IBS_OP_2_DIS                         (1ULL <<  0)
+#define IBS_OP_2_EXCL_RIP_63_EQ_0            (1ULL <<  1)
+#define IBS_OP_2_EXCL_RIP_63_EQ_1            (1ULL <<  2)
+#define IBS_OP_2_STRM_ST_FILTER                      (1ULL <<  3)
+#define IBS_OP_2_STRM_ST_FILTER_SHIFT                 (3)
 
 #ifdef CONFIG_X86_LOCAL_APIC
 extern u32 get_ibs_caps(void);