RISC-V: Remove FRM for vfncvt.rod instruction

Apparently, vfncvt.rod rounding mode is encoded, so we don't need FRM.

gcc/ChangeLog:

	* config/riscv/vector.md: Remove FRM.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cd696da5d8987e60ed36f24d9e916ded31ca9081..60f052bcec9228221aed6071d14f18b955d7cf21 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7290,10 +7290,8 @@
             (match_operand 5 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
             (match_operand 6 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
             (match_operand 7 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
-            (match_operand 8 "const_int_operand"                  "  i,  i,  i,  i,    i,    i")
             (reg:SI VL_REGNUM)
-            (reg:SI VTYPE_REGNUM)
-            (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
+            (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
          (unspec:<V_DOUBLE_TRUNC>
            [(float_truncate:<V_DOUBLE_TRUNC>
               (match_operand:VWEXTF 3 "register_operand"          "  0,  0,  0,  0,   vr,   vr"))] UNSPEC_ROD)