]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/edram: extract i915_edram.[ch] for edram detection
authorJani Nikula <jani.nikula@intel.com>
Wed, 19 Nov 2025 18:52:40 +0000 (20:52 +0200)
committerJani Nikula <jani.nikula@intel.com>
Fri, 21 Nov 2025 10:11:14 +0000 (12:11 +0200)
While edram detection ostensibly belongs with the rest of the dram stuff
in soc/intel_dram.c, it's only required by i915 core, not
display. Extract it to a separate i915_edram.[ch] file.

This allows us to drop the edram_size_mb member from struct xe_device.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/612edb7b70755655fbf193ba8af1c539fb93b698.1763578288.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/Makefile
drivers/gpu/drm/i915/i915_driver.c
drivers/gpu/drm/i915/i915_edram.c [new file with mode: 0644]
drivers/gpu/drm/i915/i915_edram.h [new file with mode: 0644]
drivers/gpu/drm/i915/soc/intel_dram.c
drivers/gpu/drm/i915/soc/intel_dram.h
drivers/gpu/drm/xe/xe_device_types.h

index 477278aee8314fb8bb75a1a1e2574d62bfeee11a..4e263ab520c1b8cc4c057dc93d318da872e39c92 100644 (file)
@@ -27,6 +27,7 @@ i915-y += \
        i915_config.o \
        i915_driver.o \
        i915_drm_client.o \
+       i915_edram.o \
        i915_getparam.o \
        i915_ioctl.o \
        i915_irq.o \
index 7c60b687393401fe51431a971b6eb1ad1083dde9..44a17ffc3058c9ec72c2725073ee771915e23b8b 100644 (file)
@@ -94,6 +94,7 @@
 #include "i915_driver.h"
 #include "i915_drm_client.h"
 #include "i915_drv.h"
+#include "i915_edram.h"
 #include "i915_file_private.h"
 #include "i915_getparam.h"
 #include "i915_hwmon.h"
@@ -493,7 +494,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
        }
 
        /* needs to be done before ggtt probe */
-       intel_dram_edram_detect(dev_priv);
+       i915_edram_detect(dev_priv);
 
        ret = i915_set_dma_info(dev_priv);
        if (ret)
diff --git a/drivers/gpu/drm/i915/i915_edram.c b/drivers/gpu/drm/i915/i915_edram.c
new file mode 100644 (file)
index 0000000..5818ec3
--- /dev/null
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: MIT
+/* Copyright © 2025 Intel Corporation */
+
+#include <drm/drm_print.h>
+
+#include "i915_drv.h"
+#include "i915_edram.h"
+#include "i915_reg.h"
+
+static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
+{
+       static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
+       static const u8 sets[4] = { 1, 1, 2, 2 };
+
+       return EDRAM_NUM_BANKS(cap) *
+               ways[EDRAM_WAYS_IDX(cap)] *
+               sets[EDRAM_SETS_IDX(cap)];
+}
+
+void i915_edram_detect(struct drm_i915_private *i915)
+{
+       u32 edram_cap = 0;
+
+       if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
+               return;
+
+       edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);
+
+       /* NB: We can't write IDICR yet because we don't have gt funcs set up */
+
+       if (!(edram_cap & EDRAM_ENABLED))
+               return;
+
+       /*
+        * The needed capability bits for size calculation are not there with
+        * pre gen9 so return 128MB always.
+        */
+       if (GRAPHICS_VER(i915) < 9)
+               i915->edram_size_mb = 128;
+       else
+               i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
+
+       drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);
+}
diff --git a/drivers/gpu/drm/i915/i915_edram.h b/drivers/gpu/drm/i915/i915_edram.h
new file mode 100644 (file)
index 0000000..8319422
--- /dev/null
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2025 Intel Corporation */
+
+#ifndef __I915_DRAM_H__
+#define __I915_DRAM_H__
+
+struct drm_i915_private;
+
+void i915_edram_detect(struct drm_i915_private *i915);
+
+#endif /* __I915_DRAM_H__ */
index 739cfe48f6db16844aef6fc70207a09f235a7573..cfe96c3c1b1a4d012e9b7caebd4f97e9769998f1 100644 (file)
@@ -861,39 +861,3 @@ const struct dram_info *intel_dram_info(struct drm_device *drm)
 
        return i915->dram_info;
 }
-
-static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
-{
-       static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
-       static const u8 sets[4] = { 1, 1, 2, 2 };
-
-       return EDRAM_NUM_BANKS(cap) *
-               ways[EDRAM_WAYS_IDX(cap)] *
-               sets[EDRAM_SETS_IDX(cap)];
-}
-
-void intel_dram_edram_detect(struct drm_i915_private *i915)
-{
-       u32 edram_cap = 0;
-
-       if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
-               return;
-
-       edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP);
-
-       /* NB: We can't write IDICR yet because we don't have gt funcs set up */
-
-       if (!(edram_cap & EDRAM_ENABLED))
-               return;
-
-       /*
-        * The needed capability bits for size calculation are not there with
-        * pre gen9 so return 128MB always.
-        */
-       if (GRAPHICS_VER(i915) < 9)
-               i915->edram_size_mb = 128;
-       else
-               i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
-
-       drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);
-}
index 8475ee379daab8ea7787f97c41e46382aadc790b..58aaf2f91afe1c26da2783936b4aee49243ef0a5 100644 (file)
@@ -35,7 +35,6 @@ struct dram_info {
        bool has_16gb_dimms;
 };
 
-void intel_dram_edram_detect(struct drm_i915_private *i915);
 int intel_dram_detect(struct drm_i915_private *i915);
 unsigned int intel_fsb_freq(struct drm_i915_private *i915);
 unsigned int intel_mem_freq(struct drm_i915_private *i915);
index e772851c08e9a5aa4b47da165ffb0366db7819df..430ac085c22bf2b2b33c0152b39f366734575d27 100644 (file)
@@ -639,12 +639,6 @@ struct xe_device {
         */
        const struct dram_info *dram_info;
 
-       /*
-        * edram size in MB.
-        * Cannot be determined by PCIID. You must always read a register.
-        */
-       u32 edram_size_mb;
-
        struct intel_uncore {
                spinlock_t lock;
        } uncore;