RISC-V: Avoid unnecessary slideup in compress pattern of vec_perm

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (shuffle_compress_patterns): Avoid unnecessary slideup.

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 1ca3f1dc8df54f01c0ab6d9ddbc923e841cd8c06..8a548f5d1a27a8c879f141c161dba46329968877 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2647,7 +2647,8 @@ shuffle_compress_patterns (struct expand_vec_perm_d *d)
 
            For index = { 0, 2, 5, 6}, we need to slide op1 up before
            we apply compress approach.  */
-  bool need_slideup_p = maybe_ne (d->perm[vlen - 1], 2 * vec_len - 1);
+  bool need_slideup_p = maybe_ne (d->perm[vlen - 1], 2 * vec_len - 1)
+                       && !const_vec_duplicate_p (d->op1);
 
   /* If we leave it directly be handled by general gather,
      the code sequence will be: