drm/msm/a6xx: Retrieve gmu core range by index

Some GPUs like A612 doesn't use a named register range resource. This
is because the reg-name property is discouraged when there is just a
single resource.

To address this, retrieve the 'gmu' register range by its index. It is
always guaranteed to be at index 0.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/696673/
Message-ID: <20251231-qcs615-spin-2-v6-1-da87debf6883@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 5903cd891b495f20e521562358068c7eea6ae603..9662201cd2e9d075425ac98bfa7c60989d00337d 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2029,21 +2029,19 @@ static int cxpd_notifier_cb(struct notifier_block *nb,
        return 0;
 }
 
-static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
-               const char *name, resource_size_t *start)
+static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, resource_size_t *start)
 {
+       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        void __iomem *ret;
-       struct resource *res = platform_get_resource_byname(pdev,
-                       IORESOURCE_MEM, name);
 
        if (!res) {
-               DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
+               DRM_DEV_ERROR(&pdev->dev, "Unable to find the gmu core registers\n");
                return ERR_PTR(-EINVAL);
        }
 
        ret = ioremap(res->start, resource_size(res));
        if (!ret) {
-               DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
+               DRM_DEV_ERROR(&pdev->dev, "Unable to map the gmu core registers\n");
                return ERR_PTR(-EINVAL);
        }
 
@@ -2085,7 +2083,7 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
        gmu->nr_clocks = ret;
 
        /* Map the GMU registers */
-       gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
+       gmu->mmio = a6xx_gmu_get_mmio(pdev, &start);
        if (IS_ERR(gmu->mmio)) {
                ret = PTR_ERR(gmu->mmio);
                goto err_mmio;
@@ -2244,7 +2242,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
                goto err_memory;
 
        /* Map the GMU registers */
-       gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu", &start);
+       gmu->mmio = a6xx_gmu_get_mmio(pdev, &start);
        if (IS_ERR(gmu->mmio)) {
                ret = PTR_ERR(gmu->mmio);
                goto err_memory;