drm/amdgpu: Fix SHMEM alignment mode for GFX 12.1.0

Alignment mode in SHMEM config register is only a single bit
value on GFX 12.1.0 instead of 2 bits in previous asics.
Add a new enum and use the correct value of SHMEM alignment mode
when programming the SHMEM config register.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 3080aecc83414fb94a0a20e9a59b60640f1e9228..023a8a1114a338b987079ecd354609ad393c3b87 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -52,9 +52,10 @@
 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin");
 MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin");
 
+#define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0      0x00000001
 #define DEFAULT_SH_MEM_CONFIG \
        ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
-        (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
+        (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
         (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 
 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id);

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
index db7675c1498de8eecb6eb9cca39b39b6ceb2433f..e4ec7190fea144824df78917e3a4752cf3ec8609 100644 (file)
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
@@ -24,7 +24,7 @@
 
 #include "kfd_device_queue_manager.h"
 #include "gc/gc_12_1_0_sh_mask.h"
-#include "soc24_enum.h"
+#include "soc_v1_0_enum.h"
 
 static int update_qpd_v12_1(struct device_queue_manager *dqm,
                         struct qcm_process_device *qpd);

diff --git a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h
index 5a0963eaf3b9af7b342c586be76e0c9ca4a7ca7c..2a910785334db8ee71d47b224eb34eed1c348a2e 100644 (file)
--- a/drivers/gpu/drm/amd/include/soc_v1_0_enum.h
+++ b/drivers/gpu/drm/amd/include/soc_v1_0_enum.h
@@ -30,4 +30,9 @@ typedef enum MTYPE {
        MTYPE_UC                        = 0x00000003,
 } MTYPE;
 
+typedef enum SH_MEM_ALIGNMENT_MODE {
+       SH_MEM_ALIGNMENT_MODE_DWORD              = 0x00000000,
+       SH_MEM_ALIGNMENT_MODE_UNALIGNED          = 0x00000001,
+} SH_MEM_ALIGNMENT_MODE;
+
 #endif