]> git.ipfire.org Git - thirdparty/gcc.git/commitdiff
[PR target/118357] RISC-V: Disable fusing vsetvl instructions by VSETVL_VTYPE_CHANGE_...
authorJin Ma <jinma@linux.alibaba.com>
Sat, 18 Jan 2025 14:43:17 +0000 (07:43 -0700)
committerKito Cheng <kito.cheng@sifive.com>
Wed, 9 Apr 2025 14:03:06 +0000 (22:03 +0800)
In RVV 1.0, the instruction "vsetvli zero,zero,*" indicates that the
available vector length (avl) does not change. However, in XTheadVector,
this same instruction signifies that the avl should take the maximum value.
Consequently, when fusing vsetvl instructions, the optimization labeled
"VSETVL_VTYPE_CHANGE_ONLY" is disabled for XTheadVector.

PR target/118357

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc: Function change_vtype_only_p always
returns false for XTheadVector.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/xtheadvector/pr118357.c: New test.

gcc/config/riscv/riscv-vsetvl.cc
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c [new file with mode: 0644]

index 48ce757a6ee5b9847e04342b32f964c957028db1..62f48f0f077f9484dc5e3b0dbd8d29665fb1059b 100644 (file)
@@ -900,7 +900,8 @@ public:
   bool valid_p () const { return m_state == state_type::VALID; }
   bool unknown_p () const { return m_state == state_type::UNKNOWN; }
   bool empty_p () const { return m_state == state_type::EMPTY; }
-  bool change_vtype_only_p () const { return m_change_vtype_only; }
+  bool change_vtype_only_p () const { return m_change_vtype_only
+                                            && !TARGET_XTHEADVECTOR; }
 
   void set_valid () { m_state = state_type::VALID; }
   void set_unknown () { m_state = state_type::UNKNOWN; }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr118357.c
new file mode 100644 (file)
index 0000000..aebb0e3
--- /dev/null
@@ -0,0 +1,13 @@
+/* { dg-do compile { target { rv64 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -mabi=lp64d -O2" } */
+
+#include <riscv_vector.h>
+
+vfloat16m4_t foo (float *ptr, size_t vl)
+{
+  vfloat32m8_t _p = __riscv_vle32_v_f32m8 (ptr, vl);
+  vfloat16m4_t _half = __riscv_vfncvt_f_f_w_f16m4 (_p, vl);
+  return _half;
+}
+
+/* { dg-final { scan-assembler-not {th.vsetvli\tzero,zero} } }*/