ASoC: dt-bindings: qcom: add LPASS LPI MI2S dai ids

Add new dai ids entries for LPASS LPI MI2S and SENARY MI2S audio lines.

Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260402081118.348071-7-srinivas.kandagatla@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml
index 08c618e7e4281d46c520b26ea24225bddd0d5e8b..2b27d6c8f58f148d54e852a2871f6cd6b302aa9c 100644 (file)
--- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml
+++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml
@@ -126,13 +126,16 @@ patternProperties:
             reg:
               contains:
                 # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and
-                # QUINARY_MI2S_RX - QUINARY_MI2S_TX
+                # QUINARY_MI2S_RX - QUINARY_MI2S_TX and
+                # LPI_MI2S_RX_0 - SENARY_MI2S_TX
                 items:
                   oneOf:
                     - minimum: 16
                       maximum: 23
                     - minimum: 127
                       maximum: 128
+                    - minimum: 137
+                      maximum: 148
         then:
           required:
             - qcom,sd-lines

diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
index 6d1ce7f5da51c684c028287dfb0ed06bebcf1fda..45850f2d43425886423a53653120e932f6db20f4 100644 (file)
--- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
+++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
@@ -140,6 +140,18 @@
 #define DISPLAY_PORT_RX_6      134
 #define DISPLAY_PORT_RX_7      135
 #define USB_RX                 136
+#define LPI_MI2S_RX_0          137
+#define LPI_MI2S_TX_0          138
+#define LPI_MI2S_RX_1          139
+#define LPI_MI2S_TX_1          140
+#define LPI_MI2S_RX_2          141
+#define LPI_MI2S_TX_2          142
+#define LPI_MI2S_RX_3          143
+#define LPI_MI2S_TX_3          144
+#define LPI_MI2S_RX_4          145
+#define LPI_MI2S_TX_4          146
+#define SENARY_MI2S_RX         147
+#define SENARY_MI2S_TX         148
 
 #define LPASS_CLK_ID_PRI_MI2S_IBIT     1
 #define LPASS_CLK_ID_PRI_MI2S_EBIT     2