into their own file, memory.c.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14403
dist_noinst_SCRIPTS = filter_stderr
EXTRA_DIST = \
+ fp_and_simd.stdout.exp fp_and_simd.stderr.exp fp_and_simd.vgtest \
integer.stdout.exp integer.stderr.exp integer.vgtest \
- fp_and_simd.stdout.exp fp_and_simd.stderr.exp fp_and_simd.vgtest
+ memory.stdout.exp memory.stderr.exp memory.vgtest
check_PROGRAMS = \
allexec \
+ fp_and_simd \
integer \
- fp_and_simd
+ memory
AM_CFLAGS += @FLAG_M64@
AM_CXXFLAGS += @FLAG_M64@
#define False ((Bool)0)
#define True ((Bool)1)
-__attribute__((noinline))
-static void* memalign16(size_t szB)
-{
- void* x;
- x = memalign(16, szB);
- assert(x);
- assert(0 == ((16-1) & (unsigned long)x));
- return x;
-}
static inline UChar randUChar ( void )
{
return (seed >> 17) & 0xFF;
}
-static ULong randULong ( void )
-{
- Int i;
- ULong r = 0;
- for (i = 0; i < 8; i++) {
- r = (r << 8) | (ULong)(0xFF & randUChar());
- }
- return r;
-}
-
-
#define TESTINST1(instruction, RD, carryin) \
{ \
); \
}
-// Same as TESTINST2 except it doesn't print the RN value, since
-// that may differ between runs (it's a stack address). Also,
-// claim it trashes x28 so that can be used as scratch if needed.
-#define TESTINST2_hide2(instruction, RNval, RD, RN, carryin) \
-{ \
- ULong out; \
- ULong nzcv_out; \
- ULong nzcv_in = (carryin ? (1<<29) : 0); \
- __asm__ __volatile__( \
- "msr nzcv,%3;" \
- "mov " #RN ",%2;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,nzcv;" \
- : "=&r" (out), "=&r" (nzcv_out) \
- : "r" (RNval), "r" (nzcv_in) \
- : #RD, #RN, "cc", "memory", "x28" \
- ); \
- printf("%s :: rd %016llx rn (hidden), " \
- "cin %d, nzcv %08llx %c%c%c%c\n", \
- instruction, out, \
- carryin ? 1 : 0, \
- nzcv_out & 0xffff0000, \
- ((1<<31) & nzcv_out) ? 'N' : ' ', \
- ((1<<30) & nzcv_out) ? 'Z' : ' ', \
- ((1<<29) & nzcv_out) ? 'C' : ' ', \
- ((1<<28) & nzcv_out) ? 'V' : ' ' \
- ); \
-}
-
-#define TESTINST3_hide2and3(instruction, RMval, RNval, RD, RM, RN, carryin) \
-{ \
- ULong out; \
- ULong nzcv_out; \
- ULong nzcv_in = (carryin ? (1<<29) : 0); \
- __asm__ __volatile__( \
- "msr nzcv,%4;" \
- "mov " #RM ",%2;" \
- "mov " #RN ",%3;" \
- instruction ";" \
- "mov %0," #RD ";" \
- "mrs %1,nzcv;" \
- : "=&r" (out), "=&r" (nzcv_out) \
- : "r" (RMval), "r" (RNval), "r" (nzcv_in) \
- : #RD, #RM, #RN, "cc", "memory" \
- ); \
- printf("%s :: rd %016llx rm (hidden), rn (hidden), " \
- "cin %d, nzcv %08llx %c%c%c%c\n", \
- instruction, out, \
- carryin ? 1 : 0, \
- nzcv_out & 0xffff0000, \
- ((1<<31) & nzcv_out) ? 'N' : ' ', \
- ((1<<30) & nzcv_out) ? 'Z' : ' ', \
- ((1<<29) & nzcv_out) ? 'C' : ' ', \
- ((1<<28) & nzcv_out) ? 'V' : ' ' \
- ); \
-}
-
-
#define ALL5s 0x5555555555555555ULL
#define ALLas 0xAAAAAAAAAAAAAAAAULL
#define ALLfs 0xFFFFFFFFFFFFFFFFULL
-
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
} /* end of test_arith() */
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-
-static __attribute((noinline)) void test_memory ( void )
-{
-printf("Integer loads\n");
-
-unsigned char area[512];
-
-#define RESET \
- do { int i; for (i = 0; i < sizeof(area); i++) \
- area[i] = i | 0x80; \
- } while (0)
-
-#define AREA_MID (((ULong)(&area[(sizeof(area)/2)-1])) & (~(ULong)0xF))
-
-RESET;
-
-////////////////////////////////////////////////////////////////
-printf("LDR,STR (immediate, uimm12) (STR cases are MISSING)");
-TESTINST2_hide2("ldr x21, [x22, #24]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldr w21, [x22, #20]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrh w21, [x22, #44]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrb w21, [x22, #56]", AREA_MID, x21,x22,0);
-
-////////////////////////////////////////////////////////////////
-printf("LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)\n");
-TESTINST2_hide2("ldr x21, [x22], #-24", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldr x21, [x22, #-40]!", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldr x21, [x22, #-48]", AREA_MID, x21,x22,0);
-printf("LDUR,STUR (immediate, simm9): STR cases are MISSING");
-
-////////////////////////////////////////////////////////////////
-// TESTINST2_hide2 allows use of x28 as scratch
-printf("LDP,STP (immediate, simm7) (STR cases and wb check is MISSING)\n");
-
-TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
-
-TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
-
-////////////////////////////////////////////////////////////////
-// This is a bit tricky. We load the value from just before and
-// just after the actual instruction. Because TESTINSN2_hide2
-// generates two fixed insns either side of the test insn, these
-// should be constant and hence "safe" to check.
-
-printf("LDR (literal, int reg)\n");
-TESTINST2_hide2("xyzzy00: ldr x21, xyzzy00 - 8", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy01: ldr x21, xyzzy01 + 0", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy02: ldr x21, xyzzy02 + 8", AREA_MID, x21,x22,0);
-
-TESTINST2_hide2("xyzzy03: ldr x21, xyzzy03 - 4", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy04: ldr x21, xyzzy04 + 0", AREA_MID, x21,x22,0);
-TESTINST2_hide2("xyzzy05: ldr x21, xyzzy05 + 4", AREA_MID, x21,x22,0);
-
-////////////////////////////////////////////////////////////////
-printf("{LD,ST}R (integer register) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (uimm12)\n");
-TESTINST2_hide2("ldrsw x21, [x22, #24]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsh x21, [x22, #20]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsh w21, [x22, #44]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsb x21, [x22, #88]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsb w21, [x22, #56]", AREA_MID, x21,x22,0);
-
-////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n");
-TESTINST2_hide2("ldrsw x21, [x22, #-24]!", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsh x21, [x22, #-20]!", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsh w21, [x22, #-44]!", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsb x21, [x22, #-88]!", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsb w21, [x22, #-56]!", AREA_MID, x21,x22,0);
-
-TESTINST2_hide2("ldrsw x21, [x22], #-24", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsh x21, [x22], #-20", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsh w21, [x22], #-44", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsb x21, [x22], #-88", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsb w21, [x22], #-56", AREA_MID, x21,x22,0);
-
-////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (simm9, noUpd)\n");
-TESTINST2_hide2("ldrsw x21, [x22, #-24]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsh x21, [x22, #-20]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsh w21, [x22, #-44]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsb x21, [x22, #-88]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldrsb w21, [x22, #-56]", AREA_MID, x21,x22,0);
-
-////////////////////////////////////////////////////////////////
-printf("LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("{LD,ST}R (vector register) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (integer register, SX)\n");
-
-TESTINST3_hide2and3("ldrsw x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsw x21, [x22,x23, lsl #2]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #2]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0);
-
-TESTINST3_hide2and3("ldrsh x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh x21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
-
-TESTINST3_hide2and3("ldrsh w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh w21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
-
-TESTINST3_hide2and3("ldrsb x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb x21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
-
-TESTINST3_hide2and3("ldrsb w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb w21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
-TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
-
-////////////////////////////////////////////////////////////////
-printf("LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (single structure, no offset) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (single structure, post index) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LD{,A}X{R,RH,RB} (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("ST{,L}X{R,RH,RB} (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LDA{R,RH,RB}\n");
-TESTINST2_hide2("ldar x21, [x22]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldar w21, [x22]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldarh w21, [x22]", AREA_MID, x21,x22,0);
-TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0);
-
-////////////////////////////////////////////////////////////////
-printf("STL{R,RH,RB} (entirely MISSING)\n");
-
-} /* end of test_memory() */
-
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-////////////////////////////////////////////////////////////////
-
-static void show_block_xor ( UChar* block1, UChar* block2, Int n )
-{
- Int i;
- printf(" ");
- for (i = 0; i < n; i++) {
- if (i > 0 && 0 == (i & 15)) printf("\n ");
- if (0 == (i & 15)) printf("[%3d] ", i);
- UInt diff = 0xFF & (UInt)(block1[i] - block2[i]);
- if (diff == 0)
- printf(".. ");
- else
- printf("%02x ", diff);
- }
- printf("\n");
-}
-
-
-// In: rand:
-// memory area, xferred vec regs, xferred int regs,
-// caller spec:
-// addr reg1, addr reg2
-//
-// Out: memory area, xferred vec regs, xferred int regs, addr reg1, addr reg2
-//
-// INSN may mention the following regs as containing load/store data:
-// x13 x23 v17 v18 v19 v20
-// and
-// x5 as containing the base address
-// x6 as containing an offset, if required
-// A memory area is filled with random data, and x13, x23, v17, v18, v19, v20
-// are loaded with random data too. INSN is then executed, with
-// x5 set to the middle of the memory area + AREG1OFF, and x6 set to AREG2VAL.
-//
-// What is printed out: the XOR of the new and old versions of the
-// following:
-// the memory area
-// x13 x23 v17 v18 v19 v20
-// and the SUB of the new and old values of the following:
-// x5 x6
-// If the insn modifies its base register then (obviously) the x5 "new - old"
-// value will be nonzero.
-
-#define MEM_TEST(INSN, AREG1OFF, AREG2VAL) { \
- int i; \
- const int N = 256; \
- UChar* area = memalign16(N); \
- UChar area2[N]; \
- for (i = 0; i < N; i++) area[i] = area2[i] = randUChar(); \
- ULong block[12]; \
- /* 0:x13 1:x23 2:v17.d[0] 3:v17.d[1] 4:v18.d[0] 5:v18.d[1] */ \
- /* 6:v19.d[0] 7:v19.d[1] 8:v20.d[0] 9:v20.d[1] 10:x5 11:x6 */ \
- for (i = 0; i < 12; i++) block[i] = randULong(); \
- block[10] = (ULong)(&area[128]) + (Long)(Int)AREG1OFF; \
- block[11] = (Long)AREG2VAL; \
- ULong block2[12]; \
- for (i = 0; i < 12; i++) block2[i] = block[i]; \
- __asm__ __volatile__( \
- "ldr x13, [%0, #0] ; " \
- "ldr x23, [%0, #8] ; " \
- "ldr q17, [%0, #16] ; " \
- "ldr q18, [%0, #32] ; " \
- "ldr q19, [%0, #48] ; " \
- "ldr q20, [%0, #64] ; " \
- "ldr x5, [%0, #80] ; " \
- "ldr x6, [%0, #88] ; " \
- INSN " ; " \
- "str x13, [%0, #0] ; " \
- "str x23, [%0, #8] ; " \
- "str q17, [%0, #16] ; " \
- "str q18, [%0, #32] ; " \
- "str q19, [%0, #48] ; " \
- "str q20, [%0, #64] ; " \
- "str x5, [%0, #80] ; " \
- "str x6, [%0, #88] ; " \
- : : "r"(&block[0]) : "x5", "x6", "x13", "x23", \
- "v17", "v18", "v19", "v20", "memory", "cc" \
- ); \
- printf("%s with x5 = middle_of_block+%lld, x6=%lld\n", \
- INSN, (Long)AREG1OFF, (Long)AREG2VAL); \
- show_block_xor(&area2[0], area, 256); \
- printf(" %016llx x13 (xor, xfer intreg #1)\n", block[0] ^ block2[0]); \
- printf(" %016llx x23 (xor, xfer intreg #2)\n", block[1] ^ block2[1]); \
- printf(" %016llx v17.d[0] (xor, xfer vecreg #1)\n", block[2] ^ block2[2]); \
- printf(" %016llx v17.d[1] (xor, xfer vecreg #1)\n", block[3] ^ block2[3]); \
- printf(" %016llx v18.d[0] (xor, xfer vecreg #2)\n", block[4] ^ block2[4]); \
- printf(" %016llx v18.d[1] (xor, xfer vecreg #2)\n", block[5] ^ block2[5]); \
- printf(" %016llx v19.d[0] (xor, xfer vecreg #3)\n", block[6] ^ block2[6]); \
- printf(" %016llx v19.d[1] (xor, xfer vecreg #3)\n", block[7] ^ block2[7]); \
- printf(" %016llx v20.d[0] (xor, xfer vecreg #3)\n", block[8] ^ block2[8]); \
- printf(" %016llx v20.d[1] (xor, xfer vecreg #3)\n", block[9] ^ block2[9]); \
- printf(" %16lld x5 (sub, base reg)\n", block[10] - block2[10]); \
- printf(" %16lld x6 (sub, index reg)\n", block[11] - block2[11]); \
- printf("\n"); \
- free(area); \
- }
-
-static __attribute__((noinline)) void test_memory2 ( void )
-{
-////////////////////////////////////////////////////////////////
-printf("LDR,STR (immediate, uimm12)");
-MEM_TEST("ldr x13, [x5, #24]", -1, 0);
-MEM_TEST("ldr w13, [x5, #20]", 1, 0);
-MEM_TEST("ldrh w13, [x5, #44]", 2, 0);
-MEM_TEST("ldrb w13, [x5, #56]", 3, 0);
-MEM_TEST("str x13, [x5, #24]", -3, 0);
-MEM_TEST("str w13, [x5, #20]", 5, 0);
-MEM_TEST("strh w13, [x5, #44]", 6, 0);
-MEM_TEST("strb w13, [x5, #56]", 7, 0);
-
-////////////////////////////////////////////////////////////////
-printf("LDUR,STUR (immediate, simm9)\n");
-MEM_TEST("ldr x13, [x5], #-24", 0, 0);
-MEM_TEST("ldr x13, [x5, #-40]!", 0, 0);
-MEM_TEST("ldr x13, [x5, #-48]", 0, 0);
-MEM_TEST("str x13, [x5], #-24", 0, 0);
-MEM_TEST("str x13, [x5, #-40]!", 0, 0);
-MEM_TEST("str x13, [x5, #-48]", 0, 0);
-
-////////////////////////////////////////////////////////////////
-printf("LDP,STP (immediate, simm7)\n");
-MEM_TEST("ldp x13, x23, [x5], #-24", 0, 0);
-MEM_TEST("ldp x13, x23, [x5, #-40]!", 0, 0);
-MEM_TEST("ldp x13, x23, [x5, #-40]", 0, 0);
-MEM_TEST("stp x13, x23, [x5], #-24", 0, 0);
-MEM_TEST("stp x13, x23, [x5, #-40]!", 0, 0);
-MEM_TEST("stp x13, x23, [x5, #-40]", 0, 0);
-
-MEM_TEST("ldp w13, w23, [x5], #-24", 0, 0);
-MEM_TEST("ldp w13, w23, [x5, #-40]!", 0, 0);
-MEM_TEST("ldp w13, w23, [x5, #-40]", 0, 0);
-MEM_TEST("stp w13, w23, [x5], #-24", 0, 0);
-MEM_TEST("stp w13, w23, [x5, #-40]!", 0, 0);
-MEM_TEST("stp w13, w23, [x5, #-40]", 0, 0);
-
-////////////////////////////////////////////////////////////////
-printf("LDR (literal, int reg) (DONE ABOVE)\n");
-
-////////////////////////////////////////////////////////////////
-printf("{LD,ST}R (integer register) (entirely MISSING)\n");
-MEM_TEST("str x13, [x5, x6]", 12, -4);
-MEM_TEST("str x13, [x5, x6, lsl #3]", 12, -4);
-MEM_TEST("str x13, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("str x13, [x5, w6, uxtw #3]", 12, 4);
-MEM_TEST("str x13, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("str x13, [x5, w6, sxtw #3]", 12, -4);
-MEM_TEST("ldr x13, [x5, x6]", 12, -4);
-MEM_TEST("ldr x13, [x5, x6, lsl #3]", 12, -4);
-MEM_TEST("ldr x13, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldr x13, [x5, w6, uxtw #3]", 12, 4);
-MEM_TEST("ldr x13, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldr x13, [x5, w6, sxtw #3]", 12, -4);
-
-MEM_TEST("str w13, [x5, x6]", 12, -4);
-MEM_TEST("str w13, [x5, x6, lsl #2]", 12, -4);
-MEM_TEST("str w13, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("str w13, [x5, w6, uxtw #2]", 12, 4);
-MEM_TEST("str w13, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("str w13, [x5, w6, sxtw #2]", 12, -4);
-MEM_TEST("ldr w13, [x5, x6]", 12, -4);
-MEM_TEST("ldr w13, [x5, x6, lsl #2]", 12, -4);
-MEM_TEST("ldr w13, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldr w13, [x5, w6, uxtw #2]", 12, 4);
-MEM_TEST("ldr w13, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldr w13, [x5, w6, sxtw #2]", 12, -4);
-
-MEM_TEST("strh w13, [x5, x6]", 12, -4);
-MEM_TEST("strh w13, [x5, x6, lsl #1]", 12, -4);
-MEM_TEST("strh w13, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("strh w13, [x5, w6, uxtw #1]", 12, 4);
-MEM_TEST("strh w13, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("strh w13, [x5, w6, sxtw #1]", 12, -4);
-MEM_TEST("ldrh w13, [x5, x6]", 12, -4);
-MEM_TEST("ldrh w13, [x5, x6, lsl #1]", 12, -4);
-MEM_TEST("ldrh w13, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldrh w13, [x5, w6, uxtw #1]", 12, 4);
-MEM_TEST("ldrh w13, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldrh w13, [x5, w6, sxtw #1]", 12, -4);
-
-MEM_TEST("strb w13, [x5, x6]", 12, -4);
-MEM_TEST("strb w13, [x5, x6, lsl #0]", 12, -4);
-MEM_TEST("strb w13, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("strb w13, [x5, w6, uxtw #0]", 12, 4);
-MEM_TEST("strb w13, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("strb w13, [x5, w6, sxtw #0]", 12, -4);
-MEM_TEST("ldrb w13, [x5, x6]", 12, -4);
-MEM_TEST("ldrb w13, [x5, x6, lsl #0]", 12, -4);
-MEM_TEST("ldrb w13, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldrb w13, [x5, w6, uxtw #0]", 12, 4);
-MEM_TEST("ldrb w13, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldrb w13, [x5, w6, sxtw #0]", 12, -4);
-
-////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (uimm12)\n");
-MEM_TEST("ldrsw x13, [x5, #24]", -16, 4);
-MEM_TEST("ldrsh x13, [x5, #20]", -16, 4);
-MEM_TEST("ldrsh w13, [x5, #44]", -16, 4);
-MEM_TEST("ldrsb x13, [x5, #72]", -16, 4);
-MEM_TEST("ldrsb w13, [x5, #56]", -16, 4);
-
-////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n");
-MEM_TEST("ldrsw x13, [x5, #-24]!", -16, 4);
-MEM_TEST("ldrsh x13, [x5, #-20]!", -16, 4);
-MEM_TEST("ldrsh w13, [x5, #-44]!", -16, 4);
-MEM_TEST("ldrsb x13, [x5, #-72]!", -16, 4);
-MEM_TEST("ldrsb w13, [x5, #-56]!", -16, 4);
-
-MEM_TEST("ldrsw x13, [x5], #-24", -16, 4);
-MEM_TEST("ldrsh x13, [x5], #-20", -16, 4);
-MEM_TEST("ldrsh w13, [x5], #-44", -16, 4);
-MEM_TEST("ldrsb x13, [x5], #-72", -16, 4);
-MEM_TEST("ldrsb w13, [x5], #-56", -16, 4);
-
-////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (simm9, noUpd)\n");
-MEM_TEST("ldrsw x13, [x5, #-24]", -16, 4);
-MEM_TEST("ldrsh x13, [x5, #-20]", -16, 4);
-MEM_TEST("ldrsh w13, [x5, #-44]", -16, 4);
-MEM_TEST("ldrsb x13, [x5, #-72]", -16, 4);
-MEM_TEST("ldrsb w13, [x5, #-56]", -16, 4);
-
-////////////////////////////////////////////////////////////////
-printf("LDP,STP (immediate, simm7) (FP&VEC)\n");
-
-MEM_TEST("stp q17, q18, [x5, 32]", -16, 4);
-MEM_TEST("stp q17, q18, [x5, 32]!", -16, 4);
-MEM_TEST("stp q17, q18, [x5], 32", -16, 4);
-
-MEM_TEST("stp d17, d18, [x5, 32]", -16, 4);
-MEM_TEST("stp d17, d18, [x5, 32]!", -16, 4);
-MEM_TEST("stp d17, d18, [x5], 32", -16, 4);
-
-//MEM_TEST("stp s17, s18, [x5, 32]", -16, 4);
-//MEM_TEST("stp s17, s18, [x5, 32]!", -16, 4);
-//MEM_TEST("stp s17, s18, [x5], 32", -16, 4);
-
-MEM_TEST("ldp q17, q18, [x5, 32]", -16, 4);
-MEM_TEST("ldp q17, q18, [x5, 32]!", -16, 4);
-MEM_TEST("ldp q17, q18, [x5], 32", -16, 4);
-
-MEM_TEST("ldp d17, d18, [x5, 32]", -16, 4);
-MEM_TEST("ldp d17, d18, [x5, 32]!", -16, 4);
-MEM_TEST("ldp d17, d18, [x5], 32", -16, 4);
-
-//MEM_TEST("ldp s17, s18, [x5, 32]", -16, 4);
-//MEM_TEST("ldp s17, s18, [x5, 32]!", -16, 4);
-//MEM_TEST("ldp s17, s18, [x5], 32", -16, 4);
-
-////////////////////////////////////////////////////////////////
-printf("{LD,ST}R (vector register)\n");
-
-#if 0
-MEM_TEST("str q17, [x5, x6]", 12, -4);
-MEM_TEST("str q17, [x5, x6, lsl #4]", 12, -4);
-MEM_TEST("str q17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("str q17, [x5, w6, uxtw #4]", 12, 4);
-MEM_TEST("str q17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("str q17, [x5, w6, sxtw #4]", 12, -4);
-MEM_TEST("ldr q17, [x5, x6]", 12, -4);
-MEM_TEST("ldr q17, [x5, x6, lsl #4]", 12, -4);
-MEM_TEST("ldr q17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldr q17, [x5, w6, uxtw #4]", 12, 4);
-MEM_TEST("ldr q17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldr q17, [x5, w6, sxtw #4]", 12, -4);
-#endif
-
-MEM_TEST("str d17, [x5, x6]", 12, -4);
-MEM_TEST("str d17, [x5, x6, lsl #3]", 12, -4);
-MEM_TEST("str d17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("str d17, [x5, w6, uxtw #3]", 12, 4);
-MEM_TEST("str d17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("str d17, [x5, w6, sxtw #3]", 12, -4);
-MEM_TEST("ldr d17, [x5, x6]", 12, -4);
-MEM_TEST("ldr d17, [x5, x6, lsl #3]", 12, -4);
-MEM_TEST("ldr d17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldr d17, [x5, w6, uxtw #3]", 12, 4);
-MEM_TEST("ldr d17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldr d17, [x5, w6, sxtw #3]", 12, -4);
-
-MEM_TEST("str s17, [x5, x6]", 12, -4);
-MEM_TEST("str s17, [x5, x6, lsl #2]", 12, -4);
-MEM_TEST("str s17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("str s17, [x5, w6, uxtw #2]", 12, 4);
-MEM_TEST("str s17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("str s17, [x5, w6, sxtw #2]", 12, -4);
-MEM_TEST("ldr s17, [x5, x6]", 12, -4);
-MEM_TEST("ldr s17, [x5, x6, lsl #2]", 12, -4);
-MEM_TEST("ldr s17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldr s17, [x5, w6, uxtw #2]", 12, 4);
-MEM_TEST("ldr s17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldr s17, [x5, w6, sxtw #2]", 12, -4);
-
-#if 0
-MEM_TEST("str h17, [x5, x6]", 12, -4);
-MEM_TEST("str h17, [x5, x6, lsl #1]", 12, -4);
-MEM_TEST("str h17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("str h17, [x5, w6, uxtw #1]", 12, 4);
-MEM_TEST("str h17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("str h17, [x5, w6, sxtw #1]", 12, -4);
-MEM_TEST("ldr h17, [x5, x6]", 12, -4);
-MEM_TEST("ldr h17, [x5, x6, lsl #1]", 12, -4);
-MEM_TEST("ldr h17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldr h17, [x5, w6, uxtw #1]", 12, 4);
-MEM_TEST("ldr h17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldr h17, [x5, w6, sxtw #1]", 12, -4);
-
-MEM_TEST("str b17, [x5, x6]", 12, -4);
-MEM_TEST("str b17, [x5, x6, lsl #0]", 12, -4);
-MEM_TEST("str b17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("str b17, [x5, w6, uxtw #0]", 12, 4);
-MEM_TEST("str b17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("str b17, [x5, w6, sxtw #0]", 12, -4);
-MEM_TEST("ldr b17, [x5, x6]", 12, -4);
-MEM_TEST("ldr b17, [x5, x6, lsl #0]", 12, -4);
-MEM_TEST("ldr b17, [x5, w6, uxtw]", 12, 4);
-MEM_TEST("ldr b17, [x5, w6, uxtw #0]", 12, 4);
-MEM_TEST("ldr b17, [x5, w6, sxtw]", 12, 4);
-MEM_TEST("ldr b17, [x5, w6, sxtw #0]", 12, -4);
-#endif
-
-////////////////////////////////////////////////////////////////
-printf("LDRS{B,H,W} (integer register, SX)\n");
-
-MEM_TEST("ldrsw x13, [x5,x6]", 12, -4);
-MEM_TEST("ldrsw x13, [x5,x6, lsl #2]", 12, -4);
-MEM_TEST("ldrsw x13, [x5,w6,uxtw #0]", 12, 4);
-MEM_TEST("ldrsw x13, [x5,w6,uxtw #2]", 12, 4);
-MEM_TEST("ldrsw x13, [x5,w6,sxtw #0]", 12, 4);
-MEM_TEST("ldrsw x13, [x5,w6,sxtw #2]", 12, -4);
-
-MEM_TEST("ldrsh x13, [x5,x6]", 12, -4);
-MEM_TEST("ldrsh x13, [x5,x6, lsl #1]", 12, -4);
-MEM_TEST("ldrsh x13, [x5,w6,uxtw #0]", 12, 4);
-MEM_TEST("ldrsh x13, [x5,w6,uxtw #1]", 12, 4);
-MEM_TEST("ldrsh x13, [x5,w6,sxtw #0]", 12, 4);
-MEM_TEST("ldrsh x13, [x5,w6,sxtw #1]", 12, -4);
-
-MEM_TEST("ldrsh w13, [x5,x6]", 12, -4);
-MEM_TEST("ldrsh w13, [x5,x6, lsl #1]", 12, -4);
-MEM_TEST("ldrsh w13, [x5,w6,uxtw #0]", 12, 4);
-MEM_TEST("ldrsh w13, [x5,w6,uxtw #1]", 12, 4);
-MEM_TEST("ldrsh w13, [x5,w6,sxtw #0]", 12, 4);
-MEM_TEST("ldrsh w13, [x5,w6,sxtw #1]", 12, -4);
-
-MEM_TEST("ldrsb x13, [x5,x6]", 12, -4);
-MEM_TEST("ldrsb x13, [x5,x6, lsl #0]", 12, -4);
-MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
-MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
-MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, 4);
-MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, -4);
-
-MEM_TEST("ldrsb w13, [x5,x6]", 12, -4);
-MEM_TEST("ldrsb w13, [x5,x6, lsl #0]", 12, -4);
-MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
-MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
-MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, 4);
-MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, -4);
-
-
-////////////////////////////////////////////////////////////////
-printf("LDR/STR (immediate, SIMD&FP, unsigned offset)\n");
-MEM_TEST("str q17, [x5, #-32]", 16, 0);
-MEM_TEST("str d17, [x5, #-32]", 16, 0);
-MEM_TEST("str s17, [x5, #-32]", 16, 0);
-//MEM_TEST("str h17, [x5, #-32]", 16, 0);
-//MEM_TEST("str b17, [x5, #-32]", 16, 0);
-MEM_TEST("ldr q17, [x5, #-32]", 16, 0);
-MEM_TEST("ldr d17, [x5, #-32]", 16, 0);
-MEM_TEST("ldr s17, [x5, #-32]", 16, 0);
-//MEM_TEST("ldr h17, [x5, #-32]", 16, 0);
-//MEM_TEST("ldr b17, [x5, #-32]", 16, 0);
-
-////////////////////////////////////////////////////////////////
-printf("LDR/STR (immediate, SIMD&FP, pre/post index)\n");
-MEM_TEST("str q17, [x5], #-32", 16, 0);
-MEM_TEST("str d17, [x5], #-32", 16, 0);
-MEM_TEST("str s17, [x5], #-32", 16, 0);
-//MEM_TEST("str h17, [x5], #-32", 16, 0);
-//MEM_TEST("str b17, [x5], #-32", 16, 0);
-MEM_TEST("ldr q17, [x5], #-32", 16, 0);
-MEM_TEST("ldr d17, [x5], #-32", 16, 0);
-MEM_TEST("ldr s17, [x5], #-32", 16, 0);
-//MEM_TEST("ldr h17, [x5], #-32", 16, 0);
-//MEM_TEST("ldr b17, [x5], #-32", 16, 0);
-
-MEM_TEST("str q17, [x5, #-32]!", 16, 0);
-MEM_TEST("str d17, [x5, #-32]!", 16, 0);
-MEM_TEST("str s17, [x5, #-32]!", 16, 0);
-//MEM_TEST("str h17, [x5, #-32]!", 16, 0);
-//MEM_TEST("str b17, [x5, #-32]!", 16, 0);
-MEM_TEST("ldr q17, [x5, #-32]!", 16, 0);
-MEM_TEST("ldr d17, [x5, #-32]!", 16, 0);
-MEM_TEST("ldr s17, [x5, #-32]!", 16, 0);
-//MEM_TEST("ldr h17, [x5, #-32]!", 16, 0);
-//MEM_TEST("ldr b17, [x5, #-32]!", 16, 0);
-
-
-////////////////////////////////////////////////////////////////
-printf("LDUR/STUR (unscaled offset, SIMD&FP)\n");
-MEM_TEST("str q17, [x5, #-13]", 16, 0);
-MEM_TEST("str d17, [x5, #-13]", 16, 0);
-MEM_TEST("str s17, [x5, #-13]", 16, 0);
-//MEM_TEST("str h17, [x5, #-13]", 16, 0);
-//MEM_TEST("str b17, [x5, #-13]", 16, 0);
-MEM_TEST("ldr q17, [x5, #-13]", 16, 0);
-MEM_TEST("ldr d17, [x5, #-13]", 16, 0);
-MEM_TEST("ldr s17, [x5, #-13]", 16, 0);
-//MEM_TEST("ldr h17, [x5, #-13]", 16, 0);
-//MEM_TEST("ldr b17, [x5, #-13]", 16, 0);
-
-////////////////////////////////////////////////////////////////
-printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
-
-////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (single structure, no offset)\n");
-MEM_TEST("st1 {v17.2d}, [x5]", 3, 0)
-MEM_TEST("st1 {v17.4s}, [x5]", 5, 0)
-MEM_TEST("st1 {v17.8h}, [x5]", 7, 0)
-MEM_TEST("st1 {v17.16b}, [x5]", 13, 0)
-MEM_TEST("st1 {v17.1d}, [x5]", 3, 0)
-MEM_TEST("st1 {v17.2s}, [x5]", 5, 0)
-MEM_TEST("st1 {v17.4h}, [x5]", 7, 0)
-MEM_TEST("st1 {v17.8b}, [x5]", 13, 0)
-
-MEM_TEST("ld1 {v17.2d}, [x5]", 3, 0)
-MEM_TEST("ld1 {v17.4s}, [x5]", 5, 0)
-MEM_TEST("ld1 {v17.8h}, [x5]", 7, 0)
-MEM_TEST("ld1 {v17.16b}, [x5]", 13, 0)
-MEM_TEST("ld1 {v17.1d}, [x5]", 3, 0)
-MEM_TEST("ld1 {v17.2s}, [x5]", 5, 0)
-MEM_TEST("ld1 {v17.4h}, [x5]", 7, 0)
-MEM_TEST("ld1 {v17.8b}, [x5]", 13, 0)
-
-////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (single structure, post index)\n");
-MEM_TEST("st1 {v17.2d}, [x5], #16", 3, 0)
-MEM_TEST("st1 {v17.4s}, [x5], #16", 5, 0)
-MEM_TEST("st1 {v17.8h}, [x5], #16", 7, 0)
-MEM_TEST("st1 {v17.16b}, [x5], #16", 13, 0)
-MEM_TEST("st1 {v17.1d}, [x5], #8", 3, 0)
-MEM_TEST("st1 {v17.2s}, [x5], #8", 5, 0)
-MEM_TEST("st1 {v17.4h}, [x5], #8", 7, 0)
-MEM_TEST("st1 {v17.8b}, [x5], #8", 13, 0)
-
-MEM_TEST("ld1 {v17.2d}, [x5], #16", 3, 0)
-MEM_TEST("ld1 {v17.4s}, [x5], #16", 5, 0)
-MEM_TEST("ld1 {v17.8h}, [x5], #16", 7, 0)
-MEM_TEST("ld1 {v17.16b}, [x5], #16", 13, 0)
-MEM_TEST("ld1 {v17.1d}, [x5], #8", 3, 0)
-MEM_TEST("ld1 {v17.2s}, [x5], #8", 5, 0)
-MEM_TEST("ld1 {v17.4h}, [x5], #8", 7, 0)
-MEM_TEST("ld1 {v17.8b}, [x5], #8", 13, 0)
-
-////////////////////////////////////////////////////////////////
-printf("LD1R (single structure, replicate)\n");
-MEM_TEST("ld1r {v17.2d}, [x5]", 3, -5)
-MEM_TEST("ld1r {v17.1d}, [x5]", 3, -4)
-MEM_TEST("ld1r {v17.4s}, [x5]", 3, -3)
-MEM_TEST("ld1r {v17.2s}, [x5]", 3, -2)
-MEM_TEST("ld1r {v17.8h}, [x5]", 3, -1)
-MEM_TEST("ld1r {v17.4h}, [x5]", 3, 1)
-MEM_TEST("ld1r {v17.16b}, [x5]", 3, 2)
-MEM_TEST("ld1r {v17.8b}, [x5]", 3, 3)
-
-MEM_TEST("ld1r {v17.2d}, [x5], #8", 3, -5)
-MEM_TEST("ld1r {v17.1d}, [x5], #8", 3, -4)
-MEM_TEST("ld1r {v17.4s}, [x5], #4", 3, -3)
-MEM_TEST("ld1r {v17.2s}, [x5], #4", 3, -2)
-MEM_TEST("ld1r {v17.8h}, [x5], #2", 3, -1)
-MEM_TEST("ld1r {v17.4h}, [x5], #2", 3, 1)
-MEM_TEST("ld1r {v17.16b}, [x5], #1", 3, 2)
-MEM_TEST("ld1r {v17.8b}, [x5], #1", 3, 3)
-
-MEM_TEST("ld1r {v17.2d}, [x5], x6", 3, -5)
-MEM_TEST("ld1r {v17.1d}, [x5], x6", 3, -4)
-MEM_TEST("ld1r {v17.4s}, [x5], x6", 3, -3)
-MEM_TEST("ld1r {v17.2s}, [x5], x6", 3, -2)
-MEM_TEST("ld1r {v17.8h}, [x5], x6", 3, -1)
-MEM_TEST("ld1r {v17.4h}, [x5], x6", 3, 1)
-MEM_TEST("ld1r {v17.16b}, [x5], x6", 3, 2)
-MEM_TEST("ld1r {v17.8b}, [x5], x6", 3, 3)
-
-////////////////////////////////////////////////////////////////
-printf("LD2/ST2 (multiple 2-elem structs to/from 2/regs, post index)"
- " (VERY INCOMPLETE)\n");
-
-MEM_TEST("ld2 {v17.2d, v18.2d}, [x5], #32", 3, 0)
-MEM_TEST("st2 {v17.2d, v18.2d}, [x5], #32", 7, 0)
-
-MEM_TEST("ld2 {v17.4s, v18.4s}, [x5], #32", 13, 0)
-MEM_TEST("st2 {v17.4s, v18.4s}, [x5], #32", 17, 0)
-
-
-////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (multiple 1-elem structs to/from 2 regs, no offset)"
- " (VERY INCOMPLETE)\n");
-
-MEM_TEST("ld1 {v17.16b, v18.16b}, [x5]", 3, 0)
-MEM_TEST("st1 {v17.16b, v18.16b}, [x5]", 7, 0)
-
-
-////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (multiple 1-elem structs to/from 2 regs, post index)"
- " (VERY INCOMPLETE)\n");
-
-MEM_TEST("ld1 {v17.16b, v18.16b}, [x5], #32", 3, 0)
-MEM_TEST("st1 {v17.16b, v18.16b}, [x5], #32", 7, 0)
-
-
-////////////////////////////////////////////////////////////////
-printf("LD1/ST1 (multiple 1-elem structs to/from 3 regs, no offset)"
- " (VERY INCOMPLETE)\n");
-
-MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5]", 3, 0)
-MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5]", 7, 0)
-
-
-////////////////////////////////////////////////////////////////
-printf("LD3/ST3 (multiple 3-elem structs to/from 3/regs, post index)"
- " (VERY INCOMPLETE)\n");
-
-MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 13, 0)
-MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 17, 0)
-
-
-
-} /* end of test_memory2() */
-
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////
int main ( void )
{
if (1) test_arith();
- if (1) test_memory();
- if (1) test_memory2();
return 0;
}
smsubl x14,w15,w16,x17 :: rd 728a1d8a96c26c68 rm a6325ae016fbd710, rn f0211fade82d1008, ra 70668d1659e224e8, cin 0, nzcv 00000000
smsubl x14,w15,w16,x17 :: rd 5399710b490151b6 rm 1f1dd8017f191501, rn f69aef71040bfeab, ra 559bc9e2fca45761, cin 0, nzcv 00000000
smsubl x14,w15,w16,x17 :: rd a6de96c8aaae46b7 rm 389ce2f3140cec0c, rn 7a3ab866f2dcd171, ra a5d72d6243684403, cin 0, nzcv 00000000
-Integer loads
-LDR,STR (immediate, uimm12) (STR cases are MISSING)ldr x21, [x22, #24] :: rd 8f8e8d8c8b8a8988 rn (hidden), cin 0, nzcv 00000000
-ldr w21, [x22, #20] :: rd 0000000087868584 rn (hidden), cin 0, nzcv 00000000
-ldrh w21, [x22, #44] :: rd 0000000000009d9c rn (hidden), cin 0, nzcv 00000000
-ldrb w21, [x22, #56] :: rd 00000000000000a8 rn (hidden), cin 0, nzcv 00000000
-LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)
-ldr x21, [x22], #-24 :: rd f7f6f5f4f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
-ldr x21, [x22, #-40]! :: rd cfcecdcccbcac9c8 rn (hidden), cin 0, nzcv 00000000
-ldr x21, [x22, #-48] :: rd c7c6c5c4c3c2c1c0 rn (hidden), cin 0, nzcv 00000000
-LDUR,STUR (immediate, simm9): STR cases are MISSINGLDP,STP (immediate, simm7) (STR cases and wb check is MISSING)
-ldp x21, x28, [x22], #-24 ; add x21,x21,x28 :: rd f7f5f3f1efedebe8 rn (hidden), cin 0, nzcv 00000000
-ldp x21, x28, [x22], #-24 ; eor x21,x21,x28 :: rd 0808080808080808 rn (hidden), cin 0, nzcv 00000000
-ldp x21, x28, [x22, #-40]! ; add x21,x21,x28 :: rd a7a5a3a19f9d9b98 rn (hidden), cin 0, nzcv 00000000
-ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28 :: rd 1818181818181818 rn (hidden), cin 0, nzcv 00000000
-ldp x21, x28, [x22, #-40] ; add x21,x21,x28 :: rd a7a5a3a19f9d9b98 rn (hidden), cin 0, nzcv 00000000
-ldp x21, x28, [x22, #-40] ; eor x21,x21,x28 :: rd 1818181818181818 rn (hidden), cin 0, nzcv 00000000
-ldp w21, w28, [x22], #-24 ; add x21,x21,x28 :: rd 00000001ebe9e7e4 rn (hidden), cin 0, nzcv 00000000
-ldp w21, w28, [x22], #-24 ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
-ldp w21, w28, [x22, #-40]! ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000
-ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
-ldp w21, w28, [x22, #-40] ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000
-ldp w21, w28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
-LDR (literal, int reg)
-xyzzy00: ldr x21, xyzzy00 - 8 :: rd aa0003f6d51b4203 rn (hidden), cin 0, nzcv 00000000
-xyzzy01: ldr x21, xyzzy01 + 0 :: rd aa1503e258000015 rn (hidden), cin 0, nzcv 00000000
-xyzzy02: ldr x21, xyzzy02 + 8 :: rd 911e43a0d53b4201 rn (hidden), cin 0, nzcv 00000000
-xyzzy03: ldr x21, xyzzy03 - 4 :: rd 58fffff5aa0003f6 rn (hidden), cin 0, nzcv 00000000
-xyzzy04: ldr x21, xyzzy04 + 0 :: rd aa1503e258000015 rn (hidden), cin 0, nzcv 00000000
-xyzzy05: ldr x21, xyzzy05 + 4 :: rd d53b4201aa1503e2 rn (hidden), cin 0, nzcv 00000000
-{LD,ST}R (integer register) (entirely MISSING)
-LDRS{B,H,W} (uimm12)
-ldrsw x21, [x22, #24] :: rd ffffffff8b8a8988 rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22, #20] :: rd ffffffffffff8584 rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22, #44] :: rd 00000000ffff9d9c rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22, #88] :: rd ffffffffffffffc8 rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22, #56] :: rd 00000000ffffffa8 rn (hidden), cin 0, nzcv 00000000
-LDRS{B,H,W} (simm9, upd) (upd check is MISSING)
-ldrsw x21, [x22, #-24]! :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22, #-20]! :: rd ffffffffffffdddc rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22, #-44]! :: rd 00000000ffffc5c4 rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22, #-88]! :: rd ffffffffffffff98 rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22, #-56]! :: rd 00000000ffffffb8 rn (hidden), cin 0, nzcv 00000000
-ldrsw x21, [x22], #-24 :: rd fffffffff3f2f1f0 rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22], #-20 :: rd fffffffffffff1f0 rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22], #-44 :: rd 00000000fffff1f0 rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22], #-88 :: rd fffffffffffffff0 rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22], #-56 :: rd 00000000fffffff0 rn (hidden), cin 0, nzcv 00000000
-LDRS{B,H,W} (simm9, noUpd)
-ldrsw x21, [x22, #-24] :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22, #-20] :: rd ffffffffffffdddc rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22, #-44] :: rd 00000000ffffc5c4 rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22, #-88] :: rd ffffffffffffff98 rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22, #-56] :: rd 00000000ffffffb8 rn (hidden), cin 0, nzcv 00000000
-LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING)
-{LD,ST}R (vector register) (entirely MISSING)
-LDRS{B,H,W} (integer register, SX)
-ldrsw x21, [x22,x23] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsw x21, [x22,x23, lsl #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsw x21, [x22,w23,uxtw #0] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsw x21, [x22,w23,uxtw #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsw x21, [x22,w23,sxtw #0] :: rd ffffffffeeedeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsw x21, [x22,w23,sxtw #2] :: rd ffffffffdfdedddc rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22,x23] :: rd fffffffffffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22,x23, lsl #1] :: rd fffffffffffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22,w23,uxtw #0] :: rd fffffffffffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22,w23,uxtw #1] :: rd fffffffffffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22,w23,sxtw #0] :: rd ffffffffffffeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh x21, [x22,w23,sxtw #1] :: rd ffffffffffffe7e6 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22,x23] :: rd 00000000fffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22,x23, lsl #1] :: rd 00000000fffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22,w23,uxtw #0] :: rd 00000000fffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22,w23,uxtw #1] :: rd 00000000fffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22,w23,sxtw #0] :: rd 00000000ffffeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsh w21, [x22,w23,sxtw #1] :: rd 00000000ffffe7e6 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22,x23] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22,x23, lsl #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22,w23,uxtw #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22,w23,uxtw #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22,w23,sxtw #0] :: rd ffffffffffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb x21, [x22,w23,sxtw #0] :: rd ffffffffffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22,x23] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22,x23, lsl #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22,w23,uxtw #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22,w23,uxtw #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22,w23,sxtw #0] :: rd 00000000ffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000
-ldrsb w21, [x22,w23,sxtw #0] :: rd 00000000ffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000
-LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING)
-LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING)
-LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING)
-LDR (literal, SIMD&FP) (entirely MISSING)
-LD1/ST1 (single structure, no offset) (entirely MISSING)
-LD1/ST1 (single structure, post index) (entirely MISSING)
-LD{,A}X{R,RH,RB} (entirely MISSING)
-ST{,L}X{R,RH,RB} (entirely MISSING)
-LDA{R,RH,RB}
-ldar x21, [x22] :: rd f7f6f5f4f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
-ldar w21, [x22] :: rd 00000000f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
-ldarh w21, [x22] :: rd 000000000000f1f0 rn (hidden), cin 0, nzcv 00000000
-ldarb w21, [x22] :: rd 00000000000000f0 rn (hidden), cin 0, nzcv 00000000
-STL{R,RH,RB} (entirely MISSING)
-LDR,STR (immediate, uimm12)ldr x13, [x5, #24] with x5 = middle_of_block+-1, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 37c6ea00e0f4f257 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr w13, [x5, #20] with x5 = middle_of_block+1, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 663cba29f1fe102a x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrh w13, [x5, #44] with x5 = middle_of_block+2, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 74b2685cb1630837 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrb w13, [x5, #56] with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- bf73927edcc8e3a7 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5, #24] with x5 = middle_of_block+-3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. 3d b5 fe cd 8f 1e a7 32 .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str w13, [x5, #20] with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. fb 48 5c 15 .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strh w13, [x5, #44] with x5 = middle_of_block+6, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. 43 .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strb w13, [x5, #56] with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. bd
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDUR,STUR (immediate, simm9)
-ldr x13, [x5], #-24 with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 5e602f48b53d6e42 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -24 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr x13, [x5, #-40]! with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- c2a40eb09d08f981 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -40 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr x13, [x5, #-48] with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- c5349b34f359e130 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5], #-24 with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] 3a 9b 1d 46 18 b0 ef 81 .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -24 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5, #-40]! with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. 3f 73 c0 0a b7 5c 8d 74
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -40 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5, #-48] with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] 09 95 f8 6e 41 d0 2d 47 .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDP,STP (immediate, simm7)
-ldp x13, x23, [x5], #-24 with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 1b66ab089f41ee43 x13 (xor, xfer intreg #1)
- ac8fc79beb26e5f5 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -24 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp x13, x23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b98f2dea69fe5015 x13 (xor, xfer intreg #1)
- 5913a7a99bcd1811 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -40 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp x13, x23, [x5, #-40] with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ba55d10667c950ff x13 (xor, xfer intreg #1)
- b91a382f89560923 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp x13, x23, [x5], #-24 with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] 22 0e b6 7d 25 b1 49 6c 85 67 29 ca e9 6b 42 6c
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -24 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp x13, x23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. 72 af 97 76 3d b0 cc 4f
- [ 96] 22 1a 6b 79 8f 52 63 1e .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -40 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp x13, x23, [x5, #-40] with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. ef cf 9b 01 25 8f 11 54
- [ 96] 58 be 1c a8 1f 77 e8 26 .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp w13, w23, [x5], #-24 with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 5826bd372d9e2ece x13 (xor, xfer intreg #1)
- a690cbe50b71f694 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -24 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp w13, w23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- c4a8641060c8618a x13 (xor, xfer intreg #1)
- f5f25be4fdcff02a x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -40 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp w13, w23, [x5, #-40] with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- f711f2d5f6d39080 x13 (xor, xfer intreg #1)
- 2e212f8dcab7fa0d x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp w13, w23, [x5], #-24 with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] c0 f4 d9 ba de 39 bb 1f .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -24 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp w13, w23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. b3 3b 5a ac f6 fc e4
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -40 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp w13, w23, [x5, #-40] with x5 = middle_of_block+0, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. 66 84 fc c9 b9 a8 37 28
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDR (literal, int reg) (DONE ABOVE)
-{LD,ST}R (integer register) (entirely MISSING)
-str x13, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. b8 34 a7 48 08 af c1 91
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. e8 b0 5c d8
- [112] 52 99 34 7c .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 35 92 d1 bb d7 45 bf dc .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. 3d 99 5a 39
- [176] a9 f4 a3 2d .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] a5 3f df 5d 66 f7 20 e8 .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str x13, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 5d e8 12 15
- [112] 96 8e 05 30 .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr x13, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 91e9b1a8348ca797 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr x13, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 1cb5b125b109faeb x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr x13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 4085aae03ffeda0c x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr x13, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 6a28851da073b3f9 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr x13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 72858dcc143fe6ef x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr x13, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- de1c29d387e40b0c x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. 44 ba 04 81 .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str w13, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. d6 af 6a d7
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 80 ee 73 ad .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str w13, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. cf 5c 96 91
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 4f 39 ed 78 .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str w13, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. 8a 61 ee 1b
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 8482adce109203e3 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr w13, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- fcbcda5053fe3119 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 9bbc4e9ea534edef x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr w13, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 27f86f4c86c32be6 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 62e39eed83444fa6 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr w13, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 12f04216e80ea35a x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strh w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. 59 fc .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strh w13, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. dc 12 .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strh w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 05 f8 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strh w13, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. fa ac .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strh w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 33 e0 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strh w13, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. c8 9a .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrh w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- d8322d9d06f127c8 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrh w13, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b6a77dd46effc11f x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrh w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ec53c5c6d2bc4105 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrh w13, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 3dab680838dbf069 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrh w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 6f21cb2ea4117de5 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrh w13, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 442a51cc1911c952 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strb w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. f9 .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strb w13, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. 87 .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strb w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] c4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strb w13, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] c3 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strb w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 51 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-strb w13, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. d4 .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrb w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 568db3c39f462465 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrb w13, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- da7e66eeefeac8c3 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrb w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- e616c1c66bacf629 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrb w13, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 3dc827dc1a415140 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrb w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- a50afdc7fd5c7dde x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrb w13, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- e14fa7191ab21ead x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDRS{B,H,W} (uimm12)
-ldrsw x13, [x5, #24] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 4bf47798b0084d23 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5, #20] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 1c4efbbaef23ef5c x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5, #44] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 32b781460ee5ea9b x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5, #72] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 9a6f9e00e49efa40 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5, #56] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 40af08046d98739f x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDRS{B,H,W} (simm9, upd) (upd check is MISSING)
-ldrsw x13, [x5, #-24]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 868adbe916974e3c x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -24 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5, #-20]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 026cc1be8681bd68 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -20 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5, #-44]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 674094a1f1f871a6 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -44 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5, #-72]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 8903429dc60011fa x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -72 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5, #-56]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 2752acc8fc4a8119 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -56 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsw x13, [x5], #-24 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 059f35b78686b811 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -24 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5], #-20 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 199fbe0162896025 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -20 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5], #-44 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 900736310fc037e8 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -44 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5], #-72 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- c50975e3f31cb340 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -72 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5], #-56 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 4adb65a9b3c0ee9d x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -56 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDRS{B,H,W} (simm9, noUpd)
-ldrsw x13, [x5, #-24] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- e3ef68173ef979fb x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5, #-20] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 54bae2c06ea881e0 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5, #-44] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 61b03939c0a975cd x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5, #-72] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 32b930e96a65fd89 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5, #-56] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 5eee08eb7529502a x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDP,STP (immediate, simm7) (FP&VEC)
-stp q17, q18, [x5, 32] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 55 18 f1 5c aa 84 c0 38 cd 7e 31 c8 92 f4 b0 e7
- [160] 0e 6c 4b d1 1e 2a 76 4c e2 a7 c8 5a 26 59 0e 5b
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp q17, q18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 02 3e c1 07 ca e4 d0 ed 19 98 1e 29 25 e0 75 25
- [160] e1 0f a7 69 a1 4c 5b 2c 01 08 48 ca f8 ff dc 16
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp q17, q18, [x5], 32 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 67 98 a3 78 5f 8e f9 57 5e 90 fc 32 c8 db d6 2c
- [128] 20 68 2a 31 1b f7 e9 b2 9f 6a 21 20 db 21 17 27
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp d17, d18, [x5, 32] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] a0 6c d2 7f 89 d1 b1 b6 c5 5d 74 11 63 9d cb b9
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp d17, d18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 6f 14 75 6c 06 fe e1 ea 40 30 6e 55 7c 36 4d c4
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-stp d17, d18, [x5], 32 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] c2 ae 80 3d 80 4f 9f 9e 93 76 25 55 85 51 97 1a
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp q17, q18, [x5, 32] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- c3aeec76faa5f5c3 v17.d[0] (xor, xfer vecreg #1)
- d81dc8f6818b6e41 v17.d[1] (xor, xfer vecreg #1)
- c4709239d600ee90 v18.d[0] (xor, xfer vecreg #2)
- a640a2efa8725362 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp q17, q18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 80b42ff8dc0573ed v17.d[0] (xor, xfer vecreg #1)
- 978d0461007b54b8 v17.d[1] (xor, xfer vecreg #1)
- 47b1ef6f289cbd69 v18.d[0] (xor, xfer vecreg #2)
- 4283a680f9f42f27 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp q17, q18, [x5], 32 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 32e4abace36584a4 v17.d[0] (xor, xfer vecreg #1)
- 94465539af6bee2a v17.d[1] (xor, xfer vecreg #1)
- 45ee7595ed87a70a v18.d[0] (xor, xfer vecreg #2)
- 0b0689e9f49030da v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp d17, d18, [x5, 32] with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 81468c3a81e28308 v17.d[0] (xor, xfer vecreg #1)
- 9402389a9fd7e622 v17.d[1] (xor, xfer vecreg #1)
- ac80e445d56aaf23 v18.d[0] (xor, xfer vecreg #2)
- f429df6f28a16e8a v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp d17, d18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 63c656d72c05e674 v17.d[0] (xor, xfer vecreg #1)
- 0693fb5daf24d9a0 v17.d[1] (xor, xfer vecreg #1)
- ce871ca48d1a40cc v18.d[0] (xor, xfer vecreg #2)
- d38bf1af25daca31 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldp d17, d18, [x5], 32 with x5 = middle_of_block+-16, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- ce2bf285733f1da6 v17.d[0] (xor, xfer vecreg #1)
- d57bc365125181f6 v17.d[1] (xor, xfer vecreg #1)
- 0fde67d4c6716a14 v18.d[0] (xor, xfer vecreg #2)
- f4335fd1bac1932e v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-{LD,ST}R (vector register)
-str d17, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. db 63 b8 ac e6 bd 2f 97
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 0e cf b0 95
- [112] ba ca a7 9c .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 20 05 ac 34 8e ff 78 7a .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. 61 1e 17 07
- [176] cd a0 14 3e .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] fe 3c 6b 02 b7 fe 10 c3 .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 7f b8 e7 ca
- [112] 50 fb 04 68 .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 368c5b732c1248a5 v17.d[0] (xor, xfer vecreg #1)
- f68888b1170ad684 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- ee01fe34a2d85c41 v17.d[0] (xor, xfer vecreg #1)
- 3b8184af9c823f6c v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- dc4fd084ba3953c1 v17.d[0] (xor, xfer vecreg #1)
- 426589a518aea21f v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 619304aa5a129766 v17.d[0] (xor, xfer vecreg #1)
- 4e2a7aa80ec124f3 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 8d7d6fe89f4f3dd9 v17.d[0] (xor, xfer vecreg #1)
- a2c23ccc03f0e73c v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 480d291c1baa1e67 v17.d[0] (xor, xfer vecreg #1)
- 8323b3257a6e114c v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. 05 44 01 d5 .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. 5b 32 ec e5
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 79 ee 29 c6 .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. 41 e4 eb 1d
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] e6 b1 03 2d .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. ec f6 d1 82
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- f1bb54fe78f0286a v17.d[0] (xor, xfer vecreg #1)
- 63b582e54ba32e35 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 59faf450fdf6566e v17.d[0] (xor, xfer vecreg #1)
- 3ba5adb465ed9857 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- cfed330c080743c7 v17.d[0] (xor, xfer vecreg #1)
- 03f1916ba55aac35 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 160a73c656d57e46 v17.d[0] (xor, xfer vecreg #1)
- 018e121e8f1f8f24 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- f4c4181184dc39c4 v17.d[0] (xor, xfer vecreg #1)
- 776e13e3a8706377 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 2c8e878293ad5852 v17.d[0] (xor, xfer vecreg #1)
- ab8679cc737f4e82 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDRS{B,H,W} (integer register, SX)
-ldrsw x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 4991809b592766de x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsw x13, [x5,x6, lsl #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ecab746191e71575 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsw x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 22a74ae38fee367e x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsw x13, [x5,w6,uxtw #2] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 1cd6637ce5e8e8da x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsw x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 9eab24c24f0ac55c x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsw x13, [x5,w6,sxtw #2] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 6c9cf046e9a2bfa3 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b5e3d360b748922c x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- fb9f3c5f3b2bddc4 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ba667ce49472fbca x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ea7d6667dd92cdf2 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- afc148d693ed6288 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh x13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 58d88efd9452995d x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5,x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- a8359b70e176717b x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 654ed4c3800da87c x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 51959d8974ca561f x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 32805957c26143f5 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ca816dc1927863b6 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsh w13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- de0e3d5a79ef9f53 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- ce66d34814b16659 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 89989f6cc65775a1 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 578206f2f140e49e x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 54bd9f2dc8392d13 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b0320b9e0885afab x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- a1e0a2c260cad60b x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5,x6] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 45283e54c51f5bad x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- c75cfa3b6ceb89d9 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- aa2ff686984d59d6 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- b01695c9b1059196 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 9f833c9791a66c27 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 39eb4f856504f7ce x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDR/STR (immediate, SIMD&FP, unsigned offset)
-str q17, [x5, #-32] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 7b 5d 69 f7 64 8c 79 47 6f 8f 57 84 7b c3 9c 9f
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5, #-32] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 42 cd cc 36 af 70 5a 49 .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, #-32] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 8d 06 22 df .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr q17, [x5, #-32] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- eedbb4bf846226cd v17.d[0] (xor, xfer vecreg #1)
- 94094b6d188de7fa v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, #-32] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 029fcee15d9319f2 v17.d[0] (xor, xfer vecreg #1)
- 50541814802369e6 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, #-32] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 86bcef9905c6716d v17.d[0] (xor, xfer vecreg #1)
- fa13cb2fc8681760 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDR/STR (immediate, SIMD&FP, pre/post index)
-str q17, [x5], #-32 with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 3a fc f2 7c 33 4d e6 bb 98 8b 63 7d c8 cc ed c5
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5], #-32 with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] d6 89 52 b2 c9 1c 8f 84 .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5], #-32 with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] 61 9d 73 ee .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr q17, [x5], #-32 with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- f3e66911400e0ffd v17.d[0] (xor, xfer vecreg #1)
- bceee589d845dc5c v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5], #-32 with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 476d9e9cc8b9ac0a v17.d[0] (xor, xfer vecreg #1)
- 17224cc91cc3a43e v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5], #-32 with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 20d04ccbe8ce283b v17.d[0] (xor, xfer vecreg #1)
- 22146e45c5a92bce v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 3c 68 70 1a e9 09 6a 17 ff 65 da cd 31 9d 99 f7
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] 1a ee af 76 38 32 54 22 .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] bd ff 23 fb .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- c08cfa3f5c85e9ec v17.d[0] (xor, xfer vecreg #1)
- d13f15e778e3733d v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 8cd8469c4bb50f10 v17.d[0] (xor, xfer vecreg #1)
- 0cee45c96b719b9f v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 8cb8b23ad49fbfa0 v17.d[0] (xor, xfer vecreg #1)
- 0864e77407470a14 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDUR/STUR (unscaled offset, SIMD&FP)
-str q17, [x5, #-13] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 92 be 41 c2 36 e0 f2 76 79 06 b2 b1 bd
- [144] 83 b1 f0 .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str d17, [x5, #-13] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. ff 9d d1 08 13 ab 3d b9 .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-str s17, [x5, #-13] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. bb bb 62 b6 .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr q17, [x5, #-13] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 315438529f368984 v17.d[0] (xor, xfer vecreg #1)
- 63c745a60b8405eb v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr d17, [x5, #-13] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 61d08c15c6fc312c v17.d[0] (xor, xfer vecreg #1)
- 8f9963f2cf0bade7 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ldr s17, [x5, #-13] with x5 = middle_of_block+16, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 2b5282c8bfe45946 v17.d[0] (xor, xfer vecreg #1)
- 0ce3959eed221512 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LDR (literal, SIMD&FP) (entirely MISSING)
-LD1/ST1 (single structure, no offset)
-st1 {v17.2d}, [x5] with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. b8 20 bd e5 8a f9 76 f3 cc ae a8 d0 18
- [144] 47 f5 2c .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.4s}, [x5] with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. 64 0a f3 ac 33 39 0b fb cb 96 09
- [144] 7b ac c2 61 4e .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.8h}, [x5] with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 24 9d d3 60 d7 68 98 1a d1
- [144] 3c 02 23 a5 ab 09 03 .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.16b}, [x5] with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. c0 d2 1e
- [144] 09 b5 58 b4 9e d4 9d d9 78 3f 12 c7 ad .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.1d}, [x5] with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 9e 6a 38 6f 46 53 2c 51 .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.2s}, [x5] with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. 99 50 bc c2 fb 65 .. cc .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.4h}, [x5] with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. e6 45 98 4f 7f 3f 99 04 ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.8b}, [x5] with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 97 b2 c4
- [144] d8 5e dc 6a b7 .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.2d}, [x5] with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0e7683e67672f875 v17.d[0] (xor, xfer vecreg #1)
- 5849c62885094425 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.4s}, [x5] with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- cc566178b0505ce2 v17.d[0] (xor, xfer vecreg #1)
- 9ba578e187b7ec29 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.8h}, [x5] with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- f5a2c2db348d79c9 v17.d[0] (xor, xfer vecreg #1)
- 2d19eece1ac4cfe1 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.16b}, [x5] with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 2895e1c44e7d6375 v17.d[0] (xor, xfer vecreg #1)
- 68121b8e14fe75c3 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.1d}, [x5] with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 11488cce9b957a63 v17.d[0] (xor, xfer vecreg #1)
- a8e3a2dc36f2376f v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.2s}, [x5] with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- e400b2d8baf17a43 v17.d[0] (xor, xfer vecreg #1)
- 2ce128ce0966e831 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.4h}, [x5] with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- fad3b103f776773a v17.d[0] (xor, xfer vecreg #1)
- c2db8749219d644f v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.8b}, [x5] with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 1fb93f52acada1d3 v17.d[0] (xor, xfer vecreg #1)
- acc5a26005cccd1d v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LD1/ST1 (single structure, post index)
-st1 {v17.2d}, [x5], #16 with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. be 9f 67 38 8a 5a ae 31 9f 68 ea 98 79
- [144] 97 d9 93 .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.4s}, [x5], #16 with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. af df 1d d5 ec ca 0a 2c b4 22 83
- [144] 5d a8 8e 56 3d .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.8h}, [x5], #16 with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. ec a6 76 d8 d7 cd cc 1d f1
- [144] 42 d5 a2 31 e1 24 e2 .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.16b}, [x5], #16 with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 36 31 5c
- [144] 32 93 67 52 11 bd f9 5b 3f 75 e0 8e 03 .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. 44 79 62 32 a6 05 a4 be .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.2s}, [x5], #8 with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. 34 a3 95 cb c4 36 6f 9d .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.4h}, [x5], #8 with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 2f 3e 9a 97 bf 54 ee 97 ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.8b}, [x5], #8 with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 1d 51 72
- [144] a0 0d e9 38 8b .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.2d}, [x5], #16 with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 6856852b89835e57 v17.d[0] (xor, xfer vecreg #1)
- 926cd97a6fcb250a v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.4s}, [x5], #16 with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- d5d11520d94f1b33 v17.d[0] (xor, xfer vecreg #1)
- 5cbb554327b8a8e3 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.8h}, [x5], #16 with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- b9391b4ebce992b0 v17.d[0] (xor, xfer vecreg #1)
- 2aee8c5bebb07542 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.16b}, [x5], #16 with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 677b9246bea3c7b9 v17.d[0] (xor, xfer vecreg #1)
- c2cbc85912c50a5e v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 16 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 45c02b25ccc83819 v17.d[0] (xor, xfer vecreg #1)
- 979e4bd3158ec388 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.2s}, [x5], #8 with x5 = middle_of_block+5, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 17ce07c71f09fd99 v17.d[0] (xor, xfer vecreg #1)
- 09bc3bb12d99f56d v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.4h}, [x5], #8 with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- bb582a4317d4a712 v17.d[0] (xor, xfer vecreg #1)
- cc154357cca832ef v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1 {v17.8b}, [x5], #8 with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 843b172475108087 v17.d[0] (xor, xfer vecreg #1)
- 249f48da74ee9d60 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LD1R (single structure, replicate)
-ld1r {v17.2d}, [x5] with x5 = middle_of_block+3, x6=-5
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- f2660509f772e2c4 v17.d[0] (xor, xfer vecreg #1)
- 4ce39e650ae364b8 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.1d}, [x5] with x5 = middle_of_block+3, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 4e86be680cf6eb99 v17.d[0] (xor, xfer vecreg #1)
- a211d8c7f4f18c65 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.4s}, [x5] with x5 = middle_of_block+3, x6=-3
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 993c272115d4d6de v17.d[0] (xor, xfer vecreg #1)
- 34921415b16467d2 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.2s}, [x5] with x5 = middle_of_block+3, x6=-2
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- eec233adaef7ff96 v17.d[0] (xor, xfer vecreg #1)
- a4b40916ce41e41a v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.8h}, [x5] with x5 = middle_of_block+3, x6=-1
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 935cc2072eb1386a v17.d[0] (xor, xfer vecreg #1)
- 6613df7ee0c3d743 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.4h}, [x5] with x5 = middle_of_block+3, x6=1
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- c328131db4585dfa v17.d[0] (xor, xfer vecreg #1)
- 4926fd682180c520 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.16b}, [x5] with x5 = middle_of_block+3, x6=2
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- f087f060b8d625f7 v17.d[0] (xor, xfer vecreg #1)
- 870a7f81275fc7f6 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.8b}, [x5] with x5 = middle_of_block+3, x6=3
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- cf9a2fa5f98755c2 v17.d[0] (xor, xfer vecreg #1)
- b109d45d0d4c4d17 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.2d}, [x5], #8 with x5 = middle_of_block+3, x6=-5
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0c265c7984382b89 v17.d[0] (xor, xfer vecreg #1)
- e9b2ff4b2c9fcf1f v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- bdfdd39474eccc4f v17.d[0] (xor, xfer vecreg #1)
- fdfbad94b3469f9f v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 8 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.4s}, [x5], #4 with x5 = middle_of_block+3, x6=-3
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0bcc9003fe0271dc v17.d[0] (xor, xfer vecreg #1)
- 82366f42151d77f2 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 4 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.2s}, [x5], #4 with x5 = middle_of_block+3, x6=-2
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- c9fd7dc362339d38 v17.d[0] (xor, xfer vecreg #1)
- 4c9da8af320ed858 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 4 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.8h}, [x5], #2 with x5 = middle_of_block+3, x6=-1
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 9a6cf746f39749b4 v17.d[0] (xor, xfer vecreg #1)
- 870355d295f3be89 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 2 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.4h}, [x5], #2 with x5 = middle_of_block+3, x6=1
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 205edc63fd70f66d v17.d[0] (xor, xfer vecreg #1)
- be8fe64caa441ae1 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 2 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.16b}, [x5], #1 with x5 = middle_of_block+3, x6=2
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 163053439f6c0c42 v17.d[0] (xor, xfer vecreg #1)
- e601d1578762518f v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 1 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.8b}, [x5], #1 with x5 = middle_of_block+3, x6=3
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 85f87dd58efe3327 v17.d[0] (xor, xfer vecreg #1)
- 7470860d3c8884dc v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 1 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.2d}, [x5], x6 with x5 = middle_of_block+3, x6=-5
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 742ee30b26c3644a v17.d[0] (xor, xfer vecreg #1)
- 620afd520355620a v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -5 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.1d}, [x5], x6 with x5 = middle_of_block+3, x6=-4
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- d77f537144c905fd v17.d[0] (xor, xfer vecreg #1)
- 8de2a890077a37e7 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -4 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.4s}, [x5], x6 with x5 = middle_of_block+3, x6=-3
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 733c2c6280caff90 v17.d[0] (xor, xfer vecreg #1)
- 0bd32ad90eb64b11 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -3 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.2s}, [x5], x6 with x5 = middle_of_block+3, x6=-2
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 8f097b9699ca1fd8 v17.d[0] (xor, xfer vecreg #1)
- 2a846d762bba52a3 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -2 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.8h}, [x5], x6 with x5 = middle_of_block+3, x6=-1
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 64a4000905e8aa3e v17.d[0] (xor, xfer vecreg #1)
- 930f6607495e81b1 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- -1 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.4h}, [x5], x6 with x5 = middle_of_block+3, x6=1
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- a61deef2566f701d v17.d[0] (xor, xfer vecreg #1)
- 6af5f45fc9e7f5b0 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 1 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.16b}, [x5], x6 with x5 = middle_of_block+3, x6=2
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 3ad49e64bf2c15cb v17.d[0] (xor, xfer vecreg #1)
- ab04a19d6ae38e9d v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 2 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld1r {v17.8b}, [x5], x6 with x5 = middle_of_block+3, x6=3
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 47e6864987e1a4e7 v17.d[0] (xor, xfer vecreg #1)
- 6dd65eeb01a241ae v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 3 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LD2/ST2 (multiple 2-elem structs to/from 2/regs, post index) (VERY INCOMPLETE)
-ld2 {v17.2d, v18.2d}, [x5], #32 with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 16e55b1873ee34c3 v17.d[0] (xor, xfer vecreg #1)
- 34707980f120b864 v17.d[1] (xor, xfer vecreg #1)
- ba093b5d784363cf v18.d[0] (xor, xfer vecreg #2)
- 7111d1b5c20be11e v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st2 {v17.2d, v18.2d}, [x5], #32 with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 0e 3f 31 98 6e 90 de 8d 3f
- [144] ea 85 9a 2a e6 4c b8 d3 c7 c8 62 8c 43 99 75 2c
- [160] fe 89 33 25 52 9d a8 .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-ld2 {v17.4s, v18.4s}, [x5], #32 with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 1d1dad5f22f91503 v17.d[0] (xor, xfer vecreg #1)
- b57248c23e0baef6 v17.d[1] (xor, xfer vecreg #1)
- 05bbead3136a567d v18.d[0] (xor, xfer vecreg #2)
- baed025f106d8588 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st2 {v17.4s, v18.4s}, [x5], #32 with x5 = middle_of_block+17, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. cd 11 7d 61 05 62 71 d9 e4 fa ea f5 7b 7d c4
- [160] e5 8f 06 7e 21 0a c6 48 5a 02 12 03 3a 27 30 ff
- [176] c5 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LD1/ST1 (multiple 1-elem structs to/from 2 regs, no offset) (VERY INCOMPLETE)
-ld1 {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 683f58edc2f5f671 v17.d[0] (xor, xfer vecreg #1)
- 174e8d675cf2632a v17.d[1] (xor, xfer vecreg #1)
- 15633f2c6ebd44da v18.d[0] (xor, xfer vecreg #2)
- ab3a9c72639ef492 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. 49 .. .. a2 31 44 0c 57 db
- [144] df fe 73 d3 d7 67 7d ae da 61 fc b3 41 3a 20 e8
- [160] 95 ed 8a f3 1c 8a 7f .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LD1/ST1 (multiple 1-elem structs to/from 2 regs, post index) (VERY INCOMPLETE)
-ld1 {v17.16b, v18.16b}, [x5], #32 with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 9bf660d5bdff8c3c v17.d[0] (xor, xfer vecreg #1)
- a0ccbbec9ef6f2ca v17.d[1] (xor, xfer vecreg #1)
- 8303595518823d47 v18.d[0] (xor, xfer vecreg #2)
- 75f70396adc8eda8 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.16b, v18.16b}, [x5], #32 with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. d2 47 11 63 39 8e 47 81 6e
- [144] 46 95 76 6d ba 9e 22 ad b5 07 7b 8e e5 46 4e b2
- [160] b8 27 42 be 20 42 bf .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 32 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LD1/ST1 (multiple 1-elem structs to/from 3 regs, no offset) (VERY INCOMPLETE)
-ld1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+3, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- a9d70e88d1e89d30 v17.d[0] (xor, xfer vecreg #1)
- 478a0f9d90561d2b v17.d[1] (xor, xfer vecreg #1)
- 3e85525215476b1e v18.d[0] (xor, xfer vecreg #2)
- 353dc370e1ffd26a v18.d[1] (xor, xfer vecreg #2)
- 6f4831650bbf0b6a v19.d[0] (xor, xfer vecreg #3)
- 51807f1bc8292233 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+7, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. a3 7d e6 a1 06 24 44 85 4b
- [144] 7c b1 95 4b 4a d7 c1 f5 3e f1 b7 2d 92 94 93 c4
- [160] 69 68 57 cf 90 7d 39 5f 16 3a 12 93 0b b3 fd e7
- [176] ca eb da 1a f6 75 3d .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 0 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-LD3/ST3 (multiple 3-elem structs to/from 3/regs, post index) (VERY INCOMPLETE)
-ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+13, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 446f3899b211b6a0 v17.d[0] (xor, xfer vecreg #1)
- 6437eeb9f3204807 v17.d[1] (xor, xfer vecreg #1)
- 60e1161912e2876e v18.d[0] (xor, xfer vecreg #2)
- e1a4654ef78b7a07 v18.d[1] (xor, xfer vecreg #2)
- aed5a7373cd64d1f v19.d[0] (xor, xfer vecreg #3)
- 739aef5767e6aa1f v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 48 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
-st3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+17, x6=0
- [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [144] .. c5 1c bb 41 0f c0 bd f1 9b b6 ab 88 aa 17 31
- [160] 94 7d ee 24 ee 14 61 cd 93 9f 71 69 88 94 38 eb
- [176] 2f 75 95 31 3e 9e 0e 6c .. 58 4a a7 86 5e 21 08
- [192] c0 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
- 0000000000000000 x13 (xor, xfer intreg #1)
- 0000000000000000 x23 (xor, xfer intreg #2)
- 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
- 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
- 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
- 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
- 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
- 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
- 48 x5 (sub, base reg)
- 0 x6 (sub, index reg)
-
--- /dev/null
+
+/* To compile:
+ aarch64-linux-gnu-gcc -Wall -g -O0 -o memory none/tests/arm64/memory.c
+*/
+
+#include <stdio.h>
+#include <malloc.h> // memalign
+#include <string.h> // memset
+#include <assert.h>
+
+typedef unsigned char UChar;
+typedef unsigned short int UShort;
+typedef unsigned int UInt;
+typedef signed int Int;
+typedef unsigned char UChar;
+typedef signed long long int Long;
+typedef unsigned long long int ULong;
+
+typedef unsigned char Bool;
+#define False ((Bool)0)
+#define True ((Bool)1)
+
+__attribute__((noinline))
+static void* memalign16(size_t szB)
+{
+ void* x;
+ x = memalign(16, szB);
+ assert(x);
+ assert(0 == ((16-1) & (unsigned long)x));
+ return x;
+}
+
+static inline UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+static ULong randULong ( void )
+{
+ Int i;
+ ULong r = 0;
+ for (i = 0; i < 8; i++) {
+ r = (r << 8) | (ULong)(0xFF & randUChar());
+ }
+ return r;
+}
+
+
+// Same as TESTINST2 except it doesn't print the RN value, since
+// that may differ between runs (it's a stack address). Also,
+// claim it trashes x28 so that can be used as scratch if needed.
+#define TESTINST2_hide2(instruction, RNval, RD, RN, carryin) \
+{ \
+ ULong out; \
+ ULong nzcv_out; \
+ ULong nzcv_in = (carryin ? (1<<29) : 0); \
+ __asm__ __volatile__( \
+ "msr nzcv,%3;" \
+ "mov " #RN ",%2;" \
+ instruction ";" \
+ "mov %0," #RD ";" \
+ "mrs %1,nzcv;" \
+ : "=&r" (out), "=&r" (nzcv_out) \
+ : "r" (RNval), "r" (nzcv_in) \
+ : #RD, #RN, "cc", "memory", "x28" \
+ ); \
+ printf("%s :: rd %016llx rn (hidden), " \
+ "cin %d, nzcv %08llx %c%c%c%c\n", \
+ instruction, out, \
+ carryin ? 1 : 0, \
+ nzcv_out & 0xffff0000, \
+ ((1<<31) & nzcv_out) ? 'N' : ' ', \
+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \
+ ((1<<29) & nzcv_out) ? 'C' : ' ', \
+ ((1<<28) & nzcv_out) ? 'V' : ' ' \
+ ); \
+}
+
+#define TESTINST3_hide2and3(instruction, RMval, RNval, RD, RM, RN, carryin) \
+{ \
+ ULong out; \
+ ULong nzcv_out; \
+ ULong nzcv_in = (carryin ? (1<<29) : 0); \
+ __asm__ __volatile__( \
+ "msr nzcv,%4;" \
+ "mov " #RM ",%2;" \
+ "mov " #RN ",%3;" \
+ instruction ";" \
+ "mov %0," #RD ";" \
+ "mrs %1,nzcv;" \
+ : "=&r" (out), "=&r" (nzcv_out) \
+ : "r" (RMval), "r" (RNval), "r" (nzcv_in) \
+ : #RD, #RM, #RN, "cc", "memory" \
+ ); \
+ printf("%s :: rd %016llx rm (hidden), rn (hidden), " \
+ "cin %d, nzcv %08llx %c%c%c%c\n", \
+ instruction, out, \
+ carryin ? 1 : 0, \
+ nzcv_out & 0xffff0000, \
+ ((1<<31) & nzcv_out) ? 'N' : ' ', \
+ ((1<<30) & nzcv_out) ? 'Z' : ' ', \
+ ((1<<29) & nzcv_out) ? 'C' : ' ', \
+ ((1<<28) & nzcv_out) ? 'V' : ' ' \
+ ); \
+}
+
+
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+
+static __attribute((noinline)) void test_memory ( void )
+{
+printf("Integer loads\n");
+
+unsigned char area[512];
+
+#define RESET \
+ do { int i; for (i = 0; i < sizeof(area); i++) \
+ area[i] = i | 0x80; \
+ } while (0)
+
+#define AREA_MID (((ULong)(&area[(sizeof(area)/2)-1])) & (~(ULong)0xF))
+
+RESET;
+
+////////////////////////////////////////////////////////////////
+printf("LDR,STR (immediate, uimm12) (STR cases are MISSING)");
+TESTINST2_hide2("ldr x21, [x22, #24]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldr w21, [x22, #20]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrh w21, [x22, #44]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrb w21, [x22, #56]", AREA_MID, x21,x22,0);
+
+////////////////////////////////////////////////////////////////
+printf("LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)\n");
+TESTINST2_hide2("ldr x21, [x22], #-24", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldr x21, [x22, #-40]!", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldr x21, [x22, #-48]", AREA_MID, x21,x22,0);
+printf("LDUR,STUR (immediate, simm9): STR cases are MISSING");
+
+////////////////////////////////////////////////////////////////
+// TESTINST2_hide2 allows use of x28 as scratch
+printf("LDP,STP (immediate, simm7) (STR cases and wb check is MISSING)\n");
+
+TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp x21, x28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp x21, x28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+
+TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp w21, w28, [x22], #-24 ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; add x21,x21,x28", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldp w21, w28, [x22, #-40] ; eor x21,x21,x28", AREA_MID, x21,x22,0);
+
+////////////////////////////////////////////////////////////////
+// This is a bit tricky. We load the value from just before and
+// just after the actual instruction. Because TESTINSN2_hide2
+// generates two fixed insns either side of the test insn, these
+// should be constant and hence "safe" to check.
+
+printf("LDR (literal, int reg)\n");
+TESTINST2_hide2("xyzzy00: ldr x21, xyzzy00 - 8", AREA_MID, x21,x22,0);
+TESTINST2_hide2("xyzzy01: ldr x21, xyzzy01 + 0", AREA_MID, x21,x22,0);
+TESTINST2_hide2("xyzzy02: ldr x21, xyzzy02 + 8", AREA_MID, x21,x22,0);
+
+TESTINST2_hide2("xyzzy03: ldr x21, xyzzy03 - 4", AREA_MID, x21,x22,0);
+TESTINST2_hide2("xyzzy04: ldr x21, xyzzy04 + 0", AREA_MID, x21,x22,0);
+TESTINST2_hide2("xyzzy05: ldr x21, xyzzy05 + 4", AREA_MID, x21,x22,0);
+
+////////////////////////////////////////////////////////////////
+printf("{LD,ST}R (integer register) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LDRS{B,H,W} (uimm12)\n");
+TESTINST2_hide2("ldrsw x21, [x22, #24]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsh x21, [x22, #20]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsh w21, [x22, #44]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsb x21, [x22, #88]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsb w21, [x22, #56]", AREA_MID, x21,x22,0);
+
+////////////////////////////////////////////////////////////////
+printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n");
+TESTINST2_hide2("ldrsw x21, [x22, #-24]!", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsh x21, [x22, #-20]!", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsh w21, [x22, #-44]!", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsb x21, [x22, #-88]!", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsb w21, [x22, #-56]!", AREA_MID, x21,x22,0);
+
+TESTINST2_hide2("ldrsw x21, [x22], #-24", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsh x21, [x22], #-20", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsh w21, [x22], #-44", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsb x21, [x22], #-88", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsb w21, [x22], #-56", AREA_MID, x21,x22,0);
+
+////////////////////////////////////////////////////////////////
+printf("LDRS{B,H,W} (simm9, noUpd)\n");
+TESTINST2_hide2("ldrsw x21, [x22, #-24]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsh x21, [x22, #-20]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsh w21, [x22, #-44]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsb x21, [x22, #-88]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldrsb w21, [x22, #-56]", AREA_MID, x21,x22,0);
+
+////////////////////////////////////////////////////////////////
+printf("LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("{LD,ST}R (vector register) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LDRS{B,H,W} (integer register, SX)\n");
+
+TESTINST3_hide2and3("ldrsw x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsw x21, [x22,x23, lsl #2]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #2]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0);
+
+TESTINST3_hide2and3("ldrsh x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh x21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh x21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh x21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
+
+TESTINST3_hide2and3("ldrsh w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh w21, [x22,x23, lsl #1]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh w21, [x22,w23,uxtw #1]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsh w21, [x22,w23,sxtw #1]", AREA_MID, -5ULL, x21,x22,x23,0);
+
+TESTINST3_hide2and3("ldrsb x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb x21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
+
+TESTINST3_hide2and3("ldrsb w21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb w21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb w21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
+TESTINST3_hide2and3("ldrsb w21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
+
+////////////////////////////////////////////////////////////////
+printf("LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LD1/ST1 (single structure, no offset) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LD1/ST1 (single structure, post index) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LD{,A}X{R,RH,RB} (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("ST{,L}X{R,RH,RB} (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LDA{R,RH,RB}\n");
+TESTINST2_hide2("ldar x21, [x22]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldar w21, [x22]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldarh w21, [x22]", AREA_MID, x21,x22,0);
+TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0);
+
+////////////////////////////////////////////////////////////////
+printf("STL{R,RH,RB} (entirely MISSING)\n");
+
+} /* end of test_memory() */
+
+
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+
+static void show_block_xor ( UChar* block1, UChar* block2, Int n )
+{
+ Int i;
+ printf(" ");
+ for (i = 0; i < n; i++) {
+ if (i > 0 && 0 == (i & 15)) printf("\n ");
+ if (0 == (i & 15)) printf("[%3d] ", i);
+ UInt diff = 0xFF & (UInt)(block1[i] - block2[i]);
+ if (diff == 0)
+ printf(".. ");
+ else
+ printf("%02x ", diff);
+ }
+ printf("\n");
+}
+
+
+// In: rand:
+// memory area, xferred vec regs, xferred int regs,
+// caller spec:
+// addr reg1, addr reg2
+//
+// Out: memory area, xferred vec regs, xferred int regs, addr reg1, addr reg2
+//
+// INSN may mention the following regs as containing load/store data:
+// x13 x23 v17 v18 v19 v20
+// and
+// x5 as containing the base address
+// x6 as containing an offset, if required
+// A memory area is filled with random data, and x13, x23, v17, v18, v19, v20
+// are loaded with random data too. INSN is then executed, with
+// x5 set to the middle of the memory area + AREG1OFF, and x6 set to AREG2VAL.
+//
+// What is printed out: the XOR of the new and old versions of the
+// following:
+// the memory area
+// x13 x23 v17 v18 v19 v20
+// and the SUB of the new and old values of the following:
+// x5 x6
+// If the insn modifies its base register then (obviously) the x5 "new - old"
+// value will be nonzero.
+
+#define MEM_TEST(INSN, AREG1OFF, AREG2VAL) { \
+ int i; \
+ const int N = 256; \
+ UChar* area = memalign16(N); \
+ UChar area2[N]; \
+ for (i = 0; i < N; i++) area[i] = area2[i] = randUChar(); \
+ ULong block[12]; \
+ /* 0:x13 1:x23 2:v17.d[0] 3:v17.d[1] 4:v18.d[0] 5:v18.d[1] */ \
+ /* 6:v19.d[0] 7:v19.d[1] 8:v20.d[0] 9:v20.d[1] 10:x5 11:x6 */ \
+ for (i = 0; i < 12; i++) block[i] = randULong(); \
+ block[10] = (ULong)(&area[128]) + (Long)(Int)AREG1OFF; \
+ block[11] = (Long)AREG2VAL; \
+ ULong block2[12]; \
+ for (i = 0; i < 12; i++) block2[i] = block[i]; \
+ __asm__ __volatile__( \
+ "ldr x13, [%0, #0] ; " \
+ "ldr x23, [%0, #8] ; " \
+ "ldr q17, [%0, #16] ; " \
+ "ldr q18, [%0, #32] ; " \
+ "ldr q19, [%0, #48] ; " \
+ "ldr q20, [%0, #64] ; " \
+ "ldr x5, [%0, #80] ; " \
+ "ldr x6, [%0, #88] ; " \
+ INSN " ; " \
+ "str x13, [%0, #0] ; " \
+ "str x23, [%0, #8] ; " \
+ "str q17, [%0, #16] ; " \
+ "str q18, [%0, #32] ; " \
+ "str q19, [%0, #48] ; " \
+ "str q20, [%0, #64] ; " \
+ "str x5, [%0, #80] ; " \
+ "str x6, [%0, #88] ; " \
+ : : "r"(&block[0]) : "x5", "x6", "x13", "x23", \
+ "v17", "v18", "v19", "v20", "memory", "cc" \
+ ); \
+ printf("%s with x5 = middle_of_block+%lld, x6=%lld\n", \
+ INSN, (Long)AREG1OFF, (Long)AREG2VAL); \
+ show_block_xor(&area2[0], area, 256); \
+ printf(" %016llx x13 (xor, xfer intreg #1)\n", block[0] ^ block2[0]); \
+ printf(" %016llx x23 (xor, xfer intreg #2)\n", block[1] ^ block2[1]); \
+ printf(" %016llx v17.d[0] (xor, xfer vecreg #1)\n", block[2] ^ block2[2]); \
+ printf(" %016llx v17.d[1] (xor, xfer vecreg #1)\n", block[3] ^ block2[3]); \
+ printf(" %016llx v18.d[0] (xor, xfer vecreg #2)\n", block[4] ^ block2[4]); \
+ printf(" %016llx v18.d[1] (xor, xfer vecreg #2)\n", block[5] ^ block2[5]); \
+ printf(" %016llx v19.d[0] (xor, xfer vecreg #3)\n", block[6] ^ block2[6]); \
+ printf(" %016llx v19.d[1] (xor, xfer vecreg #3)\n", block[7] ^ block2[7]); \
+ printf(" %016llx v20.d[0] (xor, xfer vecreg #3)\n", block[8] ^ block2[8]); \
+ printf(" %016llx v20.d[1] (xor, xfer vecreg #3)\n", block[9] ^ block2[9]); \
+ printf(" %16lld x5 (sub, base reg)\n", block[10] - block2[10]); \
+ printf(" %16lld x6 (sub, index reg)\n", block[11] - block2[11]); \
+ printf("\n"); \
+ free(area); \
+ }
+
+static __attribute__((noinline)) void test_memory2 ( void )
+{
+////////////////////////////////////////////////////////////////
+printf("LDR,STR (immediate, uimm12)");
+MEM_TEST("ldr x13, [x5, #24]", -1, 0);
+MEM_TEST("ldr w13, [x5, #20]", 1, 0);
+MEM_TEST("ldrh w13, [x5, #44]", 2, 0);
+MEM_TEST("ldrb w13, [x5, #56]", 3, 0);
+MEM_TEST("str x13, [x5, #24]", -3, 0);
+MEM_TEST("str w13, [x5, #20]", 5, 0);
+MEM_TEST("strh w13, [x5, #44]", 6, 0);
+MEM_TEST("strb w13, [x5, #56]", 7, 0);
+
+////////////////////////////////////////////////////////////////
+printf("LDUR,STUR (immediate, simm9)\n");
+MEM_TEST("ldr x13, [x5], #-24", 0, 0);
+MEM_TEST("ldr x13, [x5, #-40]!", 0, 0);
+MEM_TEST("ldr x13, [x5, #-48]", 0, 0);
+MEM_TEST("str x13, [x5], #-24", 0, 0);
+MEM_TEST("str x13, [x5, #-40]!", 0, 0);
+MEM_TEST("str x13, [x5, #-48]", 0, 0);
+
+////////////////////////////////////////////////////////////////
+printf("LDP,STP (immediate, simm7)\n");
+MEM_TEST("ldp x13, x23, [x5], #-24", 0, 0);
+MEM_TEST("ldp x13, x23, [x5, #-40]!", 0, 0);
+MEM_TEST("ldp x13, x23, [x5, #-40]", 0, 0);
+MEM_TEST("stp x13, x23, [x5], #-24", 0, 0);
+MEM_TEST("stp x13, x23, [x5, #-40]!", 0, 0);
+MEM_TEST("stp x13, x23, [x5, #-40]", 0, 0);
+
+MEM_TEST("ldp w13, w23, [x5], #-24", 0, 0);
+MEM_TEST("ldp w13, w23, [x5, #-40]!", 0, 0);
+MEM_TEST("ldp w13, w23, [x5, #-40]", 0, 0);
+MEM_TEST("stp w13, w23, [x5], #-24", 0, 0);
+MEM_TEST("stp w13, w23, [x5, #-40]!", 0, 0);
+MEM_TEST("stp w13, w23, [x5, #-40]", 0, 0);
+
+////////////////////////////////////////////////////////////////
+printf("LDR (literal, int reg) (DONE ABOVE)\n");
+
+////////////////////////////////////////////////////////////////
+printf("{LD,ST}R (integer register) (entirely MISSING)\n");
+MEM_TEST("str x13, [x5, x6]", 12, -4);
+MEM_TEST("str x13, [x5, x6, lsl #3]", 12, -4);
+MEM_TEST("str x13, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("str x13, [x5, w6, uxtw #3]", 12, 4);
+MEM_TEST("str x13, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("str x13, [x5, w6, sxtw #3]", 12, -4);
+MEM_TEST("ldr x13, [x5, x6]", 12, -4);
+MEM_TEST("ldr x13, [x5, x6, lsl #3]", 12, -4);
+MEM_TEST("ldr x13, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldr x13, [x5, w6, uxtw #3]", 12, 4);
+MEM_TEST("ldr x13, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldr x13, [x5, w6, sxtw #3]", 12, -4);
+
+MEM_TEST("str w13, [x5, x6]", 12, -4);
+MEM_TEST("str w13, [x5, x6, lsl #2]", 12, -4);
+MEM_TEST("str w13, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("str w13, [x5, w6, uxtw #2]", 12, 4);
+MEM_TEST("str w13, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("str w13, [x5, w6, sxtw #2]", 12, -4);
+MEM_TEST("ldr w13, [x5, x6]", 12, -4);
+MEM_TEST("ldr w13, [x5, x6, lsl #2]", 12, -4);
+MEM_TEST("ldr w13, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldr w13, [x5, w6, uxtw #2]", 12, 4);
+MEM_TEST("ldr w13, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldr w13, [x5, w6, sxtw #2]", 12, -4);
+
+MEM_TEST("strh w13, [x5, x6]", 12, -4);
+MEM_TEST("strh w13, [x5, x6, lsl #1]", 12, -4);
+MEM_TEST("strh w13, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("strh w13, [x5, w6, uxtw #1]", 12, 4);
+MEM_TEST("strh w13, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("strh w13, [x5, w6, sxtw #1]", 12, -4);
+MEM_TEST("ldrh w13, [x5, x6]", 12, -4);
+MEM_TEST("ldrh w13, [x5, x6, lsl #1]", 12, -4);
+MEM_TEST("ldrh w13, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldrh w13, [x5, w6, uxtw #1]", 12, 4);
+MEM_TEST("ldrh w13, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldrh w13, [x5, w6, sxtw #1]", 12, -4);
+
+MEM_TEST("strb w13, [x5, x6]", 12, -4);
+MEM_TEST("strb w13, [x5, x6, lsl #0]", 12, -4);
+MEM_TEST("strb w13, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("strb w13, [x5, w6, uxtw #0]", 12, 4);
+MEM_TEST("strb w13, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("strb w13, [x5, w6, sxtw #0]", 12, -4);
+MEM_TEST("ldrb w13, [x5, x6]", 12, -4);
+MEM_TEST("ldrb w13, [x5, x6, lsl #0]", 12, -4);
+MEM_TEST("ldrb w13, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldrb w13, [x5, w6, uxtw #0]", 12, 4);
+MEM_TEST("ldrb w13, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldrb w13, [x5, w6, sxtw #0]", 12, -4);
+
+////////////////////////////////////////////////////////////////
+printf("LDRS{B,H,W} (uimm12)\n");
+MEM_TEST("ldrsw x13, [x5, #24]", -16, 4);
+MEM_TEST("ldrsh x13, [x5, #20]", -16, 4);
+MEM_TEST("ldrsh w13, [x5, #44]", -16, 4);
+MEM_TEST("ldrsb x13, [x5, #72]", -16, 4);
+MEM_TEST("ldrsb w13, [x5, #56]", -16, 4);
+
+////////////////////////////////////////////////////////////////
+printf("LDRS{B,H,W} (simm9, upd) (upd check is MISSING)\n");
+MEM_TEST("ldrsw x13, [x5, #-24]!", -16, 4);
+MEM_TEST("ldrsh x13, [x5, #-20]!", -16, 4);
+MEM_TEST("ldrsh w13, [x5, #-44]!", -16, 4);
+MEM_TEST("ldrsb x13, [x5, #-72]!", -16, 4);
+MEM_TEST("ldrsb w13, [x5, #-56]!", -16, 4);
+
+MEM_TEST("ldrsw x13, [x5], #-24", -16, 4);
+MEM_TEST("ldrsh x13, [x5], #-20", -16, 4);
+MEM_TEST("ldrsh w13, [x5], #-44", -16, 4);
+MEM_TEST("ldrsb x13, [x5], #-72", -16, 4);
+MEM_TEST("ldrsb w13, [x5], #-56", -16, 4);
+
+////////////////////////////////////////////////////////////////
+printf("LDRS{B,H,W} (simm9, noUpd)\n");
+MEM_TEST("ldrsw x13, [x5, #-24]", -16, 4);
+MEM_TEST("ldrsh x13, [x5, #-20]", -16, 4);
+MEM_TEST("ldrsh w13, [x5, #-44]", -16, 4);
+MEM_TEST("ldrsb x13, [x5, #-72]", -16, 4);
+MEM_TEST("ldrsb w13, [x5, #-56]", -16, 4);
+
+////////////////////////////////////////////////////////////////
+printf("LDP,STP (immediate, simm7) (FP&VEC)\n");
+
+MEM_TEST("stp q17, q18, [x5, 32]", -16, 4);
+MEM_TEST("stp q17, q18, [x5, 32]!", -16, 4);
+MEM_TEST("stp q17, q18, [x5], 32", -16, 4);
+
+MEM_TEST("stp d17, d18, [x5, 32]", -16, 4);
+MEM_TEST("stp d17, d18, [x5, 32]!", -16, 4);
+MEM_TEST("stp d17, d18, [x5], 32", -16, 4);
+
+//MEM_TEST("stp s17, s18, [x5, 32]", -16, 4);
+//MEM_TEST("stp s17, s18, [x5, 32]!", -16, 4);
+//MEM_TEST("stp s17, s18, [x5], 32", -16, 4);
+
+MEM_TEST("ldp q17, q18, [x5, 32]", -16, 4);
+MEM_TEST("ldp q17, q18, [x5, 32]!", -16, 4);
+MEM_TEST("ldp q17, q18, [x5], 32", -16, 4);
+
+MEM_TEST("ldp d17, d18, [x5, 32]", -16, 4);
+MEM_TEST("ldp d17, d18, [x5, 32]!", -16, 4);
+MEM_TEST("ldp d17, d18, [x5], 32", -16, 4);
+
+//MEM_TEST("ldp s17, s18, [x5, 32]", -16, 4);
+//MEM_TEST("ldp s17, s18, [x5, 32]!", -16, 4);
+//MEM_TEST("ldp s17, s18, [x5], 32", -16, 4);
+
+////////////////////////////////////////////////////////////////
+printf("{LD,ST}R (vector register)\n");
+
+#if 0
+MEM_TEST("str q17, [x5, x6]", 12, -4);
+MEM_TEST("str q17, [x5, x6, lsl #4]", 12, -4);
+MEM_TEST("str q17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("str q17, [x5, w6, uxtw #4]", 12, 4);
+MEM_TEST("str q17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("str q17, [x5, w6, sxtw #4]", 12, -4);
+MEM_TEST("ldr q17, [x5, x6]", 12, -4);
+MEM_TEST("ldr q17, [x5, x6, lsl #4]", 12, -4);
+MEM_TEST("ldr q17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldr q17, [x5, w6, uxtw #4]", 12, 4);
+MEM_TEST("ldr q17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldr q17, [x5, w6, sxtw #4]", 12, -4);
+#endif
+
+MEM_TEST("str d17, [x5, x6]", 12, -4);
+MEM_TEST("str d17, [x5, x6, lsl #3]", 12, -4);
+MEM_TEST("str d17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("str d17, [x5, w6, uxtw #3]", 12, 4);
+MEM_TEST("str d17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("str d17, [x5, w6, sxtw #3]", 12, -4);
+MEM_TEST("ldr d17, [x5, x6]", 12, -4);
+MEM_TEST("ldr d17, [x5, x6, lsl #3]", 12, -4);
+MEM_TEST("ldr d17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldr d17, [x5, w6, uxtw #3]", 12, 4);
+MEM_TEST("ldr d17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldr d17, [x5, w6, sxtw #3]", 12, -4);
+
+MEM_TEST("str s17, [x5, x6]", 12, -4);
+MEM_TEST("str s17, [x5, x6, lsl #2]", 12, -4);
+MEM_TEST("str s17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("str s17, [x5, w6, uxtw #2]", 12, 4);
+MEM_TEST("str s17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("str s17, [x5, w6, sxtw #2]", 12, -4);
+MEM_TEST("ldr s17, [x5, x6]", 12, -4);
+MEM_TEST("ldr s17, [x5, x6, lsl #2]", 12, -4);
+MEM_TEST("ldr s17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldr s17, [x5, w6, uxtw #2]", 12, 4);
+MEM_TEST("ldr s17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldr s17, [x5, w6, sxtw #2]", 12, -4);
+
+#if 0
+MEM_TEST("str h17, [x5, x6]", 12, -4);
+MEM_TEST("str h17, [x5, x6, lsl #1]", 12, -4);
+MEM_TEST("str h17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("str h17, [x5, w6, uxtw #1]", 12, 4);
+MEM_TEST("str h17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("str h17, [x5, w6, sxtw #1]", 12, -4);
+MEM_TEST("ldr h17, [x5, x6]", 12, -4);
+MEM_TEST("ldr h17, [x5, x6, lsl #1]", 12, -4);
+MEM_TEST("ldr h17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldr h17, [x5, w6, uxtw #1]", 12, 4);
+MEM_TEST("ldr h17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldr h17, [x5, w6, sxtw #1]", 12, -4);
+
+MEM_TEST("str b17, [x5, x6]", 12, -4);
+MEM_TEST("str b17, [x5, x6, lsl #0]", 12, -4);
+MEM_TEST("str b17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("str b17, [x5, w6, uxtw #0]", 12, 4);
+MEM_TEST("str b17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("str b17, [x5, w6, sxtw #0]", 12, -4);
+MEM_TEST("ldr b17, [x5, x6]", 12, -4);
+MEM_TEST("ldr b17, [x5, x6, lsl #0]", 12, -4);
+MEM_TEST("ldr b17, [x5, w6, uxtw]", 12, 4);
+MEM_TEST("ldr b17, [x5, w6, uxtw #0]", 12, 4);
+MEM_TEST("ldr b17, [x5, w6, sxtw]", 12, 4);
+MEM_TEST("ldr b17, [x5, w6, sxtw #0]", 12, -4);
+#endif
+
+////////////////////////////////////////////////////////////////
+printf("LDRS{B,H,W} (integer register, SX)\n");
+
+MEM_TEST("ldrsw x13, [x5,x6]", 12, -4);
+MEM_TEST("ldrsw x13, [x5,x6, lsl #2]", 12, -4);
+MEM_TEST("ldrsw x13, [x5,w6,uxtw #0]", 12, 4);
+MEM_TEST("ldrsw x13, [x5,w6,uxtw #2]", 12, 4);
+MEM_TEST("ldrsw x13, [x5,w6,sxtw #0]", 12, 4);
+MEM_TEST("ldrsw x13, [x5,w6,sxtw #2]", 12, -4);
+
+MEM_TEST("ldrsh x13, [x5,x6]", 12, -4);
+MEM_TEST("ldrsh x13, [x5,x6, lsl #1]", 12, -4);
+MEM_TEST("ldrsh x13, [x5,w6,uxtw #0]", 12, 4);
+MEM_TEST("ldrsh x13, [x5,w6,uxtw #1]", 12, 4);
+MEM_TEST("ldrsh x13, [x5,w6,sxtw #0]", 12, 4);
+MEM_TEST("ldrsh x13, [x5,w6,sxtw #1]", 12, -4);
+
+MEM_TEST("ldrsh w13, [x5,x6]", 12, -4);
+MEM_TEST("ldrsh w13, [x5,x6, lsl #1]", 12, -4);
+MEM_TEST("ldrsh w13, [x5,w6,uxtw #0]", 12, 4);
+MEM_TEST("ldrsh w13, [x5,w6,uxtw #1]", 12, 4);
+MEM_TEST("ldrsh w13, [x5,w6,sxtw #0]", 12, 4);
+MEM_TEST("ldrsh w13, [x5,w6,sxtw #1]", 12, -4);
+
+MEM_TEST("ldrsb x13, [x5,x6]", 12, -4);
+MEM_TEST("ldrsb x13, [x5,x6, lsl #0]", 12, -4);
+MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
+MEM_TEST("ldrsb x13, [x5,w6,uxtw #0]", 12, 4);
+MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, 4);
+MEM_TEST("ldrsb x13, [x5,w6,sxtw #0]", 12, -4);
+
+MEM_TEST("ldrsb w13, [x5,x6]", 12, -4);
+MEM_TEST("ldrsb w13, [x5,x6, lsl #0]", 12, -4);
+MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
+MEM_TEST("ldrsb w13, [x5,w6,uxtw #0]", 12, 4);
+MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, 4);
+MEM_TEST("ldrsb w13, [x5,w6,sxtw #0]", 12, -4);
+
+
+////////////////////////////////////////////////////////////////
+printf("LDR/STR (immediate, SIMD&FP, unsigned offset)\n");
+MEM_TEST("str q17, [x5, #-32]", 16, 0);
+MEM_TEST("str d17, [x5, #-32]", 16, 0);
+MEM_TEST("str s17, [x5, #-32]", 16, 0);
+//MEM_TEST("str h17, [x5, #-32]", 16, 0);
+//MEM_TEST("str b17, [x5, #-32]", 16, 0);
+MEM_TEST("ldr q17, [x5, #-32]", 16, 0);
+MEM_TEST("ldr d17, [x5, #-32]", 16, 0);
+MEM_TEST("ldr s17, [x5, #-32]", 16, 0);
+//MEM_TEST("ldr h17, [x5, #-32]", 16, 0);
+//MEM_TEST("ldr b17, [x5, #-32]", 16, 0);
+
+////////////////////////////////////////////////////////////////
+printf("LDR/STR (immediate, SIMD&FP, pre/post index)\n");
+MEM_TEST("str q17, [x5], #-32", 16, 0);
+MEM_TEST("str d17, [x5], #-32", 16, 0);
+MEM_TEST("str s17, [x5], #-32", 16, 0);
+//MEM_TEST("str h17, [x5], #-32", 16, 0);
+//MEM_TEST("str b17, [x5], #-32", 16, 0);
+MEM_TEST("ldr q17, [x5], #-32", 16, 0);
+MEM_TEST("ldr d17, [x5], #-32", 16, 0);
+MEM_TEST("ldr s17, [x5], #-32", 16, 0);
+//MEM_TEST("ldr h17, [x5], #-32", 16, 0);
+//MEM_TEST("ldr b17, [x5], #-32", 16, 0);
+
+MEM_TEST("str q17, [x5, #-32]!", 16, 0);
+MEM_TEST("str d17, [x5, #-32]!", 16, 0);
+MEM_TEST("str s17, [x5, #-32]!", 16, 0);
+//MEM_TEST("str h17, [x5, #-32]!", 16, 0);
+//MEM_TEST("str b17, [x5, #-32]!", 16, 0);
+MEM_TEST("ldr q17, [x5, #-32]!", 16, 0);
+MEM_TEST("ldr d17, [x5, #-32]!", 16, 0);
+MEM_TEST("ldr s17, [x5, #-32]!", 16, 0);
+//MEM_TEST("ldr h17, [x5, #-32]!", 16, 0);
+//MEM_TEST("ldr b17, [x5, #-32]!", 16, 0);
+
+
+////////////////////////////////////////////////////////////////
+printf("LDUR/STUR (unscaled offset, SIMD&FP)\n");
+MEM_TEST("str q17, [x5, #-13]", 16, 0);
+MEM_TEST("str d17, [x5, #-13]", 16, 0);
+MEM_TEST("str s17, [x5, #-13]", 16, 0);
+//MEM_TEST("str h17, [x5, #-13]", 16, 0);
+//MEM_TEST("str b17, [x5, #-13]", 16, 0);
+MEM_TEST("ldr q17, [x5, #-13]", 16, 0);
+MEM_TEST("ldr d17, [x5, #-13]", 16, 0);
+MEM_TEST("ldr s17, [x5, #-13]", 16, 0);
+//MEM_TEST("ldr h17, [x5, #-13]", 16, 0);
+//MEM_TEST("ldr b17, [x5, #-13]", 16, 0);
+
+////////////////////////////////////////////////////////////////
+printf("LDR (literal, SIMD&FP) (entirely MISSING)\n");
+
+////////////////////////////////////////////////////////////////
+printf("LD1/ST1 (single structure, no offset)\n");
+MEM_TEST("st1 {v17.2d}, [x5]", 3, 0)
+MEM_TEST("st1 {v17.4s}, [x5]", 5, 0)
+MEM_TEST("st1 {v17.8h}, [x5]", 7, 0)
+MEM_TEST("st1 {v17.16b}, [x5]", 13, 0)
+MEM_TEST("st1 {v17.1d}, [x5]", 3, 0)
+MEM_TEST("st1 {v17.2s}, [x5]", 5, 0)
+MEM_TEST("st1 {v17.4h}, [x5]", 7, 0)
+MEM_TEST("st1 {v17.8b}, [x5]", 13, 0)
+
+MEM_TEST("ld1 {v17.2d}, [x5]", 3, 0)
+MEM_TEST("ld1 {v17.4s}, [x5]", 5, 0)
+MEM_TEST("ld1 {v17.8h}, [x5]", 7, 0)
+MEM_TEST("ld1 {v17.16b}, [x5]", 13, 0)
+MEM_TEST("ld1 {v17.1d}, [x5]", 3, 0)
+MEM_TEST("ld1 {v17.2s}, [x5]", 5, 0)
+MEM_TEST("ld1 {v17.4h}, [x5]", 7, 0)
+MEM_TEST("ld1 {v17.8b}, [x5]", 13, 0)
+
+////////////////////////////////////////////////////////////////
+printf("LD1/ST1 (single structure, post index)\n");
+MEM_TEST("st1 {v17.2d}, [x5], #16", 3, 0)
+MEM_TEST("st1 {v17.4s}, [x5], #16", 5, 0)
+MEM_TEST("st1 {v17.8h}, [x5], #16", 7, 0)
+MEM_TEST("st1 {v17.16b}, [x5], #16", 13, 0)
+MEM_TEST("st1 {v17.1d}, [x5], #8", 3, 0)
+MEM_TEST("st1 {v17.2s}, [x5], #8", 5, 0)
+MEM_TEST("st1 {v17.4h}, [x5], #8", 7, 0)
+MEM_TEST("st1 {v17.8b}, [x5], #8", 13, 0)
+
+MEM_TEST("ld1 {v17.2d}, [x5], #16", 3, 0)
+MEM_TEST("ld1 {v17.4s}, [x5], #16", 5, 0)
+MEM_TEST("ld1 {v17.8h}, [x5], #16", 7, 0)
+MEM_TEST("ld1 {v17.16b}, [x5], #16", 13, 0)
+MEM_TEST("ld1 {v17.1d}, [x5], #8", 3, 0)
+MEM_TEST("ld1 {v17.2s}, [x5], #8", 5, 0)
+MEM_TEST("ld1 {v17.4h}, [x5], #8", 7, 0)
+MEM_TEST("ld1 {v17.8b}, [x5], #8", 13, 0)
+
+////////////////////////////////////////////////////////////////
+printf("LD1R (single structure, replicate)\n");
+MEM_TEST("ld1r {v17.2d}, [x5]", 3, -5)
+MEM_TEST("ld1r {v17.1d}, [x5]", 3, -4)
+MEM_TEST("ld1r {v17.4s}, [x5]", 3, -3)
+MEM_TEST("ld1r {v17.2s}, [x5]", 3, -2)
+MEM_TEST("ld1r {v17.8h}, [x5]", 3, -1)
+MEM_TEST("ld1r {v17.4h}, [x5]", 3, 1)
+MEM_TEST("ld1r {v17.16b}, [x5]", 3, 2)
+MEM_TEST("ld1r {v17.8b}, [x5]", 3, 3)
+
+MEM_TEST("ld1r {v17.2d}, [x5], #8", 3, -5)
+MEM_TEST("ld1r {v17.1d}, [x5], #8", 3, -4)
+MEM_TEST("ld1r {v17.4s}, [x5], #4", 3, -3)
+MEM_TEST("ld1r {v17.2s}, [x5], #4", 3, -2)
+MEM_TEST("ld1r {v17.8h}, [x5], #2", 3, -1)
+MEM_TEST("ld1r {v17.4h}, [x5], #2", 3, 1)
+MEM_TEST("ld1r {v17.16b}, [x5], #1", 3, 2)
+MEM_TEST("ld1r {v17.8b}, [x5], #1", 3, 3)
+
+MEM_TEST("ld1r {v17.2d}, [x5], x6", 3, -5)
+MEM_TEST("ld1r {v17.1d}, [x5], x6", 3, -4)
+MEM_TEST("ld1r {v17.4s}, [x5], x6", 3, -3)
+MEM_TEST("ld1r {v17.2s}, [x5], x6", 3, -2)
+MEM_TEST("ld1r {v17.8h}, [x5], x6", 3, -1)
+MEM_TEST("ld1r {v17.4h}, [x5], x6", 3, 1)
+MEM_TEST("ld1r {v17.16b}, [x5], x6", 3, 2)
+MEM_TEST("ld1r {v17.8b}, [x5], x6", 3, 3)
+
+////////////////////////////////////////////////////////////////
+printf("LD2/ST2 (multiple 2-elem structs to/from 2/regs, post index)"
+ " (VERY INCOMPLETE)\n");
+
+MEM_TEST("ld2 {v17.2d, v18.2d}, [x5], #32", 3, 0)
+MEM_TEST("st2 {v17.2d, v18.2d}, [x5], #32", 7, 0)
+
+MEM_TEST("ld2 {v17.4s, v18.4s}, [x5], #32", 13, 0)
+MEM_TEST("st2 {v17.4s, v18.4s}, [x5], #32", 17, 0)
+
+
+////////////////////////////////////////////////////////////////
+printf("LD1/ST1 (multiple 1-elem structs to/from 2 regs, no offset)"
+ " (VERY INCOMPLETE)\n");
+
+MEM_TEST("ld1 {v17.16b, v18.16b}, [x5]", 3, 0)
+MEM_TEST("st1 {v17.16b, v18.16b}, [x5]", 7, 0)
+
+
+////////////////////////////////////////////////////////////////
+printf("LD1/ST1 (multiple 1-elem structs to/from 2 regs, post index)"
+ " (VERY INCOMPLETE)\n");
+
+MEM_TEST("ld1 {v17.16b, v18.16b}, [x5], #32", 3, 0)
+MEM_TEST("st1 {v17.16b, v18.16b}, [x5], #32", 7, 0)
+
+
+////////////////////////////////////////////////////////////////
+printf("LD1/ST1 (multiple 1-elem structs to/from 3 regs, no offset)"
+ " (VERY INCOMPLETE)\n");
+
+MEM_TEST("ld1 {v17.16b, v18.16b, v19.16b}, [x5]", 3, 0)
+MEM_TEST("st1 {v17.16b, v18.16b, v19.16b}, [x5]", 7, 0)
+
+
+////////////////////////////////////////////////////////////////
+printf("LD3/ST3 (multiple 3-elem structs to/from 3/regs, post index)"
+ " (VERY INCOMPLETE)\n");
+
+MEM_TEST("ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 13, 0)
+MEM_TEST("st3 {v17.2d, v18.2d, v19.2d}, [x5], #48", 17, 0)
+
+
+
+} /* end of test_memory2() */
+
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+////////////////////////////////////////////////////////////////
+
+int main ( void )
+{
+ if (1) test_memory();
+ if (1) test_memory2();
+ return 0;
+}
--- /dev/null
+Integer loads
+LDR,STR (immediate, uimm12) (STR cases are MISSING)ldr x21, [x22, #24] :: rd 8f8e8d8c8b8a8988 rn (hidden), cin 0, nzcv 00000000
+ldr w21, [x22, #20] :: rd 0000000087868584 rn (hidden), cin 0, nzcv 00000000
+ldrh w21, [x22, #44] :: rd 0000000000009d9c rn (hidden), cin 0, nzcv 00000000
+ldrb w21, [x22, #56] :: rd 00000000000000a8 rn (hidden), cin 0, nzcv 00000000
+LDUR,STUR (immediate, simm9) (STR cases and wb check are MISSING)
+ldr x21, [x22], #-24 :: rd f7f6f5f4f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
+ldr x21, [x22, #-40]! :: rd cfcecdcccbcac9c8 rn (hidden), cin 0, nzcv 00000000
+ldr x21, [x22, #-48] :: rd c7c6c5c4c3c2c1c0 rn (hidden), cin 0, nzcv 00000000
+LDUR,STUR (immediate, simm9): STR cases are MISSINGLDP,STP (immediate, simm7) (STR cases and wb check is MISSING)
+ldp x21, x28, [x22], #-24 ; add x21,x21,x28 :: rd f7f5f3f1efedebe8 rn (hidden), cin 0, nzcv 00000000
+ldp x21, x28, [x22], #-24 ; eor x21,x21,x28 :: rd 0808080808080808 rn (hidden), cin 0, nzcv 00000000
+ldp x21, x28, [x22, #-40]! ; add x21,x21,x28 :: rd a7a5a3a19f9d9b98 rn (hidden), cin 0, nzcv 00000000
+ldp x21, x28, [x22, #-40]! ; eor x21,x21,x28 :: rd 1818181818181818 rn (hidden), cin 0, nzcv 00000000
+ldp x21, x28, [x22, #-40] ; add x21,x21,x28 :: rd a7a5a3a19f9d9b98 rn (hidden), cin 0, nzcv 00000000
+ldp x21, x28, [x22, #-40] ; eor x21,x21,x28 :: rd 1818181818181818 rn (hidden), cin 0, nzcv 00000000
+ldp w21, w28, [x22], #-24 ; add x21,x21,x28 :: rd 00000001ebe9e7e4 rn (hidden), cin 0, nzcv 00000000
+ldp w21, w28, [x22], #-24 ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
+ldp w21, w28, [x22, #-40]! ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000
+ldp w21, w28, [x22, #-40]! ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
+ldp w21, w28, [x22, #-40] ; add x21,x21,x28 :: rd 000000019b999794 rn (hidden), cin 0, nzcv 00000000
+ldp w21, w28, [x22, #-40] ; eor x21,x21,x28 :: rd 0000000004040404 rn (hidden), cin 0, nzcv 00000000
+LDR (literal, int reg)
+xyzzy00: ldr x21, xyzzy00 - 8 :: rd aa0003f6d51b4203 rn (hidden), cin 0, nzcv 00000000
+xyzzy01: ldr x21, xyzzy01 + 0 :: rd aa1503e258000015 rn (hidden), cin 0, nzcv 00000000
+xyzzy02: ldr x21, xyzzy02 + 8 :: rd 911e43a0d53b4201 rn (hidden), cin 0, nzcv 00000000
+xyzzy03: ldr x21, xyzzy03 - 4 :: rd 58fffff5aa0003f6 rn (hidden), cin 0, nzcv 00000000
+xyzzy04: ldr x21, xyzzy04 + 0 :: rd aa1503e258000015 rn (hidden), cin 0, nzcv 00000000
+xyzzy05: ldr x21, xyzzy05 + 4 :: rd d53b4201aa1503e2 rn (hidden), cin 0, nzcv 00000000
+{LD,ST}R (integer register) (entirely MISSING)
+LDRS{B,H,W} (uimm12)
+ldrsw x21, [x22, #24] :: rd ffffffff8b8a8988 rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22, #20] :: rd ffffffffffff8584 rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22, #44] :: rd 00000000ffff9d9c rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22, #88] :: rd ffffffffffffffc8 rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22, #56] :: rd 00000000ffffffa8 rn (hidden), cin 0, nzcv 00000000
+LDRS{B,H,W} (simm9, upd) (upd check is MISSING)
+ldrsw x21, [x22, #-24]! :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22, #-20]! :: rd ffffffffffffdddc rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22, #-44]! :: rd 00000000ffffc5c4 rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22, #-88]! :: rd ffffffffffffff98 rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22, #-56]! :: rd 00000000ffffffb8 rn (hidden), cin 0, nzcv 00000000
+ldrsw x21, [x22], #-24 :: rd fffffffff3f2f1f0 rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22], #-20 :: rd fffffffffffff1f0 rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22], #-44 :: rd 00000000fffff1f0 rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22], #-88 :: rd fffffffffffffff0 rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22], #-56 :: rd 00000000fffffff0 rn (hidden), cin 0, nzcv 00000000
+LDRS{B,H,W} (simm9, noUpd)
+ldrsw x21, [x22, #-24] :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22, #-20] :: rd ffffffffffffdddc rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22, #-44] :: rd 00000000ffffc5c4 rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22, #-88] :: rd ffffffffffffff98 rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22, #-56] :: rd 00000000ffffffb8 rn (hidden), cin 0, nzcv 00000000
+LDP,STP (immediate, simm7) (FP&VEC) (entirely MISSING)
+{LD,ST}R (vector register) (entirely MISSING)
+LDRS{B,H,W} (integer register, SX)
+ldrsw x21, [x22,x23] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsw x21, [x22,x23, lsl #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsw x21, [x22,w23,uxtw #0] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsw x21, [x22,w23,uxtw #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsw x21, [x22,w23,sxtw #0] :: rd ffffffffeeedeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsw x21, [x22,w23,sxtw #2] :: rd ffffffffdfdedddc rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22,x23] :: rd fffffffffffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22,x23, lsl #1] :: rd fffffffffffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22,w23,uxtw #0] :: rd fffffffffffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22,w23,uxtw #1] :: rd fffffffffffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22,w23,sxtw #0] :: rd ffffffffffffeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh x21, [x22,w23,sxtw #1] :: rd ffffffffffffe7e6 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22,x23] :: rd 00000000fffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22,x23, lsl #1] :: rd 00000000fffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22,w23,uxtw #0] :: rd 00000000fffff6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22,w23,uxtw #1] :: rd 00000000fffffbfa rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22,w23,sxtw #0] :: rd 00000000ffffeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsh w21, [x22,w23,sxtw #1] :: rd 00000000ffffe7e6 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22,x23] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22,x23, lsl #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22,w23,uxtw #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22,w23,uxtw #0] :: rd fffffffffffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22,w23,sxtw #0] :: rd ffffffffffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb x21, [x22,w23,sxtw #0] :: rd ffffffffffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22,x23] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22,x23, lsl #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22,w23,uxtw #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22,w23,uxtw #0] :: rd 00000000fffffff5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22,w23,sxtw #0] :: rd 00000000ffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000
+ldrsb w21, [x22,w23,sxtw #0] :: rd 00000000ffffffeb rm (hidden), rn (hidden), cin 0, nzcv 00000000
+LDR/STR (immediate, SIMD&FP, unsigned offset) (entirely MISSING)
+LDR/STR (immediate, SIMD&FP, pre/post index) (entirely MISSING)
+LDUR/STUR (unscaled offset, SIMD&FP) (entirely MISSING)
+LDR (literal, SIMD&FP) (entirely MISSING)
+LD1/ST1 (single structure, no offset) (entirely MISSING)
+LD1/ST1 (single structure, post index) (entirely MISSING)
+LD{,A}X{R,RH,RB} (entirely MISSING)
+ST{,L}X{R,RH,RB} (entirely MISSING)
+LDA{R,RH,RB}
+ldar x21, [x22] :: rd f7f6f5f4f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
+ldar w21, [x22] :: rd 00000000f3f2f1f0 rn (hidden), cin 0, nzcv 00000000
+ldarh w21, [x22] :: rd 000000000000f1f0 rn (hidden), cin 0, nzcv 00000000
+ldarb w21, [x22] :: rd 00000000000000f0 rn (hidden), cin 0, nzcv 00000000
+STL{R,RH,RB} (entirely MISSING)
+LDR,STR (immediate, uimm12)ldr x13, [x5, #24] with x5 = middle_of_block+-1, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 37c6ea00e0f4f257 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr w13, [x5, #20] with x5 = middle_of_block+1, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 663cba29f1fe102a x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrh w13, [x5, #44] with x5 = middle_of_block+2, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 74b2685cb1630837 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrb w13, [x5, #56] with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ bf73927edcc8e3a7 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5, #24] with x5 = middle_of_block+-3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. 3d b5 fe cd 8f 1e a7 32 .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str w13, [x5, #20] with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. fb 48 5c 15 .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strh w13, [x5, #44] with x5 = middle_of_block+6, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. 43 .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strb w13, [x5, #56] with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. bd
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDUR,STUR (immediate, simm9)
+ldr x13, [x5], #-24 with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 5e602f48b53d6e42 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr x13, [x5, #-40]! with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ c2a40eb09d08f981 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -40 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr x13, [x5, #-48] with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ c5349b34f359e130 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5], #-24 with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] 3a 9b 1d 46 18 b0 ef 81 .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5, #-40]! with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. 3f 73 c0 0a b7 5c 8d 74
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -40 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5, #-48] with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] 09 95 f8 6e 41 d0 2d 47 .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDP,STP (immediate, simm7)
+ldp x13, x23, [x5], #-24 with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 1b66ab089f41ee43 x13 (xor, xfer intreg #1)
+ ac8fc79beb26e5f5 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp x13, x23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ b98f2dea69fe5015 x13 (xor, xfer intreg #1)
+ 5913a7a99bcd1811 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -40 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp x13, x23, [x5, #-40] with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ ba55d10667c950ff x13 (xor, xfer intreg #1)
+ b91a382f89560923 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp x13, x23, [x5], #-24 with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] 22 0e b6 7d 25 b1 49 6c 85 67 29 ca e9 6b 42 6c
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp x13, x23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. 72 af 97 76 3d b0 cc 4f
+ [ 96] 22 1a 6b 79 8f 52 63 1e .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -40 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp x13, x23, [x5, #-40] with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. ef cf 9b 01 25 8f 11 54
+ [ 96] 58 be 1c a8 1f 77 e8 26 .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp w13, w23, [x5], #-24 with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 5826bd372d9e2ece x13 (xor, xfer intreg #1)
+ a690cbe50b71f694 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp w13, w23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ c4a8641060c8618a x13 (xor, xfer intreg #1)
+ f5f25be4fdcff02a x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -40 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp w13, w23, [x5, #-40] with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ f711f2d5f6d39080 x13 (xor, xfer intreg #1)
+ 2e212f8dcab7fa0d x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp w13, w23, [x5], #-24 with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] c0 f4 d9 ba de 39 bb 1f .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp w13, w23, [x5, #-40]! with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. b3 3b 5a ac f6 fc e4
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -40 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp w13, w23, [x5, #-40] with x5 = middle_of_block+0, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. 66 84 fc c9 b9 a8 37 28
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDR (literal, int reg) (DONE ABOVE)
+{LD,ST}R (integer register) (entirely MISSING)
+str x13, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. b8 34 a7 48 08 af c1 91
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. e8 b0 5c d8
+ [112] 52 99 34 7c .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 35 92 d1 bb d7 45 bf dc .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. 3d 99 5a 39
+ [176] a9 f4 a3 2d .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] a5 3f df 5d 66 f7 20 e8 .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str x13, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 5d e8 12 15
+ [112] 96 8e 05 30 .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr x13, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 91e9b1a8348ca797 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr x13, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 1cb5b125b109faeb x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr x13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 4085aae03ffeda0c x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr x13, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 6a28851da073b3f9 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr x13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 72858dcc143fe6ef x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr x13, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ de1c29d387e40b0c x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 44 ba 04 81 .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str w13, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. d6 af 6a d7
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 80 ee 73 ad .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str w13, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. cf 5c 96 91
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 4f 39 ed 78 .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str w13, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. 8a 61 ee 1b
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 8482adce109203e3 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr w13, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ fcbcda5053fe3119 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 9bbc4e9ea534edef x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr w13, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 27f86f4c86c32be6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 62e39eed83444fa6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr w13, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 12f04216e80ea35a x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strh w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 59 fc .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strh w13, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. dc 12 .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strh w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 05 f8 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strh w13, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. fa ac .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strh w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 33 e0 .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strh w13, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. c8 9a .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrh w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ d8322d9d06f127c8 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrh w13, [x5, x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ b6a77dd46effc11f x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrh w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ ec53c5c6d2bc4105 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrh w13, [x5, w6, uxtw #1] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 3dab680838dbf069 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrh w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 6f21cb2ea4117de5 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrh w13, [x5, w6, sxtw #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 442a51cc1911c952 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strb w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. f9 .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strb w13, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 87 .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strb w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] c4 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strb w13, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] c3 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strb w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 51 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+strb w13, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. d4 .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrb w13, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 568db3c39f462465 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrb w13, [x5, x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ da7e66eeefeac8c3 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrb w13, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ e616c1c66bacf629 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrb w13, [x5, w6, uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 3dc827dc1a415140 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrb w13, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ a50afdc7fd5c7dde x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrb w13, [x5, w6, sxtw #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ e14fa7191ab21ead x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDRS{B,H,W} (uimm12)
+ldrsw x13, [x5, #24] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 4bf47798b0084d23 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5, #20] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 1c4efbbaef23ef5c x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5, #44] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 32b781460ee5ea9b x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5, #72] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 9a6f9e00e49efa40 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5, #56] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 40af08046d98739f x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDRS{B,H,W} (simm9, upd) (upd check is MISSING)
+ldrsw x13, [x5, #-24]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 868adbe916974e3c x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5, #-20]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 026cc1be8681bd68 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -20 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5, #-44]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 674094a1f1f871a6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -44 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5, #-72]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 8903429dc60011fa x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -72 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5, #-56]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 2752acc8fc4a8119 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -56 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsw x13, [x5], #-24 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 059f35b78686b811 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -24 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5], #-20 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 199fbe0162896025 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -20 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5], #-44 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 900736310fc037e8 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -44 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5], #-72 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ c50975e3f31cb340 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -72 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5], #-56 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 4adb65a9b3c0ee9d x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -56 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDRS{B,H,W} (simm9, noUpd)
+ldrsw x13, [x5, #-24] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ e3ef68173ef979fb x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5, #-20] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 54bae2c06ea881e0 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5, #-44] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 61b03939c0a975cd x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5, #-72] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 32b930e96a65fd89 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5, #-56] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 5eee08eb7529502a x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDP,STP (immediate, simm7) (FP&VEC)
+stp q17, q18, [x5, 32] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 55 18 f1 5c aa 84 c0 38 cd 7e 31 c8 92 f4 b0 e7
+ [160] 0e 6c 4b d1 1e 2a 76 4c e2 a7 c8 5a 26 59 0e 5b
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp q17, q18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 02 3e c1 07 ca e4 d0 ed 19 98 1e 29 25 e0 75 25
+ [160] e1 0f a7 69 a1 4c 5b 2c 01 08 48 ca f8 ff dc 16
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp q17, q18, [x5], 32 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 67 98 a3 78 5f 8e f9 57 5e 90 fc 32 c8 db d6 2c
+ [128] 20 68 2a 31 1b f7 e9 b2 9f 6a 21 20 db 21 17 27
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp d17, d18, [x5, 32] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] a0 6c d2 7f 89 d1 b1 b6 c5 5d 74 11 63 9d cb b9
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp d17, d18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 6f 14 75 6c 06 fe e1 ea 40 30 6e 55 7c 36 4d c4
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+stp d17, d18, [x5], 32 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] c2 ae 80 3d 80 4f 9f 9e 93 76 25 55 85 51 97 1a
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp q17, q18, [x5, 32] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c3aeec76faa5f5c3 v17.d[0] (xor, xfer vecreg #1)
+ d81dc8f6818b6e41 v17.d[1] (xor, xfer vecreg #1)
+ c4709239d600ee90 v18.d[0] (xor, xfer vecreg #2)
+ a640a2efa8725362 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp q17, q18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 80b42ff8dc0573ed v17.d[0] (xor, xfer vecreg #1)
+ 978d0461007b54b8 v17.d[1] (xor, xfer vecreg #1)
+ 47b1ef6f289cbd69 v18.d[0] (xor, xfer vecreg #2)
+ 4283a680f9f42f27 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp q17, q18, [x5], 32 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 32e4abace36584a4 v17.d[0] (xor, xfer vecreg #1)
+ 94465539af6bee2a v17.d[1] (xor, xfer vecreg #1)
+ 45ee7595ed87a70a v18.d[0] (xor, xfer vecreg #2)
+ 0b0689e9f49030da v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp d17, d18, [x5, 32] with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 81468c3a81e28308 v17.d[0] (xor, xfer vecreg #1)
+ 9402389a9fd7e622 v17.d[1] (xor, xfer vecreg #1)
+ ac80e445d56aaf23 v18.d[0] (xor, xfer vecreg #2)
+ f429df6f28a16e8a v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp d17, d18, [x5, 32]! with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 63c656d72c05e674 v17.d[0] (xor, xfer vecreg #1)
+ 0693fb5daf24d9a0 v17.d[1] (xor, xfer vecreg #1)
+ ce871ca48d1a40cc v18.d[0] (xor, xfer vecreg #2)
+ d38bf1af25daca31 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldp d17, d18, [x5], 32 with x5 = middle_of_block+-16, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ ce2bf285733f1da6 v17.d[0] (xor, xfer vecreg #1)
+ d57bc365125181f6 v17.d[1] (xor, xfer vecreg #1)
+ 0fde67d4c6716a14 v18.d[0] (xor, xfer vecreg #2)
+ f4335fd1bac1932e v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+{LD,ST}R (vector register)
+str d17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. db 63 b8 ac e6 bd 2f 97
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 0e cf b0 95
+ [112] ba ca a7 9c .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 20 05 ac 34 8e ff 78 7a .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. 61 1e 17 07
+ [176] cd a0 14 3e .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] fe 3c 6b 02 b7 fe 10 c3 .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. 7f b8 e7 ca
+ [112] 50 fb 04 68 .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 368c5b732c1248a5 v17.d[0] (xor, xfer vecreg #1)
+ f68888b1170ad684 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, x6, lsl #3] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ ee01fe34a2d85c41 v17.d[0] (xor, xfer vecreg #1)
+ 3b8184af9c823f6c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ dc4fd084ba3953c1 v17.d[0] (xor, xfer vecreg #1)
+ 426589a518aea21f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, w6, uxtw #3] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 619304aa5a129766 v17.d[0] (xor, xfer vecreg #1)
+ 4e2a7aa80ec124f3 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 8d7d6fe89f4f3dd9 v17.d[0] (xor, xfer vecreg #1)
+ a2c23ccc03f0e73c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, w6, sxtw #3] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 480d291c1baa1e67 v17.d[0] (xor, xfer vecreg #1)
+ 8323b3257a6e114c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. 05 44 01 d5 .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. 5b 32 ec e5
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 79 ee 29 c6 .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. 41 e4 eb 1d
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] e6 b1 03 2d .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. ec f6 d1 82
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f1bb54fe78f0286a v17.d[0] (xor, xfer vecreg #1)
+ 63b582e54ba32e35 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, x6, lsl #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 59faf450fdf6566e v17.d[0] (xor, xfer vecreg #1)
+ 3ba5adb465ed9857 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, w6, uxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ cfed330c080743c7 v17.d[0] (xor, xfer vecreg #1)
+ 03f1916ba55aac35 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, w6, uxtw #2] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 160a73c656d57e46 v17.d[0] (xor, xfer vecreg #1)
+ 018e121e8f1f8f24 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, w6, sxtw] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f4c4181184dc39c4 v17.d[0] (xor, xfer vecreg #1)
+ 776e13e3a8706377 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, w6, sxtw #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 2c8e878293ad5852 v17.d[0] (xor, xfer vecreg #1)
+ ab8679cc737f4e82 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDRS{B,H,W} (integer register, SX)
+ldrsw x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 4991809b592766de x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsw x13, [x5,x6, lsl #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ ecab746191e71575 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsw x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 22a74ae38fee367e x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsw x13, [x5,w6,uxtw #2] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 1cd6637ce5e8e8da x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsw x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 9eab24c24f0ac55c x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsw x13, [x5,w6,sxtw #2] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 6c9cf046e9a2bfa3 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ b5e3d360b748922c x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ fb9f3c5f3b2bddc4 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ ba667ce49472fbca x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ ea7d6667dd92cdf2 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ afc148d693ed6288 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh x13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 58d88efd9452995d x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ a8359b70e176717b x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5,x6, lsl #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 654ed4c3800da87c x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 51959d8974ca561f x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5,w6,uxtw #1] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 32805957c26143f5 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ ca816dc1927863b6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsh w13, [x5,w6,sxtw #1] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ de0e3d5a79ef9f53 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ ce66d34814b16659 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 89989f6cc65775a1 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 578206f2f140e49e x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 54bd9f2dc8392d13 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ b0320b9e0885afab x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb x13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ a1e0a2c260cad60b x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5,x6] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 45283e54c51f5bad x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5,x6, lsl #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ c75cfa3b6ceb89d9 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ aa2ff686984d59d6 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ b01695c9b1059196 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 9f833c9791a66c27 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldrsb w13, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 39eb4f856504f7ce x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDR/STR (immediate, SIMD&FP, unsigned offset)
+str q17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 7b 5d 69 f7 64 8c 79 47 6f 8f 57 84 7b c3 9c 9f
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 42 cd cc 36 af 70 5a 49 .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 8d 06 22 df .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr q17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ eedbb4bf846226cd v17.d[0] (xor, xfer vecreg #1)
+ 94094b6d188de7fa v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 029fcee15d9319f2 v17.d[0] (xor, xfer vecreg #1)
+ 50541814802369e6 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, #-32] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 86bcef9905c6716d v17.d[0] (xor, xfer vecreg #1)
+ fa13cb2fc8681760 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDR/STR (immediate, SIMD&FP, pre/post index)
+str q17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 3a fc f2 7c 33 4d e6 bb 98 8b 63 7d c8 cc ed c5
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] d6 89 52 b2 c9 1c 8f 84 .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] 61 9d 73 ee .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr q17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f3e66911400e0ffd v17.d[0] (xor, xfer vecreg #1)
+ bceee589d845dc5c v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 476d9e9cc8b9ac0a v17.d[0] (xor, xfer vecreg #1)
+ 17224cc91cc3a43e v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5], #-32 with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 20d04ccbe8ce283b v17.d[0] (xor, xfer vecreg #1)
+ 22146e45c5a92bce v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 3c 68 70 1a e9 09 6a 17 ff 65 da cd 31 9d 99 f7
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] 1a ee af 76 38 32 54 22 .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] bd ff 23 fb .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr q17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c08cfa3f5c85e9ec v17.d[0] (xor, xfer vecreg #1)
+ d13f15e778e3733d v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 8cd8469c4bb50f10 v17.d[0] (xor, xfer vecreg #1)
+ 0cee45c96b719b9f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, #-32]! with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 8cb8b23ad49fbfa0 v17.d[0] (xor, xfer vecreg #1)
+ 0864e77407470a14 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDUR/STUR (unscaled offset, SIMD&FP)
+str q17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. 92 be 41 c2 36 e0 f2 76 79 06 b2 b1 bd
+ [144] 83 b1 f0 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str d17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. ff 9d d1 08 13 ab 3d b9 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+str s17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. bb bb 62 b6 .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr q17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 315438529f368984 v17.d[0] (xor, xfer vecreg #1)
+ 63c745a60b8405eb v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr d17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 61d08c15c6fc312c v17.d[0] (xor, xfer vecreg #1)
+ 8f9963f2cf0bade7 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ldr s17, [x5, #-13] with x5 = middle_of_block+16, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 2b5282c8bfe45946 v17.d[0] (xor, xfer vecreg #1)
+ 0ce3959eed221512 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LDR (literal, SIMD&FP) (entirely MISSING)
+LD1/ST1 (single structure, no offset)
+st1 {v17.2d}, [x5] with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. b8 20 bd e5 8a f9 76 f3 cc ae a8 d0 18
+ [144] 47 f5 2c .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4s}, [x5] with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. 64 0a f3 ac 33 39 0b fb cb 96 09
+ [144] 7b ac c2 61 4e .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8h}, [x5] with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. 24 9d d3 60 d7 68 98 1a d1
+ [144] 3c 02 23 a5 ab 09 03 .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b}, [x5] with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. c0 d2 1e
+ [144] 09 b5 58 b4 9e d4 9d d9 78 3f 12 c7 ad .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.1d}, [x5] with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. 9e 6a 38 6f 46 53 2c 51 .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2s}, [x5] with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. 99 50 bc c2 fb 65 .. cc .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4h}, [x5] with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. e6 45 98 4f 7f 3f 99 04 ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8b}, [x5] with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 97 b2 c4
+ [144] d8 5e dc 6a b7 .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2d}, [x5] with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0e7683e67672f875 v17.d[0] (xor, xfer vecreg #1)
+ 5849c62885094425 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4s}, [x5] with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ cc566178b0505ce2 v17.d[0] (xor, xfer vecreg #1)
+ 9ba578e187b7ec29 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8h}, [x5] with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f5a2c2db348d79c9 v17.d[0] (xor, xfer vecreg #1)
+ 2d19eece1ac4cfe1 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.16b}, [x5] with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 2895e1c44e7d6375 v17.d[0] (xor, xfer vecreg #1)
+ 68121b8e14fe75c3 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.1d}, [x5] with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 11488cce9b957a63 v17.d[0] (xor, xfer vecreg #1)
+ a8e3a2dc36f2376f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2s}, [x5] with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ e400b2d8baf17a43 v17.d[0] (xor, xfer vecreg #1)
+ 2ce128ce0966e831 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4h}, [x5] with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ fad3b103f776773a v17.d[0] (xor, xfer vecreg #1)
+ c2db8749219d644f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8b}, [x5] with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 1fb93f52acada1d3 v17.d[0] (xor, xfer vecreg #1)
+ acc5a26005cccd1d v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD1/ST1 (single structure, post index)
+st1 {v17.2d}, [x5], #16 with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. be 9f 67 38 8a 5a ae 31 9f 68 ea 98 79
+ [144] 97 d9 93 .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4s}, [x5], #16 with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. af df 1d d5 ec ca 0a 2c b4 22 83
+ [144] 5d a8 8e 56 3d .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8h}, [x5], #16 with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. ec a6 76 d8 d7 cd cc 1d f1
+ [144] 42 d5 a2 31 e1 24 e2 .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b}, [x5], #16 with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 36 31 5c
+ [144] 32 93 67 52 11 bd f9 5b 3f 75 e0 8e 03 .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. 44 79 62 32 a6 05 a4 be .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.2s}, [x5], #8 with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. 34 a3 95 cb c4 36 6f 9d .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.4h}, [x5], #8 with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. 2f 3e 9a 97 bf 54 ee 97 ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.8b}, [x5], #8 with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. 1d 51 72
+ [144] a0 0d e9 38 8b .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2d}, [x5], #16 with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 6856852b89835e57 v17.d[0] (xor, xfer vecreg #1)
+ 926cd97a6fcb250a v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4s}, [x5], #16 with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d5d11520d94f1b33 v17.d[0] (xor, xfer vecreg #1)
+ 5cbb554327b8a8e3 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8h}, [x5], #16 with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ b9391b4ebce992b0 v17.d[0] (xor, xfer vecreg #1)
+ 2aee8c5bebb07542 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.16b}, [x5], #16 with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 677b9246bea3c7b9 v17.d[0] (xor, xfer vecreg #1)
+ c2cbc85912c50a5e v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 16 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 45c02b25ccc83819 v17.d[0] (xor, xfer vecreg #1)
+ 979e4bd3158ec388 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.2s}, [x5], #8 with x5 = middle_of_block+5, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 17ce07c71f09fd99 v17.d[0] (xor, xfer vecreg #1)
+ 09bc3bb12d99f56d v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.4h}, [x5], #8 with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ bb582a4317d4a712 v17.d[0] (xor, xfer vecreg #1)
+ cc154357cca832ef v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1 {v17.8b}, [x5], #8 with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 843b172475108087 v17.d[0] (xor, xfer vecreg #1)
+ 249f48da74ee9d60 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD1R (single structure, replicate)
+ld1r {v17.2d}, [x5] with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f2660509f772e2c4 v17.d[0] (xor, xfer vecreg #1)
+ 4ce39e650ae364b8 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.1d}, [x5] with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 4e86be680cf6eb99 v17.d[0] (xor, xfer vecreg #1)
+ a211d8c7f4f18c65 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4s}, [x5] with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 993c272115d4d6de v17.d[0] (xor, xfer vecreg #1)
+ 34921415b16467d2 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2s}, [x5] with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ eec233adaef7ff96 v17.d[0] (xor, xfer vecreg #1)
+ a4b40916ce41e41a v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8h}, [x5] with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 935cc2072eb1386a v17.d[0] (xor, xfer vecreg #1)
+ 6613df7ee0c3d743 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4h}, [x5] with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c328131db4585dfa v17.d[0] (xor, xfer vecreg #1)
+ 4926fd682180c520 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.16b}, [x5] with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ f087f060b8d625f7 v17.d[0] (xor, xfer vecreg #1)
+ 870a7f81275fc7f6 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8b}, [x5] with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ cf9a2fa5f98755c2 v17.d[0] (xor, xfer vecreg #1)
+ b109d45d0d4c4d17 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2d}, [x5], #8 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0c265c7984382b89 v17.d[0] (xor, xfer vecreg #1)
+ e9b2ff4b2c9fcf1f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.1d}, [x5], #8 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ bdfdd39474eccc4f v17.d[0] (xor, xfer vecreg #1)
+ fdfbad94b3469f9f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 8 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4s}, [x5], #4 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0bcc9003fe0271dc v17.d[0] (xor, xfer vecreg #1)
+ 82366f42151d77f2 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2s}, [x5], #4 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ c9fd7dc362339d38 v17.d[0] (xor, xfer vecreg #1)
+ 4c9da8af320ed858 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8h}, [x5], #2 with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 9a6cf746f39749b4 v17.d[0] (xor, xfer vecreg #1)
+ 870355d295f3be89 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4h}, [x5], #2 with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 205edc63fd70f66d v17.d[0] (xor, xfer vecreg #1)
+ be8fe64caa441ae1 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.16b}, [x5], #1 with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 163053439f6c0c42 v17.d[0] (xor, xfer vecreg #1)
+ e601d1578762518f v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8b}, [x5], #1 with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 85f87dd58efe3327 v17.d[0] (xor, xfer vecreg #1)
+ 7470860d3c8884dc v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2d}, [x5], x6 with x5 = middle_of_block+3, x6=-5
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 742ee30b26c3644a v17.d[0] (xor, xfer vecreg #1)
+ 620afd520355620a v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -5 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.1d}, [x5], x6 with x5 = middle_of_block+3, x6=-4
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ d77f537144c905fd v17.d[0] (xor, xfer vecreg #1)
+ 8de2a890077a37e7 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -4 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4s}, [x5], x6 with x5 = middle_of_block+3, x6=-3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 733c2c6280caff90 v17.d[0] (xor, xfer vecreg #1)
+ 0bd32ad90eb64b11 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.2s}, [x5], x6 with x5 = middle_of_block+3, x6=-2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 8f097b9699ca1fd8 v17.d[0] (xor, xfer vecreg #1)
+ 2a846d762bba52a3 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8h}, [x5], x6 with x5 = middle_of_block+3, x6=-1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 64a4000905e8aa3e v17.d[0] (xor, xfer vecreg #1)
+ 930f6607495e81b1 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ -1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.4h}, [x5], x6 with x5 = middle_of_block+3, x6=1
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ a61deef2566f701d v17.d[0] (xor, xfer vecreg #1)
+ 6af5f45fc9e7f5b0 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 1 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.16b}, [x5], x6 with x5 = middle_of_block+3, x6=2
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 3ad49e64bf2c15cb v17.d[0] (xor, xfer vecreg #1)
+ ab04a19d6ae38e9d v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 2 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld1r {v17.8b}, [x5], x6 with x5 = middle_of_block+3, x6=3
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 47e6864987e1a4e7 v17.d[0] (xor, xfer vecreg #1)
+ 6dd65eeb01a241ae v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 3 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD2/ST2 (multiple 2-elem structs to/from 2/regs, post index) (VERY INCOMPLETE)
+ld2 {v17.2d, v18.2d}, [x5], #32 with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 16e55b1873ee34c3 v17.d[0] (xor, xfer vecreg #1)
+ 34707980f120b864 v17.d[1] (xor, xfer vecreg #1)
+ ba093b5d784363cf v18.d[0] (xor, xfer vecreg #2)
+ 7111d1b5c20be11e v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v17.2d, v18.2d}, [x5], #32 with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. 0e 3f 31 98 6e 90 de 8d 3f
+ [144] ea 85 9a 2a e6 4c b8 d3 c7 c8 62 8c 43 99 75 2c
+ [160] fe 89 33 25 52 9d a8 .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+ld2 {v17.4s, v18.4s}, [x5], #32 with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 1d1dad5f22f91503 v17.d[0] (xor, xfer vecreg #1)
+ b57248c23e0baef6 v17.d[1] (xor, xfer vecreg #1)
+ 05bbead3136a567d v18.d[0] (xor, xfer vecreg #2)
+ baed025f106d8588 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st2 {v17.4s, v18.4s}, [x5], #32 with x5 = middle_of_block+17, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. cd 11 7d 61 05 62 71 d9 e4 fa ea f5 7b 7d c4
+ [160] e5 8f 06 7e 21 0a c6 48 5a 02 12 03 3a 27 30 ff
+ [176] c5 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD1/ST1 (multiple 1-elem structs to/from 2 regs, no offset) (VERY INCOMPLETE)
+ld1 {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 683f58edc2f5f671 v17.d[0] (xor, xfer vecreg #1)
+ 174e8d675cf2632a v17.d[1] (xor, xfer vecreg #1)
+ 15633f2c6ebd44da v18.d[0] (xor, xfer vecreg #2)
+ ab3a9c72639ef492 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b}, [x5] with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. 49 .. .. a2 31 44 0c 57 db
+ [144] df fe 73 d3 d7 67 7d ae da 61 fc b3 41 3a 20 e8
+ [160] 95 ed 8a f3 1c 8a 7f .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD1/ST1 (multiple 1-elem structs to/from 2 regs, post index) (VERY INCOMPLETE)
+ld1 {v17.16b, v18.16b}, [x5], #32 with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 9bf660d5bdff8c3c v17.d[0] (xor, xfer vecreg #1)
+ a0ccbbec9ef6f2ca v17.d[1] (xor, xfer vecreg #1)
+ 8303595518823d47 v18.d[0] (xor, xfer vecreg #2)
+ 75f70396adc8eda8 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b}, [x5], #32 with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. d2 47 11 63 39 8e 47 81 6e
+ [144] 46 95 76 6d ba 9e 22 ad b5 07 7b 8e e5 46 4e b2
+ [160] b8 27 42 be 20 42 bf .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 32 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD1/ST1 (multiple 1-elem structs to/from 3 regs, no offset) (VERY INCOMPLETE)
+ld1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+3, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ a9d70e88d1e89d30 v17.d[0] (xor, xfer vecreg #1)
+ 478a0f9d90561d2b v17.d[1] (xor, xfer vecreg #1)
+ 3e85525215476b1e v18.d[0] (xor, xfer vecreg #2)
+ 353dc370e1ffd26a v18.d[1] (xor, xfer vecreg #2)
+ 6f4831650bbf0b6a v19.d[0] (xor, xfer vecreg #3)
+ 51807f1bc8292233 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st1 {v17.16b, v18.16b, v19.16b}, [x5] with x5 = middle_of_block+7, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. a3 7d e6 a1 06 24 44 85 4b
+ [144] 7c b1 95 4b 4a d7 c1 f5 3e f1 b7 2d 92 94 93 c4
+ [160] 69 68 57 cf 90 7d 39 5f 16 3a 12 93 0b b3 fd e7
+ [176] ca eb da 1a f6 75 3d .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 0 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+LD3/ST3 (multiple 3-elem structs to/from 3/regs, post index) (VERY INCOMPLETE)
+ld3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+13, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 446f3899b211b6a0 v17.d[0] (xor, xfer vecreg #1)
+ 6437eeb9f3204807 v17.d[1] (xor, xfer vecreg #1)
+ 60e1161912e2876e v18.d[0] (xor, xfer vecreg #2)
+ e1a4654ef78b7a07 v18.d[1] (xor, xfer vecreg #2)
+ aed5a7373cd64d1f v19.d[0] (xor, xfer vecreg #3)
+ 739aef5767e6aa1f v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
+st3 {v17.2d, v18.2d, v19.2d}, [x5], #48 with x5 = middle_of_block+17, x6=0
+ [ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [144] .. c5 1c bb 41 0f c0 bd f1 9b b6 ab 88 aa 17 31
+ [160] 94 7d ee 24 ee 14 61 cd 93 9f 71 69 88 94 38 eb
+ [176] 2f 75 95 31 3e 9e 0e 6c .. 58 4a a7 86 5e 21 08
+ [192] c0 .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ [240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
+ 0000000000000000 x13 (xor, xfer intreg #1)
+ 0000000000000000 x23 (xor, xfer intreg #2)
+ 0000000000000000 v17.d[0] (xor, xfer vecreg #1)
+ 0000000000000000 v17.d[1] (xor, xfer vecreg #1)
+ 0000000000000000 v18.d[0] (xor, xfer vecreg #2)
+ 0000000000000000 v18.d[1] (xor, xfer vecreg #2)
+ 0000000000000000 v19.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v19.d[1] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[0] (xor, xfer vecreg #3)
+ 0000000000000000 v20.d[1] (xor, xfer vecreg #3)
+ 48 x5 (sub, base reg)
+ 0 x6 (sub, index reg)
+
--- /dev/null
+prog: memory
+vgopts: -q
projects / thirdparty / valgrind.git / commitdiff
