i386: Deprecate -m[no-]avx10.1 and make -mno-avx10.1-512 to disable the whole AVX10.1

Based on the feedback we got, we would like to re-alias avx10.x to 512
bit in the future. This leaves the current avx10.1 alias to 256 bit
inconsistent. Since it has been there for GCC 14.1 and GCC 14.2,
we decide to deprecate avx10.1 alias. The current proposal is not
adding it back in the future, but it might change if necessary.

For -mno- options, it is confusing what it is disabling when it comes
to avx10. Since there is barely usage enabling AVX10 with 512 bit
then disabling it, we will only provide -mno-avx10.x options in the
future, disabling the whole AVX10.x. If someone really wants to disable
512 bit after enabling it, -mavx10.x-512 -mno-avx10.x -mavx10.x-256 is
the only way to do that since we also do not want to break the usual
expression on -m- options enabling everything mentioned.

However, for avx10.1, since we deprecated avx10.1, there is no reason
we should have -mno-avx10.1. Thus, we need to keep -mno-avx10.1-[256,512].
To avoid confusion, we will make -mno-avx10.1-512 to disable the
whole AVX10.1 set to match the future -mno-avx10.x.

gcc/ChangeLog:

	* common/config/i386/i386-common.cc
	(OPTION_MASK_ISA2_AVX2_UNSET): Change AVX10.1 unset macro.
	(OPTION_MASK_ISA2_AVX10_1_256_UNSET): Removed.
	(OPTION_MASK_ISA2_AVX10_1_512_UNSET): Removed.
	(OPTION_MASK_ISA2_AVX10_1_UNSET): New.
	(ix86_handle_option): Adjust AVX10.1 unset macro.
	* common/config/i386/i386-isas.h: Remove avx10.1.
	* config/i386/i386-options.cc
	(ix86_valid_target_attribute_inner_p): Ditto.
	(ix86_option_override_internal): Adjust warning message.
	* config/i386/i386.opt: Remove mavx10.1.
	* doc/extend.texi: Remove avx10.1 and adjust doc.
	* doc/sourcebuild.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx10-check.h: Change to avx10.1-256.
	* gcc.target/i386/avx10_1-1.c: Ditto.
	* gcc.target/i386/avx10_1-13.c: Ditto.
	* gcc.target/i386/avx10_1-14.c: Ditto.
	* gcc.target/i386/avx10_1-21.c: Ditto.
	* gcc.target/i386/avx10_1-22.c: Ditto.
	* gcc.target/i386/avx10_1-23.c: Ditto.
	* gcc.target/i386/avx10_1-24.c: Ditto.
	* gcc.target/i386/avx10_1-3.c: Ditto.
	* gcc.target/i386/avx10_1-5.c: Ditto.
	* gcc.target/i386/avx10_1-6.c: Ditto.
	* gcc.target/i386/avx10_1-8.c: Ditto.
	* gcc.target/i386/pr117946.c: Ditto.
	* gcc.target/i386/avx10_1-12.c: Adjust warning message.
	* gcc.target/i386/avx10_1-19.c: Ditto.
	* gcc.target/i386/avx10_1-17.c: Adjust to no-avx10.1-512.

diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 52ad1c5acd17a9df3ae1f73fc6c26af0139067ff..793d68456845857cc26480702bb14d59a8af1799 100644 (file)
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -249,7 +249,7 @@ along with GCC; see the file COPYING3.  If not see
   (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
    | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
    | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
-   | OPTION_MASK_ISA2_AVX10_1_256_UNSET)
+   | OPTION_MASK_ISA2_AVX10_1_UNSET)
 #define OPTION_MASK_ISA_AVX512F_UNSET \
   (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
    | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
@@ -325,11 +325,9 @@ along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F
 #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
-#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \
-  (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET \
-   | OPTION_MASK_ISA2_AVX10_2_256_UNSET)
-#define OPTION_MASK_ISA2_AVX10_1_512_UNSET \
-  (OPTION_MASK_ISA2_AVX10_1_512 | OPTION_MASK_ISA2_AVX10_2_512_UNSET)
+#define OPTION_MASK_ISA2_AVX10_1_UNSET \
+  (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512 \
+   | OPTION_MASK_ISA2_AVX10_2_256_UNSET | OPTION_MASK_ISA2_AVX10_2_512_UNSET)
 #define OPTION_MASK_ISA2_AVX10_2_256_UNSET OPTION_MASK_ISA2_AVX10_2_256
 #define OPTION_MASK_ISA2_AVX10_2_512_UNSET \
   (OPTION_MASK_ISA2_AVX10_2_512 | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
@@ -1378,8 +1376,8 @@ ix86_handle_option (struct gcc_options *opts,
        }
       else
        {
-         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET;
-         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET;
+         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
          opts->x_ix86_no_avx10_1_explicit = 1;
        }
       return true;
@@ -1394,8 +1392,8 @@ ix86_handle_option (struct gcc_options *opts,
        }
       else
        {
-         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET;
-         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET;
+         opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
+         opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
          opts->x_ix86_no_avx10_1_explicit = 1;
        }
       return true;

diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 8976b031807a2d3f7d809fa880bb68b0159d3403..52e2dd3b65609d3cab6c9b7e223dcab3379c8306 100644 (file)
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -183,7 +183,6 @@ ISA_NAMES_TABLE_START
   ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4")
   ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
   ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
-  ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1")
   ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256, "-mavx10.1-256")
   ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_AVX10_1_512, "-mavx10.1-512")
   ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2_256, P_NONE, "-mavx10.2")

diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 7e85334d3d366fd28f5ccf5cb2116f752c8b8b20..b9be6708b0a17a4020f47bf9d256e25146798dc4 100644 (file)
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -1134,7 +1134,6 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
     IX86_ATTR_ISA ("apxf", OPT_mapxf),
     IX86_ATTR_ISA ("evex512", OPT_mevex512),
     IX86_ATTR_ISA ("usermsr", OPT_musermsr),
-    IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256),
     IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
     IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512),
     IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2_256),
@@ -2732,7 +2731,7 @@ ix86_option_override_internal (bool main_args_p,
          && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512)
              & opts->x_ix86_isa_flags2_explicit))
        {
-         warning (0, "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> "
+         warning (0, "%<-mno-avx10.1-256, -mno-avx10.1-512%> "
                      "cannot disable AVX512 instructions when "
                      "%<-mavx512XXX%>");
          /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is

diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 5c889b72cc58a4cebd0fa43b5b3b1c5bddb7cba8..0ee5c52be5da267da508695200c5f04cbc0e2f94 100644 (file)
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1373,11 +1373,6 @@ Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
 and AVX10.1-512 built-in functions and code generation.
 
-mavx10.1
-Target Alias(mavx10.1-256)
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-and AVX10.1 built-in functions and code generation.
-
 mavx10.2-256
 Target Mask(ISA2_AVX10_2_256) Var(ix86_isa_flags2) Save
 Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 065bd8b84e14ce53cb24fe0d55b05ac2232e9618..8ff850a150d15620ecb0a948b0469217c2c56945 100644 (file)
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7600,20 +7600,17 @@ Enable/disable the generation of the USER_MSR instructions.
 Enable/disable the generation of the APX features, including
 EGPR, PUSH2POP2, NDD and PPX.
 
-@cindex @code{target("avx10.1")} function attribute, x86
-@item avx10.1
-@itemx no-avx10.1
-Enable/disable the generation of the AVX10.1 instructions.
-
 @cindex @code{target("avx10.1-256")} function attribute, x86
 @item avx10.1-256
 @itemx no-avx10.1-256
-Enable/disable the generation of the AVX10.1 instructions.
+Enable the generation of the AVX10.1 instructions with 256 bit support.
+Disable the generation of the AVX10.1 instructions.
 
 @cindex @code{target("avx10.1-512")} function attribute, x86
 @item avx10.1-512
 @itemx no-avx10.1-512
-Enable/disable the generation of the AVX10.1 512 bit instructions.
+Enable the generation of the AVX10.1 instructions with 512 bit support.
+Disable the generation of the AVX10.1 instructions.
 
 @cindex @code{target("avx10.2")} function attribute, x86
 @item avx10.2

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 797775e90de9c21e3350898f4881c59ffe975143..d63812533fb506742b794398b98616f509e3cffe 100644 (file)
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2611,11 +2611,8 @@ Target supports compiling @code{avx} instructions.
 @item avx_runtime
 Target supports the execution of @code{avx} instructions.
 
-@item avx10.1
-Target supports the execution of @code{avx10.1} instructions.
-
 @item avx10.1-256
-Target supports the execution of @code{avx10.1} instructions.
+Target supports the execution of @code{avx10.1-256} instructions.
 
 @item avx10.1-512
 Target supports the execution of @code{avx10.1-512} instructions.

diff --git a/gcc/testsuite/gcc.target/i386/avx10-check.h b/gcc/testsuite/gcc.target/i386/avx10-check.h
index 87fa818f048bbb5d56ae840826d1592d071c6ec6..cabeedafc64c1412ebad007570a2f8460338fff3 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10-check.h
+++ b/gcc/testsuite/gcc.target/i386/avx10-check.h
@@ -38,7 +38,7 @@ int
 main ()
 {
   /* Run AVX10 test only if host has ISA support.  */
-  if (__builtin_cpu_supports ("avx10.1")
+  if (__builtin_cpu_supports ("avx10.1-256")
 #ifdef AVX10_2
       && __builtin_cpu_supports ("avx10.2")
 #endif

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
index cfd9662bb139069b36a863dd1ca02712dd8e1759..33ce99ed60abe75f806b7c2388498d7c4a139472 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
index 61f0e4db61b6bbcf5408e0b6dc6581d21f91ee31..ae1c77bbcbdc2282c3b18d69c039651924685f48 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-12.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
@@ -1,6 +1,6 @@
 /* { dg-do compile } */
 /* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */
-/* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
+/* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
 /* { dg-final { scan-assembler "%zmm" } } */
 
 #include "avx10_1-2.c"

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
index 8a1111900259ac5b1f5bdd0526eb16e01c982d31..e94ac8e1862ca7a2393dd2ee39d484ab06ca400c 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-13.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256" } */
 /* { dg-final { scan-assembler "%zmm" } } */
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
index 03222a7a0311d4b2ff5e9ddcfac9a7866f715ab5..76573e644fe5ec5981d33d691914d354c0895880 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-14.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
@@ -4,7 +4,7 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("avx10.1"))) __m512d
+__attribute__ ((target ("avx10.1-256"))) __m512d
 foo ()
 { /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */
   __m512d a, b;

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
index a19230f597bdb90c03eee409ea55419cb10d424c..09f125215dc2a0ef45c616fedd7edb513b15f05f 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-17.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
@@ -4,9 +4,9 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("no-avx10.1"))) __m512d
+__attribute__ ((target ("no-avx10.1-512"))) __m512d
 foo ()
-{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
   __m512d a, b;
   a = a + b;
   return a;

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
index 7aacc15aad944612255f6f991e1f2b9f6f7f03c6..7445ecfa548a66d613f9c60bb075efc8ee0f84f5 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-19.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
@@ -6,7 +6,7 @@ typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
 __attribute__ ((target ("avx512f"))) __m512d
 foo ()
-{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
+{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */
   __m512d a, b;
   a = a + b;
   return a;

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
index 27a7265df611c3623fc2e11926eec3c3ee903c72..0a1fcc9c0f863cad9f32b549b2dd17af5c19f82f 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-21.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mevex512 -Wno-psabi" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -mevex512 -Wno-psabi" } */
 /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
index 796262283d6883ea1bcc84ae1b12c108412aac69..cb649dc5538e2d88e19ccadf4d08f5f4d714aa35 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-22.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -Wno-psabi" } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
index 6e8d64d0f34c7c509cb35aabe388cea7b63e57f9..f31c63650ab35f50b512bfa4b4247c4aace7b44b 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-23.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
@@ -4,7 +4,7 @@
 
 typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
 
-__attribute__ ((target ("avx10.1"))) __m512d
+__attribute__ ((target ("avx10.1-256"))) __m512d
 foo ()
 { /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */
   __m512d a, b;

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-24.c b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
index 2e93f041760d0060aca5ff9dff61d402b92e193c..1bba0fb4b66d00b24bcc190a2faf2b48858a2a81 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-24.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-24.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 /* { dg-final { scan-assembler-not "%zmm" } } */
 
 typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
index 3be988a1a62bfba939fc4059e00f9b0e2632e3ab..a176f2749ce68e8ae6e6e82f8fe6dae1127fc80a 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
index 20b78ea951027d436c6f2968b5daa5e6bed6569e..3079cf14ef088c8b85df2c2e3570b4368a0841c7 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-5.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O0 -march=x86-64 -mavx10.1 -Wno-psabi" } */
+/* { dg-options "-O0 -march=x86-64 -mavx10.1-256 -Wno-psabi" } */
 /* { dg-final { scan-assembler-not ".%zmm" } } */
 
 #include "avx10_1-2.c"

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
index fbc92d5c4caed158345dfb53d8d14323f017890e..60dbd05c4a749b3e8f35f076a73ba2de4a89a380 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-6.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
+/* { dg-options "-O2 -march=x86-64 -mavx10.1-256" } */
 
 #include <immintrin.h>
 

diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
index 69b6c6a3e1ae0ef62d42239d81f5b24a79b7fc0f..ec930f72218fa04ee8f68873861fe52714b75035 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/avx10_1-8.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
@@ -1,4 +1,4 @@
 /* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */
+/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f -mno-evex512" } */
 
 #include "avx10_1-1.c"

diff --git a/gcc/testsuite/gcc.target/i386/pr117946.c b/gcc/testsuite/gcc.target/i386/pr117946.c
index 7304e01d1a7e5f2737061b1f17043a04ec8d03bb..e7b660bdf9b72f5aabfbc6b2150e44f6768deac7 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/pr117946.c
+++ b/gcc/testsuite/gcc.target/i386/pr117946.c
@@ -1,5 +1,5 @@
 /* { dg-do compile  { target { ! ia32 } } } */
-/* { dg-options "-O -favoid-store-forwarding -mavx10.1 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */
+/* { dg-options "-O -favoid-store-forwarding -mavx10.1-256 -mprefer-avx128 --param=store-forwarding-max-distance=128 -Wno-psabi" } */
 typedef __attribute__((__vector_size__ (64))) _Decimal32 V;
 
 void