RISC-V: Minimal support for svvptc extension.

This patch support svvptc extension[1].
To enable GCC to recognize and process svvptc extension correctly at compile time.

[1] https://github.com/riscv/riscv-svvptc

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: New extension.
	* common/config/riscv/riscv-ext-bitmask.def (RISCV_EXT_BITMASK): Ditto.
	* config/riscv/riscv.opt: New mask.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-44.c: New test.

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 49e8a41846ee76036eafa67c0177968ba756ba5e..4c9a72d1180a97beb8971305efa54411c8de7bec 100644 (file)
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -405,6 +405,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svpbmt",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"svvptc",  ISA_SPEC_CLASS_NONE, 1, 0},
 
   {"xcvmac", ISA_SPEC_CLASS_NONE, 1, 0},
   {"xcvalu", ISA_SPEC_CLASS_NONE, 1, 0},
@@ -1723,6 +1724,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
 
   RISCV_EXT_FLAG_ENTRY ("svinval", x_riscv_sv_subext, MASK_SVINVAL),
   RISCV_EXT_FLAG_ENTRY ("svnapot", x_riscv_sv_subext, MASK_SVNAPOT),
+  RISCV_EXT_FLAG_ENTRY ("svvptc", x_riscv_sv_subext, MASK_SVVPTC),
 
   RISCV_EXT_FLAG_ENTRY ("ztso", x_riscv_ztso_subext, MASK_ZTSO),
 

diff --git a/gcc/common/config/riscv/riscv-ext-bitmask.def b/gcc/common/config/riscv/riscv-ext-bitmask.def
index ca5df1740f3f11f9bd8c4cdbe43b376ccd30225b..a733533df98eeea99814f2a1438604ba206bd202 100644 (file)
--- a/gcc/common/config/riscv/riscv-ext-bitmask.def
+++ b/gcc/common/config/riscv/riscv-ext-bitmask.def
@@ -79,5 +79,6 @@ RISCV_EXT_BITMASK ("zcd",             1,  4)
 RISCV_EXT_BITMASK ("zcf",              1,  5)
 RISCV_EXT_BITMASK ("zcmop",            1,  6)
 RISCV_EXT_BITMASK ("zawrs",            1,  7)
+RISCV_EXT_BITMASK ("svvptc",           1,  8)
 
 #undef RISCV_EXT_BITMASK

diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index d7fa47f70806032b14e02499b3d8ce459f7d12f3..a6a61a83db1b7ea749436e4c0132cfec7ab00690 100644 (file)
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -466,6 +466,8 @@ Mask(SVINVAL) Var(riscv_sv_subext)
 
 Mask(SVNAPOT) Var(riscv_sv_subext)
 
+Mask(SVVPTC) Var(riscv_sv_subext)
+
 TargetVariable
 int riscv_ztso_subext
 

diff --git a/gcc/testsuite/gcc.target/riscv/arch-44.c b/gcc/testsuite/gcc.target/riscv/arch-44.c
new file mode 100644 (file)
index 0000000..80dc19a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-44.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_svvptc -mabi=lp64" } */
+int foo()
+{
+}