CPU_TYPE:=xscale
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.12
define Target/Description
Build firmware images for the IXP4xx XScale CPU
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FORCE_PCI=y
+# CONFIG_FRAMER is not set
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REALTEK_PHY=y
+CONFIG_REALTEK_PHY_HWMON=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_SCSI=y
-From ed23e07bf7a1896b6eaa85b773bb43b1fad66d4b Mon Sep 17 00:00:00 2001
+From eff2700d2ec99aac06fff0ad35cbc594bd3e04a8 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sat, 21 Dec 2024 00:07:11 +0100
-Subject: [PATCH] ARM: dts: ixp4xx: Fix up PCI on WG302
+Date: Mon, 10 Feb 2025 10:31:16 +0100
+Subject: [PATCH 1/2] ARM: dts: ixp4xx: Fix up PCI on WG302
Looking at the board file for WG302 v2 was not a good idea
because the GPIO IRQ for slot 2 differs, and v1 uses GPIO
10 instead of GPIO 9. Fix it up.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-2-6b752d745e04@linaro.org
---
.../dts/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
-From 1d22f422fca8875f6d2cb297f735d41fd5830000 Mon Sep 17 00:00:00 2001
+From f8a9ef38de91ddffa51255d15589c460bb6d9916 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 23 Dec 2024 17:50:52 +0100
-Subject: [PATCH] ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
+Date: Mon, 10 Feb 2025 10:31:17 +0100
+Subject: [PATCH 2/2] ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs
This adds GPIO LED indicators, the reset GPIO RESET
button on the Netgear WG302 v1 to the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/20250210-ixp4xx-dts-v1-3-6b752d745e04@linaro.org
---
.../ixp/intel-ixp42x-netgear-wg302v1.dts | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
+++ /dev/null
-From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Thu, 21 Sep 2023 00:12:42 +0200
-Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
-
-This makes it possible to provide basic clock output on pins
-14 and 15. The clocks are typically used by random electronics,
-not modeled in the device tree, so they just need to be provided
-on request.
-
-In order to not disturb old systems that require that the
-hardware defaults are kept in the clock setting bits, we only
-manipulate these if either device tree property is present.
-Once we know a device needs one of the clocks we can set it
-in the device tree.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
- 1 file changed, 48 insertions(+), 1 deletion(-)
-
---- a/drivers/gpio/gpio-ixp4xx.c
-+++ b/drivers/gpio/gpio-ixp4xx.c
-@@ -38,6 +38,18 @@
- #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
- #define IXP4XX_GPIO_STYLE_SIZE 3
-
-+/*
-+ * Clock output control register defines.
-+ */
-+#define IXP4XX_GPCLK_CLK0DC_SHIFT 0
-+#define IXP4XX_GPCLK_CLK0TC_SHIFT 4
-+#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0)
-+#define IXP4XX_GPCLK_MUX14 BIT(8)
-+#define IXP4XX_GPCLK_CLK1DC_SHIFT 16
-+#define IXP4XX_GPCLK_CLK1TC_SHIFT 20
-+#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16)
-+#define IXP4XX_GPCLK_MUX15 BIT(24)
-+
- /**
- * struct ixp4xx_gpio - IXP4 GPIO state container
- * @dev: containing device for this instance
-@@ -202,6 +214,8 @@ static int ixp4xx_gpio_probe(struct plat
- struct ixp4xx_gpio *g;
- struct gpio_irq_chip *girq;
- struct device_node *irq_parent;
-+ bool clk_14, clk_15;
-+ u32 val;
- int ret;
-
- g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
-@@ -231,7 +245,40 @@ static int ixp4xx_gpio_probe(struct plat
- */
- if (of_machine_is_compatible("dlink,dsm-g600-a") ||
- of_machine_is_compatible("iom,nas-100d"))
-- __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
-+ val = 0;
-+ else
-+ val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
-+
-+ /*
-+ * If either clock output is enabled explicitly in the device tree
-+ * we take full control of the clock by masking off all bits for
-+ * the clock control and selectively enabling them. Otherwise
-+ * we leave the hardware default settings.
-+ *
-+ * Enable clock outputs with default timings of requested clock.
-+ * If you need control over TC and DC, add these to the device
-+ * tree bindings and use them here.
-+ */
-+ clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
-+ clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
-+ if (clk_14 || clk_15) {
-+ val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
-+ val &= ~IXP4XX_GPCLK_CLK0_MASK;
-+ val &= ~IXP4XX_GPCLK_CLK1_MASK;
-+ if (clk_14) {
-+ val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
-+ val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
-+ val |= IXP4XX_GPCLK_MUX14;
-+ }
-+
-+ if (clk_15) {
-+ val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
-+ val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
-+ val |= IXP4XX_GPCLK_MUX15;
-+ }
-+ }
-+
-+ __raw_writel(val, g->base + IXP4XX_REG_GPCLK);
-
- /*
- * This is a very special big-endian ARM issue: when the IXP4xx is
+++ /dev/null
-From 6599df775e2cbb4988bdf8239acf4fbec70e5ef9 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sat, 23 Sep 2023 20:38:22 +0200
-Subject: [PATCH 3/4] net: ixp4xx_eth: Support changing the MTU
-
-As we don't specify the MTU in the driver, the framework
-will fall back to 1500 bytes and this doesn't work very
-well when we try to attach a DSA switch:
-
- eth1: mtu greater than device maximum
- ixp4xx_eth c800a000.ethernet eth1: error -22 setting
- MTU to 1504 to include DSA overhead
-
-After locating an out-of-tree patch in OpenWrt I found
-suitable code to set the MTU on the interface and ported
-it and updated it. Now the MTU gets set properly.
-
-Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/net/ethernet/xscale/ixp4xx_eth.c | 65 +++++++++++++++++++++++-
- 1 file changed, 64 insertions(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
-+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-@@ -24,6 +24,7 @@
- #include <linux/dma-mapping.h>
- #include <linux/dmapool.h>
- #include <linux/etherdevice.h>
-+#include <linux/if_vlan.h>
- #include <linux/io.h>
- #include <linux/kernel.h>
- #include <linux/net_tstamp.h>
-@@ -63,7 +64,15 @@
-
- #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
- #define REGS_SIZE 0x1000
--#define MAX_MRU 1536 /* 0x600 */
-+
-+/* MRU is said to be 14320 in a code dump, the SW manual says that
-+ * MRU/MTU is 16320 and includes VLAN and ethernet headers.
-+ * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161.
-+ *
-+ * FIXME: we have chosen the safe default (14320) but if you can test
-+ * jumboframes, experiment with 16320 and see what happens!
-+ */
-+#define MAX_MRU (14320 - VLAN_ETH_HLEN)
- #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
-
- #define NAPI_WEIGHT 16
-@@ -1182,6 +1191,54 @@ static void destroy_queues(struct port *
- }
- }
-
-+static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu)
-+{
-+ struct port *port = netdev_priv(dev);
-+ struct npe *npe = port->npe;
-+ int framesize, chunks;
-+ struct msg msg = {};
-+
-+ /* adjust for ethernet headers */
-+ framesize = new_mtu + VLAN_ETH_HLEN;
-+ /* max rx/tx 64 byte chunks */
-+ chunks = DIV_ROUND_UP(framesize, 64);
-+
-+ msg.cmd = NPE_SETMAXFRAMELENGTHS;
-+ msg.eth_id = port->id;
-+
-+ /* Firmware wants to know buffer size in 64 byte chunks */
-+ msg.byte2 = chunks << 8;
-+ msg.byte3 = chunks << 8;
-+
-+ msg.byte4 = msg.byte6 = framesize >> 8;
-+ msg.byte5 = msg.byte7 = framesize & 0xff;
-+
-+ if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH"))
-+ return -EIO;
-+ netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n",
-+ npe_name(npe), new_mtu);
-+
-+ return 0;
-+}
-+
-+static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu)
-+{
-+ int ret;
-+
-+ /* MTU can only be changed when the interface is up. We also
-+ * set the MTU from dev->mtu when opening the device.
-+ */
-+ if (dev->flags & IFF_UP) {
-+ ret = ixp4xx_do_change_mtu(dev, new_mtu);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
-+ dev->mtu = new_mtu;
-+
-+ return 0;
-+}
-+
- static int eth_open(struct net_device *dev)
- {
- struct port *port = netdev_priv(dev);
-@@ -1232,6 +1289,8 @@ static int eth_open(struct net_device *d
- if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
- return -EIO;
-
-+ ixp4xx_do_change_mtu(dev, dev->mtu);
-+
- if ((err = request_queues(port)) != 0)
- return err;
-
-@@ -1374,6 +1433,7 @@ static int eth_close(struct net_device *
- static const struct net_device_ops ixp4xx_netdev_ops = {
- .ndo_open = eth_open,
- .ndo_stop = eth_close,
-+ .ndo_change_mtu = ixp4xx_eth_change_mtu,
- .ndo_start_xmit = eth_xmit,
- .ndo_set_rx_mode = eth_set_mcast_list,
- .ndo_eth_ioctl = eth_ioctl,
-@@ -1488,6 +1548,9 @@ static int ixp4xx_eth_probe(struct platf
- ndev->dev.dma_mask = dev->dma_mask;
- ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
-
-+ ndev->min_mtu = ETH_MIN_MTU;
-+ ndev->max_mtu = MAX_MRU;
-+
- netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
-
- if (!(port->npe = npe_request(NPE_ID(port->id))))
+++ /dev/null
-From a1490c1e8a12a8286c6a34c3d277a519066fc51e Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sat, 7 Oct 2023 14:32:40 +0200
-Subject: [PATCH] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
-
-This is a USRobotics NAS/Firewall/router that has been supported
-by OpenWrt in the past. It had dedicated users so let's get it
-properly supported.
-
-Some debugging and fixing was provided by Howard Harte.
-
-Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v1-1-aded3d6ff6f1@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/intel/ixp/Makefile | 3 +-
- .../ixp/intel-ixp42x-usrobotics-usr8200.dts | 229 ++++++++++++++++++
- 2 files changed, 231 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
-
---- a/arch/arm/boot/dts/intel/ixp/Makefile
-+++ b/arch/arm/boot/dts/intel/ixp/Makefile
-@@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
- intel-ixp43x-gateworks-gw2358.dtb \
- intel-ixp42x-netgear-wg302v1.dtb \
- intel-ixp42x-arcom-vulcan.dtb \
-- intel-ixp42x-gateway-7001.dtb
-+ intel-ixp42x-gateway-7001.dtb \
-+ intel-ixp42x-usrobotics-usr8200.dtb
---- /dev/null
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
-@@ -0,0 +1,229 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for the USRobotics USR8200 firewall
-+ * VPN and NAS. Based on know-how from Peter Denison.
-+ *
-+ * This machine is based on IXP422, the USR internal codename
-+ * is "Jeeves".
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x.dtsi"
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+ model = "USRobotics USR8200";
-+ compatible = "usr,usr8200", "intel,ixp42x";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x00000000 0x4000000>;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200n8";
-+ stdout-path = "uart1:115200n8";
-+ };
-+
-+ aliases {
-+ /* These are switched around */
-+ serial0 = &uart1;
-+ serial1 = &uart0;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ ieee1394_led: led-1394 {
-+ label = "usr8200:green:1394";
-+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ usb1_led: led-usb1 {
-+ label = "usr8200:green:usb1";
-+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ usb2_led: led-usb2 {
-+ label = "usr8200:green:usb2";
-+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ wireless_led: led-wireless {
-+ /*
-+ * This LED is mounted inside the case but cannot be
-+ * seen from the outside: probably USR planned at one
-+ * point for the device to have a wireless card, then
-+ * changed their mind and didn't mount it, leaving the
-+ * LED in place.
-+ */
-+ label = "usr8200:green:wireless";
-+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ pwr_led: led-pwr {
-+ label = "usr8200:green:pwr";
-+ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ linux,default-trigger = "heartbeat";
-+ };
-+ };
-+
-+ gpio_keys {
-+ compatible = "gpio-keys";
-+
-+ button-reset {
-+ wakeup-source;
-+ linux,code = <KEY_RESTART>;
-+ label = "reset";
-+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ soc {
-+ bus@c4000000 {
-+ flash@0,0 {
-+ compatible = "intel,ixp4xx-flash", "cfi-flash";
-+ bank-width = <2>;
-+ /* Enable writes on the expansion bus */
-+ intel,ixp4xx-eb-write-enable = <1>;
-+ /* 16 MB of Flash mapped in at CS0 */
-+ reg = <0 0x00000000 0x1000000>;
-+
-+ partitions {
-+ compatible = "redboot-fis";
-+ /* Eraseblock at 0x0fe0000 */
-+ fis-index-block = <0x7f>;
-+ };
-+ };
-+ rtc@2,0 {
-+ /* EPSON RTC7301 DG DIL-capsule */
-+ compatible = "epson,rtc7301dg";
-+ /*
-+ * These timing settings were found in the boardfile patch:
-+ * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
-+ * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
-+ */
-+ intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
-+ intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
-+ intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
-+ intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
-+ intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
-+ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
-+ intel,ixp4xx-eb-byte-access-on-halfword = <0>;
-+ intel,ixp4xx-eb-mux-address-and-data = <0>;
-+ intel,ixp4xx-eb-ahb-split-transfers = <0>;
-+ intel,ixp4xx-eb-write-enable = <1>;
-+ intel,ixp4xx-eb-byte-access = <1>;
-+ /* 512 bytes at CS2 */
-+ reg = <2 0x00000000 0x0000200>;
-+ reg-io-width = <1>;
-+ native-endian;
-+ /* FIXME: try to check if there is an IRQ for the RTC? */
-+ };
-+ };
-+
-+ pci@c0000000 {
-+ status = "okay";
-+
-+ /*
-+ * Taken from USR8200 boardfile from OpenWrt
-+ *
-+ * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
-+ * We assume the same IRQ for all pins on the remaining slots, that
-+ * is what the boardfile was doing.
-+ */
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ interrupt-map =
-+ /* IDSEL 14 used for "Wireless" in the board file */
-+ <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
-+ /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
-+ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
-+ /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
-+ <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
-+ <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
-+ <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
-+ };
-+
-+ gpio@c8004000 {
-+ /* Enable clock out on GPIO 15 */
-+ intel,ixp4xx-gpio15-clkout;
-+ };
-+
-+ /* EthB WAN */
-+ ethernet@c8009000 {
-+ status = "okay";
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy9>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy9: ethernet-phy@9 {
-+ reg = <9>;
-+ };
-+
-+ /* The switch uses MDIO addresses 16 thru 31 */
-+ switch@16 {
-+ compatible = "marvell,mv88e6060";
-+ reg = <16>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 {
-+ reg = <0>;
-+ label = "lan1";
-+ };
-+
-+ port@1 {
-+ reg = <1>;
-+ label = "lan2";
-+ };
-+
-+ port@2 {
-+ reg = <2>;
-+ label = "lan3";
-+ };
-+
-+ port@3 {
-+ reg = <3>;
-+ label = "lan4";
-+ };
-+
-+ port@5 {
-+ /* Port 5 is the CPU port according to the MV88E6060 datasheet */
-+ reg = <5>;
-+ phy-mode = "rgmii-id";
-+ ethernet = <ðc>;
-+ label = "cpu";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+ };
-+ };
-+ };
-+ };
-+
-+ /* EthC LAN connected to the Marvell DSA Switch */
-+ ethc: ethernet@c800a000 {
-+ status = "okay";
-+ queue-rx = <&qmgr 4>;
-+ queue-txready = <&qmgr 21>;
-+ phy-mode = "rgmii";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+ };
-+};
+++ /dev/null
-From 98f3b5f44b9ae86c4a80185b57149867472a2570 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Fri, 20 Oct 2023 15:11:41 +0200
-Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
-
-The MV88E6060 switch has internal PHY registers at MDIO
-addresses 0x00..0x04. Tie each port to the corresponding
-PHY.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
-Signed-off-by: Arnd Bergmann <arnd@arndb.de>
----
- .../ixp/intel-ixp42x-usrobotics-usr8200.dts | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
-@@ -165,6 +165,24 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-+ /*
-+ * PHY 0..4 are internal to the MV88E6060 switch but appear
-+ * as independent devices.
-+ */
-+ phy0: ethernet-phy@0 {
-+ reg = <0>;
-+ };
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ phy2: ethernet-phy@2 {
-+ reg = <2>;
-+ };
-+ phy3: ethernet-phy@3 {
-+ reg = <3>;
-+ };
-+
-+ /* Altima AMI101L used by the WAN port */
- phy9: ethernet-phy@9 {
- reg = <9>;
- };
-@@ -181,21 +199,25 @@
- port@0 {
- reg = <0>;
- label = "lan1";
-+ phy-handle = <&phy0>;
- };
-
- port@1 {
- reg = <1>;
- label = "lan2";
-+ phy-handle = <&phy1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
-+ phy-handle = <&phy2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan4";
-+ phy-handle = <&phy3>;
- };
-
- port@5 {
+++ /dev/null
-From 89eccb6726d93c9c78997e91bd641b0e46bc3c5f Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Fri, 8 Sep 2023 12:49:48 +0200
-Subject: [PATCH] ARM: dts: ixp4xx-nslu2: Enable write on flash
-
-To upgrade the firmware and similar, the flash needs write
-access.
-
-Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-1-98d36264ed6d@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
-@@ -101,6 +101,8 @@
- flash@0,0 {
- compatible = "intel,ixp4xx-flash", "cfi-flash";
- bank-width = <2>;
-+ /* Enable writes on the expansion bus */
-+ intel,ixp4xx-eb-write-enable = <1>;
- /*
- * 8 MB of Flash in 0x20000 byte blocks
- * mapped in at CS0.
+++ /dev/null
-From deb93908958e74dffbef1ce6a1cc2f82ac4f96ed Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Fri, 8 Sep 2023 12:49:49 +0200
-Subject: [PATCH] ARM: dts: ixp4xx: Use right restart keycode
-
-The "reset" key on a few IXP4xx routers were sending KEY_ESC
-but what we want to send is KEY_RESTART which will make
-OpenWrt and similar userspace do a controlled reboot.
-
-Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-2-98d36264ed6d@linaro.org
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts | 2 +-
- arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts | 2 +-
- arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts | 2 +-
- arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 +-
- 4 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
-@@ -57,7 +57,7 @@
-
- button-reset {
- wakeup-source;
-- linux,code = <KEY_ESC>;
-+ linux,code = <KEY_RESTART>;
- label = "reset";
- gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
- };
---- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
-@@ -44,7 +44,7 @@
- };
- button-reset {
- wakeup-source;
-- linux,code = <KEY_ESC>;
-+ linux,code = <KEY_RESTART>;
- label = "reset";
- gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
- };
---- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
-@@ -63,7 +63,7 @@
- };
- button-reset {
- wakeup-source;
-- linux,code = <KEY_ESC>;
-+ linux,code = <KEY_RESTART>;
- label = "reset";
- gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
- };
---- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
-+++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
-@@ -65,7 +65,7 @@
- };
- button-reset {
- wakeup-source;
-- linux,code = <KEY_ESC>;
-+ linux,code = <KEY_RESTART>;
- label = "reset";
- gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
- };
projects / thirdparty / openwrt.git / commitdiff
