+2023-06-19 Jin Ma <jinma@linux.alibaba.com>
+
+ * config/riscv/riscv.cc (riscv_compute_frame_info): Allocate frame for FCSR.
+ (riscv_for_each_saved_reg): Save and restore FCSR in interrupt functions.
+ * config/riscv/riscv.md (riscv_frcsr): New patterns.
+ (riscv_fscsr): Likewise.
+
+2023-06-19 Toru Kisuki <tkisuki@tachyum.com>
+
+ PR rtl-optimization/110305
+ * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
+ Handle HONOR_SNANS for x + 0.0.
+
+2023-06-19 Jan Hubicka <jh@suse.cz>
+
+ PR tree-optimization/109811
+ PR tree-optimization/109849
+ * passes.def: Add phiprop to early optimization passes.
+ * tree-ssa-phiprop.cc: Allow clonning.
+
+2023-06-19 Tamar Christina <tamar.christina@arm.com>
+
+ * config/aarch64/aarch64.md (arches): Add nosimd.
+ (*mov<mode>_aarch64, *movsi_aarch64, *movdi_aarch64): Rewrite to
+ compact syntax.
+
+2023-06-19 Tamar Christina <tamar.christina@arm.com>
+ Omar Tahir <Omar.Tahir2@arm.com>
+
+ * gensupport.cc (class conlist, add_constraints, add_attributes,
+ skip_spaces, expect_char, preprocess_compact_syntax,
+ parse_section_layout, parse_section, convert_syntax): New.
+ (process_rtx): Check for conversion.
+ * genoutput.cc (process_template): Check for unresolved iterators.
+ (class data): Add compact_syntax_p.
+ (gen_insn): Use it.
+ * gensupport.h (compact_syntax): New.
+ (hash-set.h): Include.
+ * doc/md.texi: Document it.
+
+2023-06-19 Uros Bizjak <ubizjak@gmail.com>
+
+ * recog.h (check_asm_operands): Change return type from int to bool.
+ (insn_invalid_p): Ditto.
+ (verify_changes): Ditto.
+ (apply_change_group): Ditto.
+ (constrain_operands): Ditto.
+ (constrain_operands_cached): Ditto.
+ (validate_replace_rtx_subexp): Ditto.
+ (validate_replace_rtx): Ditto.
+ (validate_replace_rtx_part): Ditto.
+ (validate_replace_rtx_part_nosimplify): Ditto.
+ (added_clobbers_hard_reg_p): Ditto.
+ (peep2_regno_dead_p): Ditto.
+ (peep2_reg_dead_p): Ditto.
+ (store_data_bypass_p): Ditto.
+ (if_test_bypass_p): Ditto.
+ * rtl.h (split_all_insns_noflow): Change
+ return type from unsigned int to void.
+ * genemit.cc (output_added_clobbers_hard_reg_p): Change return type
+ of generated added_clobbers_hard_reg_p from int to bool and adjust
+ function body accordingly. Change "used" variable type from
+ int to bool.
+ * recog.cc (check_asm_operands): Change return type
+ from int to bool and adjust function body accordingly.
+ (insn_invalid_p): Ditto. Change "is_asm" variable to bool.
+ (verify_changes): Change return type from int to bool.
+ (apply_change_group): Change return type from int to bool
+ and adjust function body accordingly.
+ (validate_replace_rtx_subexp): Change return type from int to bool.
+ (validate_replace_rtx): Ditto.
+ (validate_replace_rtx_part): Ditto.
+ (validate_replace_rtx_part_nosimplify): Ditto.
+ (constrain_operands_cached): Ditto.
+ (constrain_operands): Ditto. Change "lose" and "win"
+ variables type from int to bool.
+ (split_all_insns_noflow): Change return type from unsigned int
+ to void and adjust function body accordingly.
+ (peep2_regno_dead_p): Change return type from int to bool.
+ (peep2_reg_dead_p): Ditto.
+ (peep2_find_free_register): Change "success"
+ variable type from int to bool
+ (store_data_bypass_p_1): Change return type from int to bool.
+ (store_data_bypass_p): Ditto.
+
+2023-06-19 Li Xu <xuli1@eswincomputing.com>
+
+ * config/riscv/vector-iterators.md: zvfh/zvfhmin depends on the
+ Zve32f extension.
+
+2023-06-19 Pan Li <pan2.li@intel.com>
+
+ PR target/110299
+ * config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
+ modes.
+ * config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,
+ VWLMUL1_ZVE32, VI_ZVE64, VI_ZVE32, VWI, VWI_ZVE64, VWI_ZVE32,
+ VF_ZVE63 and VF_ZVE32.
+ * config/riscv/vector.md
+ (@pred_widen_reduc_plus<v_su><mode><vwlmul1>): Removed.
+ (@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve64>): Ditto.
+ (@pred_widen_reduc_plus<v_su><mode><vwlmul1_zve32>): Ditto.
+ (@pred_widen_reduc_plus<order><mode><vwlmul1>): Ditto.
+ (@pred_widen_reduc_plus<order><mode><vwlmul1_zve64>): Ditto.
+ (@pred_widen_reduc_plus<v_su><VQI:mode><VHI_LMUL1:mode>): New pattern.
+ (@pred_widen_reduc_plus<v_su><VHI:mode><VSI_LMUL1:mode>): Ditto.
+ (@pred_widen_reduc_plus<v_su><VSI:mode><VDI_LMUL1:mode>): Ditto.
+ (@pred_widen_reduc_plus<order><VHF:mode><VSF_LMUL1:mode>): Ditto.
+ (@pred_widen_reduc_plus<order><VSF:mode><VDF_LMUL1:mode>): Ditto.
+
+2023-06-19 Pan Li <pan2.li@intel.com>
+
+ PR target/110277
+ * config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for
+ ret_mode.
+ * config/riscv/vector-iterators.md: Add VHF, VSF, VDF,
+ VHF_LMUL1, VSF_LMUL1, VDF_LMUL1, and remove unused attr.
+ * config/riscv/vector.md (@pred_reduc_<reduc><mode><vlmul1>): Removed.
+ (@pred_reduc_<reduc><mode><vlmul1_zve64>): Ditto.
+ (@pred_reduc_<reduc><mode><vlmul1_zve32>): Ditto.
+ (@pred_reduc_plus<order><mode><vlmul1>): Ditto.
+ (@pred_reduc_plus<order><mode><vlmul1_zve32>): Ditto.
+ (@pred_reduc_plus<order><mode><vlmul1_zve64>): Ditto.
+ (@pred_reduc_<reduc><VHF:mode><VHF_LMUL1:mode>): New pattern.
+ (@pred_reduc_<reduc><VSF:mode><VSF_LMUL1:mode>): Ditto.
+ (@pred_reduc_<reduc><VDF:mode><VDF_LMUL1:mode>): Ditto.
+ (@pred_reduc_plus<order><VHF:mode><VHF_LMUL1:mode>): Ditto.
+ (@pred_reduc_plus<order><VSF:mode><VSF_LMUL1:mode>): Ditto.
+ (@pred_reduc_plus<order><VDF:mode><VDF_LMUL1:mode>): Ditto.
+
+2023-06-19 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn.cc (gcn_expand_divmod_libfunc): New function.
+ (gcn_init_libfuncs): Add div and mod functions for all modes.
+ Add placeholders for divmod functions.
+ (TARGET_EXPAND_DIVMOD_LIBFUNC): Define.
+
+2023-06-19 Andrew Stubbs <ams@codesourcery.com>
+
+ * tree-vect-generic.cc: Include optabs-libfuncs.h.
+ (get_compute_type): Check optab_libfunc.
+ * tree-vect-stmts.cc: Include optabs-libfuncs.h.
+ (vectorizable_operation): Check optab_libfunc.
+
+2023-06-19 Andrew Stubbs <ams@codesourcery.com>
+
+ * config/gcn/gcn-protos.h (vgpr_4reg_mode_p): New function.
+ * config/gcn/gcn-valu.md (V_4REG, V_4REG_ALT): New iterators.
+ (V_MOV, V_MOV_ALT): Likewise.
+ (scalar_mode, SCALAR_MODE): Add TImode.
+ (vnsi, VnSI, vndi, VnDI): Likewise.
+ (vec_merge, vec_merge_with_clobber, vec_merge_with_vcc): Use V_MOV.
+ (mov<mode>, mov<mode>_unspec): Use V_MOV.
+ (*mov<mode>_4reg): New insn.
+ (mov<mode>_exec): New 4reg variant.
+ (mov<mode>_sgprbase): Likewise.
+ (reload_in<mode>, reload_out<mode>): Use V_MOV.
+ (vec_set<mode>): Likewise.
+ (vec_duplicate<mode><exec>): New 4reg variant.
+ (vec_extract<mode><scalar_mode>): Likewise.
+ (vec_extract<V_ALL:mode><V_ALL_ALT:mode>): Rename to ...
+ (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): ... this, and use V_MOV.
+ (vec_extract<V_4REG:mode><V_4REG_ALT:mode>_nop): New 4reg variant.
+ (fold_extract_last_<mode>): Use V_MOV.
+ (vec_init<V_ALL:mode><V_ALL_ALT:mode>): Rename to ...
+ (vec_init<V_MOV:mode><V_MOV_ALT:mode>): ... this, and use V_MOV.
+ (gather_load<mode><vnsi>, gather<mode>_expr<exec>,
+ gather<mode>_insn_1offset<exec>, gather<mode>_insn_1offset_ds<exec>,
+ gather<mode>_insn_2offsets<exec>): Use V_MOV.
+ (scatter_store<mode><vnsi>, scatter<mode>_expr<exec_scatter>,
+ scatter<mode>_insn_1offset<exec_scatter>,
+ scatter<mode>_insn_1offset_ds<exec_scatter>,
+ scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
+ (maskload<mode>di, maskstore<mode>di, mask_gather_load<mode><vnsi>,
+ mask_scatter_store<mode><vnsi>): Likewise.
+ * config/gcn/gcn.cc (gcn_class_max_nregs): Use vgpr_4reg_mode_p.
+ (gcn_hard_regno_mode_ok): Likewise.
+ (GEN_VNM): Add TImode support.
+ (USE_TI): New macro. Separate TImode operations from non-TImode ones.
+ (gcn_vector_mode_supported_p): Add V64TImode, V32TImode, V16TImode,
+ V8TImode, and V2TImode.
+ (print_operand): Add 'J' and 'K' print codes.
+
+2023-06-19 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/110298
+ * tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely):
+ Clear number of iterations info before cleaning up the CFG.
+
+2023-06-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
+ Simplify vec_concat of lowpart subreg and high part vec_select.
+
+2023-06-19 Tobias Burnus <tobias@codesourcery.com>
+
+ * doc/invoke.texi (-foffload-options): Remove '-O3' from the examples.
+
+2023-06-19 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors):
+ Handle null niters_skip.
+
+2023-06-19 Richard Biener <rguenther@suse.de>
+
+ * config/aarch64/aarch64.cc
+ (aarch64_vector_costs::analyze_loop_vinfo): Fix reference
+ to LOOP_VINFO_MASKS.
+
+2023-06-19 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
+
+ PR target/105523
+ * common/config/avr/avr-common.cc: Remove setting
+ of OPT_fdelete_null_pointer_checks.
+ * config/avr/avr.cc (avr_option_override): Clear
+ flag_delete_null_pointer_checks if zero_address_valid.
+ (avr_addr_space_zero_address_valid): New function.
+ (TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID): Provide target
+ hook.
+
+2023-06-19 Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
+ Robin Dapp <rdapp.gcc@gmail.com>
+
+ * doc/md.texi: Add len_mask{load,store}.
+ * genopinit.cc (main): Ditto.
+ (CMP_NAME): Ditto.
+ * internal-fn.cc (len_maskload_direct): Ditto.
+ (len_maskstore_direct): Ditto.
+ (expand_call_mem_ref): Ditto.
+ (expand_partial_load_optab_fn): Ditto.
+ (expand_len_maskload_optab_fn): Ditto.
+ (expand_partial_store_optab_fn): Ditto.
+ (expand_len_maskstore_optab_fn): Ditto.
+ (direct_len_maskload_optab_supported_p): Ditto.
+ (direct_len_maskstore_optab_supported_p): Ditto.
+ * internal-fn.def (LEN_MASK_LOAD): Ditto.
+ (LEN_MASK_STORE): Ditto.
+ * optabs.def (OPTAB_CD): Ditto.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/autovec.md (<optab><mode>2): Add unop expanders.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/autovec.md (<optab><mode>3): Implement binop
+ expander.
+ * config/riscv/riscv-protos.h (emit_vlmax_fp_insn): Declare.
+ (enum vxrm_field_enum): Rename this...
+ (enum fixed_point_rounding_mode): ...to this.
+ (enum frm_field_enum): Rename this...
+ (enum floating_point_rounding_mode): ...to this.
+ * config/riscv/riscv-v.cc (emit_vlmax_fp_insn): New function
+ * config/riscv/riscv.cc (riscv_const_insns): Clarify const
+ vector handling.
+ (riscv_libgcc_floating_mode_supported_p): Adjust comment.
+ (riscv_excess_precision): Do not convert to float for ZVFH.
+ * config/riscv/vector-iterators.md: Add VF_AUTO iterator.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/vector-iterators.md: Add VI_QH iterator.
+ * config/riscv/autovec-opt.md
+ (@pred_extract_first_sextdi<mode>): New vmv.x.s pattern
+ that includes sign extension.
+ (@pred_extract_first_sextsi<mode>): Dito for SImode.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * config/riscv/autovec.md (vec_set<mode>): Implement.
+ (vec_extract<mode><vel>): Implement.
+ * config/riscv/riscv-protos.h (enum insn_type): Add slide insn.
+ (emit_vlmax_slide_insn): Declare.
+ (emit_nonvlmax_slide_tu_insn): Declare.
+ (emit_scalar_move_insn): Export.
+ (emit_nonvlmax_integer_move_insn): Export.
+ * config/riscv/riscv-v.cc (emit_vlmax_slide_insn): New function.
+ (emit_nonvlmax_slide_tu_insn): New function.
+ (emit_vlmax_masked_mu_insn): No change.
+ (emit_vlmax_integer_move_insn): Export.
+
+2023-06-19 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (enum vect_partial_vector_style): New.
+ (_loop_vec_info::partial_vector_style): Likewise.
+ (LOOP_VINFO_PARTIAL_VECTORS_STYLE): Likewise.
+ (rgroup_controls::compare_type): Add.
+ (vec_loop_masks): Change from a typedef to auto_vec<>
+ to a structure.
+ * tree-vect-loop-manip.cc (vect_set_loop_condition_partial_vectors):
+ Adjust. Convert niters_skip to compare_type.
+ (vect_set_loop_condition_partial_vectors_avx512): New function
+ implementing the AVX512 partial vector codegen.
+ (vect_set_loop_condition): Dispatch to the correct
+ vect_set_loop_condition_partial_vectors_* function based on
+ LOOP_VINFO_PARTIAL_VECTORS_STYLE.
+ (vect_prepare_for_masked_peels): Compute LOOP_VINFO_MASK_SKIP_NITERS
+ in the original niter type.
+ * tree-vect-loop.cc (_loop_vec_info::_loop_vec_info): Initialize
+ partial_vector_style.
+ (can_produce_all_loop_masks_p): Adjust.
+ (vect_verify_full_masking): Produce the rgroup_controls vector
+ here. Set LOOP_VINFO_PARTIAL_VECTORS_STYLE on success.
+ (vect_verify_full_masking_avx512): New function implementing
+ verification of AVX512 style masking.
+ (vect_verify_loop_lens): Set LOOP_VINFO_PARTIAL_VECTORS_STYLE.
+ (vect_analyze_loop_2): Also try AVX512 style masking.
+ Adjust condition.
+ (vect_estimate_min_profitable_iters): Implement AVX512 style
+ mask producing cost.
+ (vect_record_loop_mask): Do not build the rgroup_controls
+ vector here but record masks in a hash-set.
+ (vect_get_loop_mask): Implement AVX512 style mask query,
+ complementing the existing while_ult style.
+
+2023-06-19 Richard Biener <rguenther@suse.de>
+
+ * tree-vectorizer.h (vect_get_loop_mask): Add loop_vec_info
+ argument.
+ * tree-vect-loop.cc (vect_get_loop_mask): Likewise.
+ (vectorize_fold_left_reduction): Adjust.
+ (vect_transform_reduction): Likewise.
+ (vectorizable_live_operation): Likewise.
+ * tree-vect-stmts.cc (vectorizable_call): Likewise.
+ (vectorizable_operation): Likewise.
+ (vectorizable_store): Likewise.
+ (vectorizable_load): Likewise.
+ (vectorizable_condition): Likewise.
+
+2023-06-19 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
+
+ PR target/110086
+ * config/avr/avr.opt (mgas-isr-prologues, mmain-is-OS_task):
+ Add Optimization option property.
+
+2023-06-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+
+ * config/xtensa/xtensa.cc (xtensa_constantsynth_2insn):
+ Add new pattern for the abovementioned case.
+
+2023-06-19 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
+
+ * config/xtensa/xtensa.cc
+ (TARGET_MEMORY_MOVE_COST, xtensa_memory_move_cost): Remove.
+
+2023-06-19 Jiufu Guo <guojiufu@linux.ibm.com>
+
+ * config/rs6000/rs6000.cc (TARGET_CONST_ANCHOR): New define.
+
+2023-06-19 Jiufu Guo <guojiufu@linux.ibm.com>
+
+ * cse.cc (try_const_anchors): Check SCALAR_INT_MODE.
+
+2023-06-19 liuhongt <hongtao.liu@intel.com>
+
+ PR target/110235
+ * config/i386/sse.md (<sse2_avx2>_packsswb<mask_name>):
+ Substitute with ..
+ (sse2_packsswb<mask_name>): .. this, ..
+ (avx2_packsswb<mask_name>): .. this and ..
+ (avx512bw_packsswb<mask_name>): .. this.
+ (<sse2_avx2>_packssdw<mask_name>): Substitute with ..
+ (sse2_packssdw<mask_name>): .. this, ..
+ (avx2_packssdw<mask_name>): .. this and ..
+ (avx512bw_packssdw<mask_name>): .. this.
+
+2023-06-19 liuhongt <hongtao.liu@intel.com>
+
+ PR target/110235
+ * config/i386/i386-expand.cc (ix86_split_mmx_pack): Use
+ UNSPEC_US_TRUNCATE instead of original us_truncate for
+ packusdw/packuswb.
+ * config/i386/mmx.md (mmx_pack<s_trunsuffix>swb): Substitute
+ with ..
+ (mmx_packsswb): .. this and ..
+ (mmx_packuswb): .. this.
+ (mmx_packusdw): Use UNSPEC_US_TRUNCATE instead of original
+ us_truncate.
+ (s_trunsuffix): Removed code iterator.
+ (any_s_truncate): Ditto.
+ * config/i386/sse.md (<sse2_avx2>_packuswb<mask_name>): Use
+ UNSPEC_US_TRUNCATE instead of original us_truncate.
+ (<sse4_1_avx2>_packusdw<mask_name>): Ditto.
+ * config/i386/i386.md (UNSPEC_US_TRUNCATE): New unspec_c_enum.
+
2023-06-18 Pan Li <pan2.li@intel.com>
* config/riscv/riscv-vector-builtins-bases.cc: Fix one typo.
+2023-06-19 Jin Ma <jinma@linux.alibaba.com>
+
+ * gcc.target/riscv/interrupt-fcsr-1.c: New test.
+ * gcc.target/riscv/interrupt-fcsr-2.c: New test.
+ * gcc.target/riscv/interrupt-fcsr-3.c: New test.
+
+2023-06-19 Jan Hubicka <jh@suse.cz>
+
+ PR tree-optimization/109811
+ PR tree-optimization/109849
+ * gcc.dg/tree-ssa/phiprop-1.c: New test.
+ * gcc.dg/tree-ssa/pr21463.c: Adjust template.
+
+2023-06-19 Pan Li <pan2.li@intel.com>
+
+ PR target/110299
+ * gcc.target/riscv/rvv/base/pr110299-1.c: New test.
+ * gcc.target/riscv/rvv/base/pr110299-1.h: New test.
+ * gcc.target/riscv/rvv/base/pr110299-2.c: New test.
+ * gcc.target/riscv/rvv/base/pr110299-2.h: New test.
+ * gcc.target/riscv/rvv/base/pr110299-3.c: New test.
+ * gcc.target/riscv/rvv/base/pr110299-3.h: New test.
+ * gcc.target/riscv/rvv/base/pr110299-4.c: New test.
+ * gcc.target/riscv/rvv/base/pr110299-4.h: New test.
+
+2023-06-19 Pan Li <pan2.li@intel.com>
+
+ PR target/110277
+ * gcc.target/riscv/rvv/base/pr110277-1.c: New test.
+ * gcc.target/riscv/rvv/base/pr110277-1.h: New test.
+ * gcc.target/riscv/rvv/base/pr110277-2.c: New test.
+ * gcc.target/riscv/rvv/base/pr110277-2.h: New test.
+
+2023-06-19 Andrew Stubbs <ams@codesourcery.com>
+
+ * gcc.dg/tree-ssa/predcom-2.c: Avoid vectors on amdgcn.
+ * gcc.dg/unroll-8.c: Likewise.
+ * gcc.dg/vect/slp-26.c: Change expected results on amdgdn.
+ * lib/target-supports.exp
+ (check_effective_target_vect_int_mod): Add amdgcn.
+ (check_effective_target_divmod): Likewise.
+ * gcc.target/gcn/simd-math-3-16.c: New test.
+ * gcc.target/gcn/simd-math-3-2.c: New test.
+ * gcc.target/gcn/simd-math-3-32.c: New test.
+ * gcc.target/gcn/simd-math-3-4.c: New test.
+ * gcc.target/gcn/simd-math-3-8.c: New test.
+ * gcc.target/gcn/simd-math-3-char-16.c: New test.
+ * gcc.target/gcn/simd-math-3-char-2.c: New test.
+ * gcc.target/gcn/simd-math-3-char-32.c: New test.
+ * gcc.target/gcn/simd-math-3-char-4.c: New test.
+ * gcc.target/gcn/simd-math-3-char-8.c: New test.
+ * gcc.target/gcn/simd-math-3-char-run-16.c: New test.
+ * gcc.target/gcn/simd-math-3-char-run-2.c: New test.
+ * gcc.target/gcn/simd-math-3-char-run-32.c: New test.
+ * gcc.target/gcn/simd-math-3-char-run-4.c: New test.
+ * gcc.target/gcn/simd-math-3-char-run-8.c: New test.
+ * gcc.target/gcn/simd-math-3-char-run.c: New test.
+ * gcc.target/gcn/simd-math-3-char.c: New test.
+ * gcc.target/gcn/simd-math-3-long-16.c: New test.
+ * gcc.target/gcn/simd-math-3-long-2.c: New test.
+ * gcc.target/gcn/simd-math-3-long-32.c: New test.
+ * gcc.target/gcn/simd-math-3-long-4.c: New test.
+ * gcc.target/gcn/simd-math-3-long-8.c: New test.
+ * gcc.target/gcn/simd-math-3-long-run-16.c: New test.
+ * gcc.target/gcn/simd-math-3-long-run-2.c: New test.
+ * gcc.target/gcn/simd-math-3-long-run-32.c: New test.
+ * gcc.target/gcn/simd-math-3-long-run-4.c: New test.
+ * gcc.target/gcn/simd-math-3-long-run-8.c: New test.
+ * gcc.target/gcn/simd-math-3-long-run.c: New test.
+ * gcc.target/gcn/simd-math-3-long.c: New test.
+ * gcc.target/gcn/simd-math-3-run-16.c: New test.
+ * gcc.target/gcn/simd-math-3-run-2.c: New test.
+ * gcc.target/gcn/simd-math-3-run-32.c: New test.
+ * gcc.target/gcn/simd-math-3-run-4.c: New test.
+ * gcc.target/gcn/simd-math-3-run-8.c: New test.
+ * gcc.target/gcn/simd-math-3-run.c: New test.
+ * gcc.target/gcn/simd-math-3-short-16.c: New test.
+ * gcc.target/gcn/simd-math-3-short-2.c: New test.
+ * gcc.target/gcn/simd-math-3-short-32.c: New test.
+ * gcc.target/gcn/simd-math-3-short-4.c: New test.
+ * gcc.target/gcn/simd-math-3-short-8.c: New test.
+ * gcc.target/gcn/simd-math-3-short-run-16.c: New test.
+ * gcc.target/gcn/simd-math-3-short-run-2.c: New test.
+ * gcc.target/gcn/simd-math-3-short-run-32.c: New test.
+ * gcc.target/gcn/simd-math-3-short-run-4.c: New test.
+ * gcc.target/gcn/simd-math-3-short-run-8.c: New test.
+ * gcc.target/gcn/simd-math-3-short-run.c: New test.
+ * gcc.target/gcn/simd-math-3-short.c: New test.
+ * gcc.target/gcn/simd-math-3.c: New test.
+ * gcc.target/gcn/simd-math-4-char-run.c: New test.
+ * gcc.target/gcn/simd-math-4-char.c: New test.
+ * gcc.target/gcn/simd-math-4-long-run.c: New test.
+ * gcc.target/gcn/simd-math-4-long.c: New test.
+ * gcc.target/gcn/simd-math-4-run.c: New test.
+ * gcc.target/gcn/simd-math-4-short-run.c: New test.
+ * gcc.target/gcn/simd-math-4-short.c: New test.
+ * gcc.target/gcn/simd-math-4.c: New test.
+ * gcc.target/gcn/simd-math-5-16.c: New test.
+ * gcc.target/gcn/simd-math-5-32.c: New test.
+ * gcc.target/gcn/simd-math-5-4.c: New test.
+ * gcc.target/gcn/simd-math-5-8.c: New test.
+ * gcc.target/gcn/simd-math-5-char-16.c: New test.
+ * gcc.target/gcn/simd-math-5-char-32.c: New test.
+ * gcc.target/gcn/simd-math-5-char-4.c: New test.
+ * gcc.target/gcn/simd-math-5-char-8.c: New test.
+ * gcc.target/gcn/simd-math-5-char-run-16.c: New test.
+ * gcc.target/gcn/simd-math-5-char-run-32.c: New test.
+ * gcc.target/gcn/simd-math-5-char-run-4.c: New test.
+ * gcc.target/gcn/simd-math-5-char-run-8.c: New test.
+ * gcc.target/gcn/simd-math-5-char-run.c: New test.
+ * gcc.target/gcn/simd-math-5-char.c: New test.
+ * gcc.target/gcn/simd-math-5-long-16.c: New test.
+ * gcc.target/gcn/simd-math-5-long-32.c: New test.
+ * gcc.target/gcn/simd-math-5-long-4.c: New test.
+ * gcc.target/gcn/simd-math-5-long-8.c: New test.
+ * gcc.target/gcn/simd-math-5-long-run-16.c: New test.
+ * gcc.target/gcn/simd-math-5-long-run-32.c: New test.
+ * gcc.target/gcn/simd-math-5-long-run-4.c: New test.
+ * gcc.target/gcn/simd-math-5-long-run-8.c: New test.
+ * gcc.target/gcn/simd-math-5-long-run.c: New test.
+ * gcc.target/gcn/simd-math-5-long.c: New test.
+ * gcc.target/gcn/simd-math-5-run-16.c: New test.
+ * gcc.target/gcn/simd-math-5-run-32.c: New test.
+ * gcc.target/gcn/simd-math-5-run-4.c: New test.
+ * gcc.target/gcn/simd-math-5-run-8.c: New test.
+ * gcc.target/gcn/simd-math-5-run.c: New test.
+ * gcc.target/gcn/simd-math-5-short-16.c: New test.
+ * gcc.target/gcn/simd-math-5-short-32.c: New test.
+ * gcc.target/gcn/simd-math-5-short-4.c: New test.
+ * gcc.target/gcn/simd-math-5-short-8.c: New test.
+ * gcc.target/gcn/simd-math-5-short-run-16.c: New test.
+ * gcc.target/gcn/simd-math-5-short-run-32.c: New test.
+ * gcc.target/gcn/simd-math-5-short-run-4.c: New test.
+ * gcc.target/gcn/simd-math-5-short-run-8.c: New test.
+ * gcc.target/gcn/simd-math-5-short-run.c: New test.
+ * gcc.target/gcn/simd-math-5-short.c: New test.
+ * gcc.target/gcn/simd-math-5.c: New test.
+
+2023-06-19 Richard Biener <rguenther@suse.de>
+
+ * gcc.dg/vect/vect-bic-bitmask-2.c: Remove -save-temps.
+ * gcc.dg/vect/vect-bic-bitmask-3.c: Likewise.
+ * gcc.dg/vect/vect-bic-bitmask-4.c: Likewise.
+ * gcc.dg/vect/vect-bic-bitmask-5.c: Likewise.
+ * gcc.dg/vect/vect-bic-bitmask-6.c: Likewise.
+ * gcc.dg/vect/vect-bic-bitmask-8.c: Likewise.
+ * gcc.dg/vect/vect-bic-bitmask-9.c: Likewise.
+ * gcc.dg/vect/vect-bic-bitmask-10.c: Likewise.
+ * gcc.dg/vect/vect-bic-bitmask-11.c: Likewise.
+
+2023-06-19 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/110298
+ * gcc.dg/torture/pr110298.c: New testcase.
+
+2023-06-19 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * gcc.target/aarch64/simd/low-high-combine_1.c: New test.
+
+2023-06-19 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
+
+ PR target/105523
+ * lib/target-supports.exp
+ (check_effective_target_keeps_null_pointer_checks): Add
+ avr.
+ * gcc.target/avr/pr105523.c: New test.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/unop/abs-template.h: Add FP.
+ * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/unop/vneg-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/unop/vneg-rv64gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/unop/vneg-template.h: Add FP.
+ * gcc.target/riscv/rvv/autovec/unop/abs-zvfh-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/unop/vfsqrt-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv32gcv.c: New test.
+ * gcc.target/riscv/rvv/autovec/unop/vfsqrt-rv64gcv.c: New test.
+ * gcc.target/riscv/rvv/autovec/unop/vfsqrt-template.h: New test.
+ * gcc.target/riscv/rvv/autovec/unop/vfsqrt-zvfh-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/unop/vneg-zvfh-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/zvfhmin-1.c: Add unops.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Add FP.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-zvfh-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-zvfh-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-zvfh-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-zvfh-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-zvfh-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-zvfh-run.c: New test.
+ * lib/target-supports.exp: Add riscv_vector_hw and riscv_zvfh_hw
+ target selectors.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: Ensure
+ that no sext insns are present.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: Dito.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: Dito.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: Dito.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-1.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-2.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-3.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-4.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-zvfh-run.c:
+ New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-run.c: New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-zvfh-run.c:
+ New test.
+ * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_extract-run.c: New file.
+
+2023-06-19 Robin Dapp <rdapp@ventanamicro.com>
+
+ * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Adapt for
+ (u)int8_t.
+ * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/shift-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vadd-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vand-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmax-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmin-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vmul-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vor-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vrem-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: Dito.
+ * gcc.target/riscv/rvv/autovec/binop/vxor-template.h: Dito.
+
+2023-06-19 Senthil Kumar Selvaraj <saaadhu@gcc.gnu.org>
+
+ PR target/110086
+ * gcc.target/avr/pr110086.c: New test.
+
+2023-06-19 Jiufu Guo <guojiufu@linux.ibm.com>
+
+ * gcc.target/powerpc/const_anchors.c: New test.
+ * gcc.target/powerpc/try_const_anchors_ice.c: New test.
+
+2023-06-19 liuhongt <hongtao.liu@intel.com>
+
+ * gcc.target/i386/avx512bw-vpackssdw-3.c: New test.
+ * gcc.target/i386/avx512bw-vpacksswb-3.c: New test.
+
2023-06-18 Jan Hubicka <jh@suse.cz>
* gcc.dg/lto/20091013-1_0.c: Disable stringop-overread warning.
projects / thirdparty / gcc.git / commitdiff
