arm64: dts: imx95-15x15-evk: fix the overshoot issue of NETC

[ Upstream commit e0322ac2a3cf7013b7af73b1293670f1e163c92e ]

The overshoot of MDIO, MDC, ENET1_TDx and ENET2_TDx is too high, so
reduce the drive strength of these pins.

Fixes: e3e8b199aff8 ("arm64: dts: imx95: Add imx95-15x15-evk support")
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
index 514f2429dcbc2754aad23456fc312bda5edd338f..3ab4d27de1a220430ce7c3e499b4a11b5a26431f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx95-15x15-evk.dts
@@ -558,17 +558,17 @@
 &scmi_iomuxc {
        pinctrl_emdio: emdiogrp {
                fsl,pins = <
-                       IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC               0x57e
-                       IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO             0x97e
+                       IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC               0x50e
+                       IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO             0x90e
                >;
        };
 
        pinctrl_enetc0: enetc0grp {
                fsl,pins = <
-                       IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3         0x57e
-                       IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2         0x57e
-                       IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1         0x57e
-                       IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0         0x57e
+                       IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3         0x50e
+                       IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2         0x50e
+                       IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1         0x50e
+                       IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0         0x50e
                        IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL   0x57e
                        IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK      0x58e
                        IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL   0x57e
@@ -582,10 +582,10 @@
 
        pinctrl_enetc1: enetc1grp {
                fsl,pins = <
-                       IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3         0x57e
-                       IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2         0x57e
-                       IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1         0x57e
-                       IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0         0x57e
+                       IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3         0x50e
+                       IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2         0x50e
+                       IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1         0x50e
+                       IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0         0x50e
                        IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL   0x57e
                        IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK      0x58e
                        IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL   0x57e