More amd64 back end bits and pieces.

git-svn-id: svn://svn.valgrind.org/vex/trunk@874

diff --git a/VEX/priv/host-amd64/hdefs.c b/VEX/priv/host-amd64/hdefs.c
index ed0bad52c3ee6cfeebeba09e09ce2aed397e20c8..00d1df7f7236ccc4033a8c25e8c3fe2a05fcdb3f 100644 (file)
--- a/VEX/priv/host-amd64/hdefs.c
+++ b/VEX/priv/host-amd64/hdefs.c
@@ -2298,7 +2298,8 @@ vassert(0);
       if (i->Ain.MulL.sz == 8) {
          switch (i->Ain.MulL.src->tag)  {
             case Arm_Mem:
-               vassert(0);
+               *p++ = rexAMode_M( fake(0),
+                                  i->Ain.MulL.src->Arm.Mem.am);
                *p++ = 0xF7;
                p = doAMode_M(p, fake(subopc),
                                 i->Ain.MulL.src->Arm.Mem.am);

diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c
index e2e6c6c17b91e94400df30cef4d187656a82fdb8..b12998f679f3e4b09355cb2ce1613313376de7a7 100644 (file)
--- a/VEX/priv/host-amd64/isel.c
+++ b/VEX/priv/host-amd64/isel.c
@@ -1092,16 +1092,16 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
 //..             return dst;
 //..          }
 //..          case Iop_8Sto16:
-//..          case Iop_8Sto32:
+         case Iop_8Sto32: {
 //..          case Iop_16Sto32: {
-//..             HReg dst = newVRegI(env);
-//..             HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
-//..             UInt amt = e->Iex.Unop.op==Iop_16Sto32 ? 16 : 24;
-//..             addInstr(env, mk_iMOVsd_RR(src,dst) );
-//..             addInstr(env, X86Instr_Sh32(Xsh_SHL, amt, X86RM_Reg(dst)));
-//..             addInstr(env, X86Instr_Sh32(Xsh_SAR, amt, X86RM_Reg(dst)));
-//..             return dst;
-//..          }
+            HReg dst = newVRegI(env);
+            HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
+            UInt amt = e->Iex.Unop.op==Iop_16Sto32 ? 48 : 56;
+            addInstr(env, mk_iMOVsd_RR(src,dst) );
+            addInstr(env, AMD64Instr_Sh64(Ash_SHL, amt, AMD64RM_Reg(dst)));
+            addInstr(env, AMD64Instr_Sh64(Ash_SAR, amt, AMD64RM_Reg(dst)));
+            return dst;
+         }
 //..    case Iop_Not8:
 //..    case Iop_Not16:
 //..          case Iop_Not32: {
@@ -1184,8 +1184,9 @@ static HReg iselIntExpr_R_wrk ( ISelEnv* env, IRExpr* e )
 //..          case Iop_16to8:
 //..          case Iop_32to8:
 //..          case Iop_32to16:
-//..             /* These are no-ops. */
-//..             return iselIntExpr_R(env, e->Iex.Unop.arg);
+         case Iop_64to32:
+            /* These are no-ops. */
+            return iselIntExpr_R(env, e->Iex.Unop.arg);
 
          default: 
             break;
@@ -1583,13 +1584,13 @@ static AMD64CondCode iselCondCode_wrk ( ISelEnv* env, IRExpr* e )
 //..       addInstr(env, X86Instr_Alu32R(Xalu_XOR,X86RMI_Reg(r),r));
 //..       return Xcc_Z;
 //..    }
-//.. 
-//..    /* Not1(...) */
-//..    if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) {
-//..       /* Generate code for the arg, and negate the test condition */
-//..       return 1 ^ iselCondCode(env, e->Iex.Unop.arg);
-//..    }
-//.. 
+
+   /* Not1(...) */
+   if (e->tag == Iex_Unop && e->Iex.Unop.op == Iop_Not1) {
+      /* Generate code for the arg, and negate the test condition */
+      return 1 ^ iselCondCode(env, e->Iex.Unop.arg);
+   }
+
 //..    /* 32to1(1Uto32(expr1)) -- the casts are pointless, ignore them */
 //..    DEFINE_PATTERN(p_1Uto32_then_32to1,
 //..                   unop(Iop_32to1,unop(Iop_1Uto32,bind(0))));