riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number

Since riscv and arm architecture use different interrupt definitions,
use a macro SOC_PERIPHERAL_IRQ mask this difference.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index d0a627c086fbd91dac4fa7cfde74e60b16476c26..88707cc13fb4dbaf81b68a659cd20d1822a02f91 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
  */
 
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
 #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
 #include "cv180x-cpus.dtsi"
 #include "cv180x.dtsi"

diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index 6668476178bbd74c68fff122414f72cc0288a0e4..ed06c3609fb2236c1e4c29f4b097adabd5d5fbff 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -38,7 +38,7 @@
                                reg = <0>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
 
@@ -56,7 +56,7 @@
                                reg = <0>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
 
@@ -74,7 +74,7 @@
                                reg = <0>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
 
@@ -92,7 +92,7 @@
                                reg = <0>;
                                interrupt-controller;
                                #interrupt-cells = <2>;
-                               interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>;
                        };
                };
 
@@ -100,7 +100,7 @@
                        compatible = "sophgo,cv1800b-saradc";
                        reg = <0x030f0000 0x1000>;
                        clocks = <&clk CLK_SARADC>;
-                       interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        status = "disabled";
@@ -125,7 +125,7 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
                        clock-names = "ref", "pclk";
-                       interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
@@ -136,7 +136,7 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
                        clock-names = "ref", "pclk";
-                       interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
@@ -147,7 +147,7 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
                        clock-names = "ref", "pclk";
-                       interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
@@ -158,7 +158,7 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
                        clock-names = "ref", "pclk";
-                       interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
@@ -169,14 +169,14 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
                        clock-names = "ref", "pclk";
-                       interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
                uart0: serial@4140000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x04140000 0x100>;
-                       interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
                        clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
@@ -187,7 +187,7 @@
                uart1: serial@4150000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x04150000 0x100>;
-                       interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
                        clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
@@ -198,7 +198,7 @@
                uart2: serial@4160000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x04160000 0x100>;
-                       interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
                        clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
@@ -209,7 +209,7 @@
                uart3: serial@4170000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x04170000 0x100>;
-                       interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
                        clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
@@ -224,7 +224,7 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
                        clock-names = "ssi_clk", "pclk";
-                       interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
@@ -235,7 +235,7 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
                        clock-names = "ssi_clk", "pclk";
-                       interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
@@ -246,7 +246,7 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
                        clock-names = "ssi_clk", "pclk";
-                       interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
@@ -257,14 +257,14 @@
                        #size-cells = <0>;
                        clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
                        clock-names = "ssi_clk", "pclk";
-                       interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
                        status = "disabled";
                };
 
                uart4: serial@41c0000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x041c0000 0x100>;
-                       interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
                        clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
@@ -275,7 +275,7 @@
                sdhci0: mmc@4310000 {
                        compatible = "sophgo,cv1800b-dwcmshc";
                        reg = <0x4310000 0x1000>;
-                       interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_AXI4_SD0>,
                                 <&clk CLK_SD0>;
                        clock-names = "core", "bus";
@@ -285,7 +285,7 @@
                sdhci1: mmc@4320000 {
                        compatible = "sophgo,cv1800b-dwcmshc";
                        reg = <0x4320000 0x1000>;
-                       interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_AXI4_SD1>,
                                 <&clk CLK_SD1>;
                        clock-names = "core", "bus";
@@ -295,7 +295,7 @@
                dmac: dma-controller@4330000 {
                        compatible = "snps,axi-dma-1.01a";
                        reg = <0x04330000 0x1000>;
-                       interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
                        clock-names = "core-clk", "cfgr-clk";
                        #dma-cells = <1>;

diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
index d9580a2e1e7f2a0f959b800f9b6a922b6f924eef..0974955e4e0537196c9a4dc1cc52c2eff61563a0 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
  */
 
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
 #include "cv180x-cpus.dtsi"

diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
index 5fd14dd1b14fcacceb51c21a50d4a4651f97a1b6..bbdb30653e9a2bba57fc0a840c837e020587bff3 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv181x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi
@@ -11,7 +11,7 @@
                emmc: mmc@4300000 {
                        compatible = "sophgo,cv1800b-dwcmshc";
                        reg = <0x4300000 0x1000>;
-                       interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(18) IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clk CLK_AXI4_EMMC>,
                                 <&clk CLK_EMMC>;
                        clock-names = "core", "bus";

diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
index 60709df12a223b4c65fb998b6cb278e5076bafd1..6f09c91991024625cf6a26796b4ef1b3b4364a7b 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
  */
 
+#define SOC_PERIPHERAL_IRQ(nr) ((nr) + 16)
+
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
 #include "cv180x-cpus.dtsi"