RISC-V: Remove unnecessary frm restore volatile define_insn

After we add the frm register to the global_regs, we may not need to
define_insn that volatile to emit the frm restore insns.  The
cooperatively-managed global register will help to handle this, instead
of emit the volatile define_insn explicitly.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_emit_frm_mode_set): Refactor
	the frm mode set by removing fsrmsi_restore_volatile.
	* config/riscv/vector-iterators.md (unspecv): Remove as
	unnecessary.
	* config/riscv/vector.md (fsrmsi_restore_volatile): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c: Adjust
	the asm dump check times.
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c: Ditto.
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c: Ditto.
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c: Ditto.
	* gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ed635ab42f40c8e77614635ba4e0c0682b17c3cc..10e0f4adbdcf59eee752f8b915c681c4d359ac53 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -12047,27 +12047,30 @@ riscv_emit_frm_mode_set (int mode, int prev_mode)
   if (prev_mode == riscv_vector::FRM_DYN_CALL)
     emit_insn (gen_frrmsi (backup_reg)); /* Backup frm when DYN_CALL.  */
 
-  if (mode != prev_mode)
-    {
-      rtx frm = gen_int_mode (mode, SImode);
-
-      if (mode == riscv_vector::FRM_DYN_CALL
-       && prev_mode != riscv_vector::FRM_DYN && STATIC_FRM_P (cfun))
-       /* No need to emit when prev mode is DYN already.  */
-       emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
-      else if (mode == riscv_vector::FRM_DYN_EXIT && STATIC_FRM_P (cfun)
-       && prev_mode != riscv_vector::FRM_DYN
-       && prev_mode != riscv_vector::FRM_DYN_CALL)
-       /* No need to emit when prev mode is DYN or DYN_CALL already.  */
-       emit_insn (gen_fsrmsi_restore_volatile (backup_reg));
-      else if (mode == riscv_vector::FRM_DYN
-       && prev_mode != riscv_vector::FRM_DYN_CALL)
-       /* Restore frm value from backup when switch to DYN mode.  */
-       emit_insn (gen_fsrmsi_restore (backup_reg));
-      else if (riscv_static_frm_mode_p (mode))
-       /* Set frm value when switch to static mode.  */
-       emit_insn (gen_fsrmsi_restore (frm));
+  if (mode == prev_mode)
+    return;
+
+  if (riscv_static_frm_mode_p (mode))
+    {
+      /* Set frm value when switch to static mode.  */
+      emit_insn (gen_fsrmsi_restore (gen_int_mode (mode, SImode)));
+      return;
     }
+
+  bool restore_p
+    = /* No need to emit when prev mode is DYN.  */
+      (STATIC_FRM_P (cfun) && mode == riscv_vector::FRM_DYN_CALL
+       && prev_mode != riscv_vector::FRM_DYN)
+      /* No need to emit if prev mode is DYN or DYN_CALL.  */
+      || (STATIC_FRM_P (cfun) && mode == riscv_vector::FRM_DYN_EXIT
+         && prev_mode != riscv_vector::FRM_DYN
+         && prev_mode != riscv_vector::FRM_DYN_CALL)
+      /* Restore frm value when switch to DYN mode.  */
+      || (mode == riscv_vector::FRM_DYN
+         && prev_mode != riscv_vector::FRM_DYN_CALL);
+
+  if (restore_p)
+    emit_insn (gen_fsrmsi_restore (backup_reg));
 }
 
 /* Implement Mode switching.  */

diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 5687e8a613c97c0ba00b60f7fbba9ef5b360a546..b4c869094f37d7e0c8697ac9418592de9c6dd0e6 100644 (file)
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -124,7 +124,6 @@
 ])
 
 (define_c_enum "unspecv" [
-  UNSPECV_FRM_RESTORE_EXIT
   UNSPECV_SF_CV
 ])
 

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 5191ae488083e9e17c664e6eba1af0e1c1b7a899..851ba4a9490a8d613ab2bb836bb4026ca7e3f1e2 100644 (file)
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1115,19 +1115,6 @@
    (set_attr "mode" "SI")]
  )
 
-;; The volatile fsrmsi restore is used for the exit point for the
-;; dynamic mode switching. It will generate one volatile fsrm a5
-;; which won't be eliminated.
-(define_insn "fsrmsi_restore_volatile"
-  [(set (reg:SI FRM_REGNUM)
-       (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
-                           UNSPECV_FRM_RESTORE_EXIT))]
-  "TARGET_VECTOR"
-  "fsrm\t%0"
-  [(set_attr "type" "wrfrm")
-   (set_attr "mode" "SI")]
-)
-
 ;; Read FRM
 (define_insn "frrmsi"
   [(set (match_operand:SI 0 "register_operand" "=r")

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
index af89f628657abbf2cad1d8185468a3bea9acbe0c..3e8a9808ba7eb7edc9ef396831465944faf972a2 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c
@@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
 /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */
 /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
 /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
index 5b75935554724670847abdd06eb782b183b36b1a..e8fc7bbd6c28c5780beb1f51ff00b2fff0323091 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c
@@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
 /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */
 /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
 /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
index cd23141e72ed97fc2902925015b7eb6fe1c0db9e..9828987d7d261ebc9864b50eb1506504c942b861 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c
@@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
 /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */
 /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
 /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c
index fb57803640cd5431755b9b1c644b102ca8142924..c8a580038ec9f879e37c2449ff9faf6f09b19930 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c
@@ -34,6 +34,6 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
 
 /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
 /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c
index 09067d3dce72ff20ec56de6efaba5f5c2c21a2e0..186f6c565c7d9f192ad45b74bf2c4052ec2ebb45 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c
@@ -34,6 +34,6 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2,
 
 /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */
 /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 1 } } */
-/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */
 /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */
 /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */