[AArch64] Suppress unnecessary FPSR and FPCR writes.

diff --git a/ChangeLog b/ChangeLog
index a638938fb09970fda3bf898bc266a13f09b3554e..0909d3be562a1975b6180062d56869aee7b77df9 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,18 @@
+2014-04-24  Ian Bolton  <ian.bolton@arm.com>
+
+       * sysdeps/aarch64/fpu/fclrexcpt.c (feclearexcept): Don't write to
+       fpsr if value didn't change.
+       * sysdeps/aarch64/fpu/fedisblxcpt.c (fedisableexcept): Don't write
+       to fpcr if value didn't change.
+       * sysdeps/aarch64/fpu/feenablxcpt.c (feenableexcept): Likewise.
+       * sysdeps/aarch64/fpu/feholdexcpt.c (feholdexcept): Don't write to
+       fpsr or fpcr if value didn't change.
+       * sysdeps/aarch64/fpu/fesetenv.c (fesetenv): Likewise.
+       * sysdeps/aarch64/fpu/fesetround.c (fesetround): Don't write to
+       fpcr if value didn't change.
+       * sysdeps/aarch64/fpu/fsetexcptflg.c (fesetexceptflag): Don't write
+       to fpsr if value didn't change.
+
 2014-02-23  Siddhesh Poyarekar  <siddhesh@redhat.com>
 
        * nptl/tst-sem3.c: Use test-skeleton.c

diff --git a/sysdeps/aarch64/fpu/fclrexcpt.c b/sysdeps/aarch64/fpu/fclrexcpt.c
index 531269f9cf790a2dd988511dccb85bf249c4f25d..b24f0ffbbc25577e89f403ab3b68716c85bbd3fe 100644 (file)
--- a/sysdeps/aarch64/fpu/fclrexcpt.c
+++ b/sysdeps/aarch64/fpu/fclrexcpt.c
@@ -23,13 +23,15 @@ int
 feclearexcept (int excepts)
 {
   fpu_fpsr_t fpsr;
+  fpu_fpsr_t fpsr_new;
 
   excepts &= FE_ALL_EXCEPT;
 
   _FPU_GETFPSR (fpsr);
-  fpsr = (fpsr & ~FE_ALL_EXCEPT) | (fpsr & FE_ALL_EXCEPT & ~excepts);
+  fpsr_new = (fpsr & ~FE_ALL_EXCEPT) | (fpsr & FE_ALL_EXCEPT & ~excepts);
 
-  _FPU_SETFPSR (fpsr);
+  if (fpsr != fpsr_new)
+    _FPU_SETFPSR (fpsr_new);
 
   return 0;
 }

diff --git a/sysdeps/aarch64/fpu/fedisblxcpt.c b/sysdeps/aarch64/fpu/fedisblxcpt.c
index 719d52f60a94f3e3acbf073c79ffe1185a1d6f8c..c43335c4e5dba289694af54000319574acc873ff 100644 (file)
--- a/sysdeps/aarch64/fpu/fedisblxcpt.c
+++ b/sysdeps/aarch64/fpu/fedisblxcpt.c
@@ -23,6 +23,7 @@ int
 fedisableexcept (int excepts)
 {
   fpu_control_t fpcr;
+  fpu_control_t fpcr_new;
   int original_excepts;
 
   _FPU_GETCW (fpcr);
@@ -31,9 +32,10 @@ fedisableexcept (int excepts)
 
   excepts &= FE_ALL_EXCEPT;
 
-  fpcr &= ~(excepts << FE_EXCEPT_SHIFT);
+  fpcr_new = fpcr & ~(excepts << FE_EXCEPT_SHIFT);
 
-  _FPU_SETCW (fpcr);
+  if (fpcr != fpcr_new)
+    _FPU_SETCW (fpcr_new);
 
   return original_excepts;
 }

diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
index 07a4bbb58ef13a112315269481c747a1e1cf5239..70e413c9f6ca2d95efbedc8f8d87bb57c5111a18 100644 (file)
--- a/sysdeps/aarch64/fpu/feenablxcpt.c
+++ b/sysdeps/aarch64/fpu/feenablxcpt.c
@@ -23,6 +23,7 @@ int
 feenableexcept (int excepts)
 {
   fpu_control_t fpcr;
+  fpu_control_t fpcr_new;
   int original_excepts;
 
   _FPU_GETCW (fpcr);
@@ -31,9 +32,10 @@ feenableexcept (int excepts)
 
   excepts &= FE_ALL_EXCEPT;
 
-  fpcr |= (excepts << FE_EXCEPT_SHIFT);
+  fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT);
 
-  _FPU_SETCW (fpcr);
+  if (fpcr != fpcr_new)
+    _FPU_SETCW (fpcr_new);
 
   /* Trapping exceptions are optional in AArch64 the relevant enable
      bits in FPCR are RES0 hence the absence of support can be

diff --git a/sysdeps/aarch64/fpu/feholdexcpt.c b/sysdeps/aarch64/fpu/feholdexcpt.c
index 0514ac15b56c6ca83a58130eef5440af06255715..973ba4a56a240c2cf8d37c114c3b0ff1e66b5f2e 100644 (file)
--- a/sysdeps/aarch64/fpu/feholdexcpt.c
+++ b/sysdeps/aarch64/fpu/feholdexcpt.c
@@ -22,8 +22,10 @@
 int
 feholdexcept (fenv_t *envp)
 {
-  fpu_fpsr_t fpsr;
   fpu_control_t fpcr;
+  fpu_control_t fpcr_new;
+  fpu_fpsr_t fpsr;
+  fpu_fpsr_t fpsr_new;
 
   _FPU_GETCW (fpcr);
   envp->__fpcr = fpcr;
@@ -32,14 +34,16 @@ feholdexcept (fenv_t *envp)
   envp->__fpsr = fpsr;
 
   /* Now set all exceptions to non-stop.  */
-  fpcr &= ~(FE_ALL_EXCEPT << FE_EXCEPT_SHIFT);
+  fpcr_new = fpcr & ~(FE_ALL_EXCEPT << FE_EXCEPT_SHIFT);
 
   /* And clear all exception flags.  */
-  fpsr &= ~FE_ALL_EXCEPT;
+  fpsr_new = fpsr & ~FE_ALL_EXCEPT;
 
-  _FPU_SETFPSR (fpsr);
+  if (fpsr != fpsr_new)
+    _FPU_SETFPSR (fpsr_new);
 
-  _FPU_SETCW (fpcr);
+  if (fpcr != fpcr_new)
+    _FPU_SETCW (fpcr_new);
 
   return 0;
 }

diff --git a/sysdeps/aarch64/fpu/fesetenv.c b/sysdeps/aarch64/fpu/fesetenv.c
index a2434e37b0614997e81ee67ac362d59f501644cc..30193e955ff02f41b38e319de815c64d354d5596 100644 (file)
--- a/sysdeps/aarch64/fpu/fesetenv.c
+++ b/sysdeps/aarch64/fpu/fesetenv.c
@@ -23,34 +23,38 @@ int
 fesetenv (const fenv_t *envp)
 {
   fpu_control_t fpcr;
-  fpu_fpsr_t fpsr;
+  fpu_control_t fpcr_new;
   fpu_control_t updated_fpcr;
+  fpu_fpsr_t fpsr;
+  fpu_fpsr_t fpsr_new;
 
   _FPU_GETCW (fpcr);
   _FPU_GETFPSR (fpsr);
 
-  fpcr &= _FPU_RESERVED;
-  fpsr &= _FPU_FPSR_RESERVED;
+  fpcr_new = fpcr & _FPU_RESERVED;
+  fpsr_new = fpsr & _FPU_FPSR_RESERVED;
 
   if (envp == FE_DFL_ENV)
     {
-      fpcr |= _FPU_DEFAULT;
-      fpsr |= _FPU_FPSR_DEFAULT;
+      fpcr_new |= _FPU_DEFAULT;
+      fpsr_new |= _FPU_FPSR_DEFAULT;
     }
   else if (envp == FE_NOMASK_ENV)
     {
-      fpcr |= _FPU_FPCR_IEEE;
-      fpsr |= _FPU_FPSR_IEEE;
+      fpcr_new |= _FPU_FPCR_IEEE;
+      fpsr_new |= _FPU_FPSR_IEEE;
     }
   else
     {
-      fpcr |= envp->__fpcr & ~_FPU_RESERVED;
-      fpsr |= envp->__fpsr & ~_FPU_FPSR_RESERVED;
+      fpcr_new |= envp->__fpcr & ~_FPU_RESERVED;
+      fpsr_new |= envp->__fpsr & ~_FPU_FPSR_RESERVED;
     }
 
-  _FPU_SETFPSR (fpsr);
+  if (fpsr != fpsr_new)
+    _FPU_SETFPSR (fpsr_new);
 
-  _FPU_SETCW (fpcr);
+  if (fpcr != fpcr_new)
+    _FPU_SETCW (fpcr_new);
 
   /* Trapping exceptions are optional in AArch64 the relevant enable
      bits in FPCR are RES0 hence the absence of support can be
@@ -58,7 +62,7 @@ fesetenv (const fenv_t *envp)
      value.  */
 
   _FPU_GETCW (updated_fpcr);
-  if ((updated_fpcr & fpcr) != fpcr)
+  if ((updated_fpcr & fpcr_new) != fpcr_new)
     return 1;
 
   return 0;

diff --git a/sysdeps/aarch64/fpu/fesetround.c b/sysdeps/aarch64/fpu/fesetround.c
index 40a05f65823f9e69cd8a20666713f1b5f51a36e4..225096ae7cd4ecefa63852ff676e46d991d81319 100644 (file)
--- a/sysdeps/aarch64/fpu/fesetround.c
+++ b/sysdeps/aarch64/fpu/fesetround.c
@@ -23,6 +23,7 @@ int
 fesetround (int round)
 {
   fpu_control_t fpcr;
+  fpu_control_t fpcr_new;
 
   switch (round)
     {
@@ -31,9 +32,10 @@ fesetround (int round)
     case FE_DOWNWARD:
     case FE_TOWARDZERO:
       _FPU_GETCW (fpcr);
-      fpcr = (fpcr & ~FE_TOWARDZERO) | round;
+      fpcr_new = (fpcr & ~FE_TOWARDZERO) | round;
 
-      _FPU_SETCW (fpcr);
+      if (fpcr != fpcr_new)
+       _FPU_SETCW (fpcr_new);
       return 0;
 
     default:

diff --git a/sysdeps/aarch64/fpu/fsetexcptflg.c b/sysdeps/aarch64/fpu/fsetexcptflg.c
index 49cd1e467fd7002d8a240385968d2da9558e4078..60bb1c9e96935f6c8a4aad6aa47e600feb75d0db 100644 (file)
--- a/sysdeps/aarch64/fpu/fsetexcptflg.c
+++ b/sysdeps/aarch64/fpu/fsetexcptflg.c
@@ -24,16 +24,18 @@ int
 fesetexceptflag (const fexcept_t *flagp, int excepts)
 {
   fpu_fpsr_t fpsr;
+  fpu_fpsr_t fpsr_new;
 
   /* Get the current environment.  */
   _FPU_GETFPSR (fpsr);
 
   /* Set the desired exception mask.  */
-  fpsr &= ~(excepts & FE_ALL_EXCEPT);
-  fpsr |= (*flagp & excepts & FE_ALL_EXCEPT);
+  fpsr_new = fpsr & ~(excepts & FE_ALL_EXCEPT);
+  fpsr_new |= (*flagp & excepts & FE_ALL_EXCEPT);
 
   /* Save state back to the FPU.  */
-  _FPU_SETFPSR (fpsr);
+  if (fpsr != fpsr_new)
+    _FPU_SETFPSR (fpsr_new);
 
   return 0;
 }