wifi: mt76: Move Q_READ/Q_WRITE definitions in dma.h

This is a preliminary patch to enable traffic forward offloading between
the MT76 NIC and the Airoha ethernet one via the Airoha NPU module
available on the Airoha EN7581 SoC.

Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20251017-mt76-npu-devel-v2-1-ddaa90901723@kernel.org
Signed-off-by: Felix Fietkau <nbd@nbd.name>

diff --git a/drivers/net/wireless/mediatek/mt76/dma.c b/drivers/net/wireless/mediatek/mt76/dma.c
index 27aa591ff2ea20b7bef717414f811fdf06e6cba3..2dd3bd990fbaf6b98f619be45ef4be0d5465293e 100644 (file)
--- a/drivers/net/wireless/mediatek/mt76/dma.c
+++ b/drivers/net/wireless/mediatek/mt76/dma.c
@@ -7,37 +7,6 @@
 #include "mt76.h"
 #include "dma.h"
 
-#if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
-
-#define Q_READ(_q, _field) ({                                          \
-       u32 _offset = offsetof(struct mt76_queue_regs, _field);         \
-       u32 _val;                                                       \
-       if ((_q)->flags & MT_QFLAG_WED)                                 \
-               _val = mtk_wed_device_reg_read((_q)->wed,               \
-                                              ((_q)->wed_regs +        \
-                                               _offset));              \
-       else                                                            \
-               _val = readl(&(_q)->regs->_field);                      \
-       _val;                                                           \
-})
-
-#define Q_WRITE(_q, _field, _val)      do {                            \
-       u32 _offset = offsetof(struct mt76_queue_regs, _field);         \
-       if ((_q)->flags & MT_QFLAG_WED)                                 \
-               mtk_wed_device_reg_write((_q)->wed,                     \
-                                        ((_q)->wed_regs + _offset),    \
-                                        _val);                         \
-       else                                                            \
-               writel(_val, &(_q)->regs->_field);                      \
-} while (0)
-
-#else
-
-#define Q_READ(_q, _field)             readl(&(_q)->regs->_field)
-#define Q_WRITE(_q, _field, _val)      writel(_val, &(_q)->regs->_field)
-
-#endif
-
 static struct mt76_txwi_cache *
 mt76_alloc_txwi(struct mt76_dev *dev)
 {

diff --git a/drivers/net/wireless/mediatek/mt76/dma.h b/drivers/net/wireless/mediatek/mt76/dma.h
index d41f978d4d7d3618bf4675b18245986d62fbd711..19bc768913fff30b221b2da4827dbc6aff5c9f3a 100644 (file)
--- a/drivers/net/wireless/mediatek/mt76/dma.h
+++ b/drivers/net/wireless/mediatek/mt76/dma.h
@@ -46,6 +46,37 @@
 #define MT_FCE_INFO_LEN                        4
 #define MT_RX_RXWI_LEN                 32
 
+#if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED)
+
+#define Q_READ(_q, _field) ({                                          \
+       u32 _offset = offsetof(struct mt76_queue_regs, _field);         \
+       u32 _val;                                                       \
+       if ((_q)->flags & MT_QFLAG_WED)                                 \
+               _val = mtk_wed_device_reg_read((_q)->wed,               \
+                                              ((_q)->wed_regs +        \
+                                               _offset));              \
+       else                                                            \
+               _val = readl(&(_q)->regs->_field);                      \
+       _val;                                                           \
+})
+
+#define Q_WRITE(_q, _field, _val)      do {                            \
+       u32 _offset = offsetof(struct mt76_queue_regs, _field);         \
+       if ((_q)->flags & MT_QFLAG_WED)                                 \
+               mtk_wed_device_reg_write((_q)->wed,                     \
+                                        ((_q)->wed_regs + _offset),    \
+                                        _val);                         \
+       else                                                            \
+               writel(_val, &(_q)->regs->_field);                      \
+} while (0)
+
+#else
+
+#define Q_READ(_q, _field)             readl(&(_q)->regs->_field)
+#define Q_WRITE(_q, _field, _val)      writel(_val, &(_q)->regs->_field)
+
+#endif
+
 struct mt76_desc {
        __le32 buf0;
        __le32 ctrl;