Fix avx512ne2ps2bf16 wrong code [PR 111127]

Correct the parameter order for avx512ne2ps2bf16_maskz expander

gcc/ChangeLog:

	PR target/111127
	* config/i386/sse.md (avx512f_cvtne2ps2bf16_<mode>_maskz):
	Adjust paramter order.

gcc/testsuite/ChangeLog:

	PR target/111127
	* gcc.target/i386/pr111127.c: New test.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 59a0eb1c63f32e64dec71ecc5d907ffe4cbb81fa..2b1f3516f9c8d92907abb333ae6d0705ffefa680 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -29955,8 +29955,8 @@
    (match_operand:<avx512fmaskmode> 3 "register_operand")]
   "TARGET_AVX512BF16"
 {
-  emit_insn (gen_avx512f_cvtne2ps2bf16_<mode>_mask(operands[0], operands[2],
-    operands[1], CONST0_RTX(<MODE>mode), operands[3]));
+  emit_insn (gen_avx512f_cvtne2ps2bf16_<mode>_mask(operands[0], operands[1],
+    operands[2], CONST0_RTX(<MODE>mode), operands[3]));
   DONE;
 })
 

diff --git a/gcc/testsuite/gcc.target/i386/pr111127.c b/gcc/testsuite/gcc.target/i386/pr111127.c
new file mode 100644 (file)
index 0000000..c124bc1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr111127.c
@@ -0,0 +1,24 @@
+/* PR target/111127 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mavx512bf16 -mavx512vl" } */
+/* { dg-final { scan-assembler-times "vcvtne2ps2bf16\[ \\t\]+\[^\{\n\]*%zmm1, %zmm0, %zmm0\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtne2ps2bf16\[ \\t\]+\[^\{\n\]*%ymm1, %ymm0, %ymm0\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vcvtne2ps2bf16\[ \\t\]+\[^\{\n\]*%xmm1, %xmm0, %xmm0\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+__m512bh cvttest(__mmask32 k, __m512 a, __m512 b)
+{
+  return _mm512_maskz_cvtne2ps_pbh (k,a,b);
+}
+
+__m256bh cvttest2(__mmask16 k, __m256 a, __m256 b)
+{
+  return _mm256_maskz_cvtne2ps_pbh (k,a,b);
+}
+
+__m128bh cvttest3(__mmask8 k, __m128 a, __m128 b)
+{
+  return _mm_maskz_cvtne2ps_pbh (k,a,b);
+}
+