PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1),
};
-static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt7623_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range),
PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
};
-static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt7629_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),
PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
};
-static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt7981_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),
PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
};
-static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt7986_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),
PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
};
-static const struct mtk_pin_reg_calc mt7987_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt7987_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range),
PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1),
};
-static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt7988_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),
PIN_FIELD_DRV(136, 144, 0x770, 24),
};
-static const struct mtk_pin_reg_calc mt8365_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt8365_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8365_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8365_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8365_pin_di_range),
PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4),
};
-static const struct mtk_pin_reg_calc mt8512_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt8512_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range),
PIN_FIELD(117, 120, 0xd70, 0x10, 0, 4),
};
-static const struct mtk_pin_reg_calc mt8516_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt8516_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range),
PIN_FIELD(116, 119, 0xd60, 0x10, 4, 4),
};
-static const struct mtk_pin_reg_calc mt8518_reg_cals[] = {
+static const struct mtk_pin_reg_calc mt8518_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8518_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8518_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8518_pin_di_range),