}
if (dc->soc->has_powergate)
- tegra_powergate_power_off(dc->powergate);
+ tegra_pmc_powergate_power_off(dc->pmc, dc->powergate);
clk_disable_unprepare(dc->clk);
pm_runtime_put_sync(dev);
}
if (dc->soc->has_powergate) {
- err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
- dc->rst);
+ err = tegra_pmc_powergate_sequence_power_up(dc->pmc,
+ dc->powergate,
+ dc->clk, dc->rst);
if (err < 0) {
dev_err(dev, "failed to power partition: %d\n", err);
goto put_rpm;
clk_disable_unprepare(dc->clk);
if (dc->soc->has_powergate) {
+ dc->pmc = devm_tegra_pmc_get(dc->dev);
+ if (IS_ERR(dc->pmc))
+ return dev_err_probe(dc->dev, PTR_ERR(dc->pmc),
+ "failed to get PMC\n");
+
if (dc->pipe == 0)
dc->powergate = TEGRA_POWERGATE_DIS;
else
dc->powergate = TEGRA_POWERGATE_DISB;
- tegra_powergate_power_off(dc->powergate);
+ tegra_pmc_powergate_power_off(dc->pmc, dc->powergate);
}
err = tegra_dc_init_opp_table(dc);
int irq;
struct tegra_output *rgb;
+ struct tegra_pmc *pmc;
struct tegra_dc_stats stats;
struct list_head list;
unsigned int nclocks;
struct reset_control_bulk_data resets[RST_GR3D_MAX];
unsigned int nresets;
+ struct tegra_pmc *pmc;
struct dev_pm_domain_list *pd_list;
DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
if (err) {
dev_err(dev, "failed to acquire %s reset: %d\n", name, err);
} else {
- err = tegra_powergate_sequence_power_up(id, clk, reset);
+ err = tegra_pmc_powergate_sequence_power_up(gr3d->pmc, id,
+ clk, reset);
reset_control_release(reset);
}
if (err != -ENOENT)
return err;
+ gr3d->pmc = devm_tegra_pmc_get(dev);
+ if (IS_ERR(gr3d->pmc))
+ return dev_err_probe(dev, PTR_ERR(gr3d->pmc),
+ "failed to get PMC\n");
+
/*
* Older device-trees don't use GENPD. In this case we should
* toggle power domain manually.
struct clk *clk_dp;
struct clk *clk;
+ struct tegra_pmc *pmc;
+
u8 xbar_cfg[5];
struct drm_dp_link link;
if (err < 0)
dev_err(sor->dev, "failed to power down SOR: %d\n", err);
- err = tegra_io_pad_power_disable(sor->pad);
+ err = tegra_pmc_io_pad_power_disable(sor->pmc, sor->pad);
if (err < 0)
dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
div = clk_get_rate(sor->clk) / 1000000 * 4;
- err = tegra_io_pad_power_enable(sor->pad);
+ err = tegra_pmc_io_pad_power_enable(sor->pmc, sor->pad);
if (err < 0)
dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
if (err < 0)
dev_err(sor->dev, "failed to power down SOR: %d\n", err);
- err = tegra_io_pad_power_disable(sor->pad);
+ err = tegra_pmc_io_pad_power_disable(sor->pmc, sor->pad);
if (err < 0)
dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
if (err < 0)
dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
- err = tegra_io_pad_power_enable(sor->pad);
+ err = tegra_pmc_io_pad_power_enable(sor->pmc, sor->pad);
if (err < 0)
dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
sor->num_settings = sor->soc->num_settings;
+ sor->pmc = devm_tegra_pmc_get(&pdev->dev);
+ if (IS_ERR(sor->pmc)) {
+ err = PTR_ERR(sor->pmc);
+ goto put_aux;
+ }
+
np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
if (np) {
sor->aux = drm_dp_aux_find_by_of_node(np);