clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flags

The GPU clocks/GDSCs have been marked critical from the clock driver
but the GPU driver votes on these resources as per the HW requirement.
In the case where these clocks & GDSCs are left enabled, would have
power impact and also cause GPU stability/corruptions.
Fix the same by removing the CLK_IS_CRITICAL for clocks and ALWAYS_ON
flags for the GPU GDSCs.

Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-4-adcc756a23df@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index ac7552b146c77978b81885f22f7af49ad0abe128..72920f537f77eec3fa3bc110c75e836a1f023865 100644 (file)
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2023, Linaro Limited
  */
 
@@ -280,7 +280,7 @@ static struct clk_branch gpu_cc_ahb_clk = {
                                &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -294,7 +294,6 @@ static struct clk_branch gpu_cc_cb_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data){
                        .name = "gpu_cc_cb_clk",
-                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -312,7 +311,7 @@ static struct clk_branch gpu_cc_crc_ahb_clk = {
                                &gpu_cc_hub_ahb_div_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -330,7 +329,7 @@ static struct clk_branch gpu_cc_cx_ff_clk = {
                                &gpu_cc_ff_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -348,7 +347,7 @@ static struct clk_branch gpu_cc_cx_gmu_clk = {
                                &gpu_cc_gmu_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags =  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags =  CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_aon_ops,
                },
        },
@@ -362,7 +361,6 @@ static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data){
                        .name = "gpu_cc_cx_snoc_dvm_clk",
-                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -380,7 +378,7 @@ static struct clk_branch gpu_cc_cxo_aon_clk = {
                                &gpu_cc_xo_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -398,7 +396,7 @@ static struct clk_branch gpu_cc_cxo_clk = {
                                &gpu_cc_xo_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags =  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags =  CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -416,7 +414,7 @@ static struct clk_branch gpu_cc_demet_clk = {
                                &gpu_cc_demet_div_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_aon_ops,
                },
        },
@@ -430,7 +428,6 @@ static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data){
                        .name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
-                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -448,7 +445,7 @@ static struct clk_branch gpu_cc_hub_aon_clk = {
                                &gpu_cc_hub_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_aon_ops,
                },
        },
@@ -466,7 +463,7 @@ static struct clk_branch gpu_cc_hub_cx_int_clk = {
                                &gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
                        },
                        .num_parents = 1,
-                       .flags =  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+                       .flags =  CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_aon_ops,
                },
        },
@@ -480,7 +477,6 @@ static struct clk_branch gpu_cc_memnoc_gfx_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data){
                        .name = "gpu_cc_memnoc_gfx_clk",
-                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -494,7 +490,6 @@ static struct clk_branch gpu_cc_sleep_clk = {
                .enable_mask = BIT(0),
                .hw.init = &(const struct clk_init_data){
                        .name = "gpu_cc_sleep_clk",
-                       .flags = CLK_IS_CRITICAL,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -533,7 +528,7 @@ static struct gdsc cx_gdsc = {
                .name = "cx_gdsc",
        },
        .pwrsts = PWRSTS_OFF_ON,
-       .flags = VOTABLE | RETAIN_FF_ENABLE | ALWAYS_ON,
+       .flags = VOTABLE | RETAIN_FF_ENABLE,
 };
 
 static struct gdsc gx_gdsc = {