RISC-V: Change vsetvl tail and mask policy to default policy

This patch change the vsetvl policy to default policy
(returned by get_prefer_mask_policy and get_prefer_tail_policy) instead
fixed policy. Any policy is now returned, allowing change to agnostic
or undisturbed. In the future, users may be able to control the default
policy, such as keeping agnostic by compiler options.

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (IS_AGNOSTIC): Move to here.
	* config/riscv/riscv-v.cc (gen_no_side_effects_vsetvl_rtx):
	Change to default policy.
	* config/riscv/riscv-vector-builtins-bases.cc: Change to default policy.
	* config/riscv/riscv-vsetvl.h (IS_AGNOSTIC): Delete.
	* config/riscv/riscv.cc (riscv_print_operand): Use IS_AGNOSTIC to test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/binop_vx_constraint-171.c: Adjust.
	* gcc.target/riscv/rvv/base/binop_vx_constraint-173.c: Adjust.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-24.c: New test.

diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 92e30a10f3c3a2178358e4451c90275fb9909804..e145ee6c69b303c7683d6b3bb473db95fcba976b 100644 (file)
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -406,6 +406,9 @@ enum mask_policy
   MASK_ANY = 2,
 };
 
+/* Return true if VALUE is agnostic or any policy.  */
+#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1))
+
 enum class reduction_type
 {
   UNORDERED,

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 427700192a343401c90febf3ed4ec1ee919da574..6228ff3d92e979b7fb0a5061781c2dbc344b4ce3 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1672,9 +1672,11 @@ static rtx
 gen_no_side_effects_vsetvl_rtx (machine_mode vmode, rtx vl, rtx avl)
 {
   unsigned int sew = get_sew (vmode);
+  rtx tail_policy = gen_int_mode (get_prefer_tail_policy (), Pmode);
+  rtx mask_policy = gen_int_mode (get_prefer_mask_policy (), Pmode);
   return gen_vsetvl_no_side_effects (Pmode, vl, avl, gen_int_mode (sew, Pmode),
                                     gen_int_mode (get_vlmul (vmode), Pmode),
-                                    const0_rtx, const0_rtx);
+                                    tail_policy, mask_policy);
 }
 
 /* GET VL * 2 rtx.  */

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 54582ee130c4eb87d1ea608270dd9c96cf0973f9..8e679f7239279b76927ac62b30e08ec53cf7fa24 100644 (file)
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -139,11 +139,11 @@ public:
     /* LMUL.  */
     e.add_input_operand (Pmode, gen_int_mode (get_vlmul (mode), Pmode));
 
-    /* TA.  */
-    e.add_input_operand (Pmode, gen_int_mode (1, Pmode));
+    /* TAIL_ANY.  */
+    e.add_input_operand (Pmode, gen_int_mode (get_prefer_tail_policy (), Pmode));
 
-    /* MU.  */
-    e.add_input_operand (Pmode, gen_int_mode (0, Pmode));
+    /* MASK_ANY.  */
+    e.add_input_operand (Pmode, gen_int_mode (get_prefer_mask_policy (), Pmode));
     return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode));
   }
 };

diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h
index 2a315e45f311464b35e4ed1ccdc61d5cfc59640a..53549abfac55016bce6f8054797eaf2e87b049f1 100644 (file)
--- a/gcc/config/riscv/riscv-vsetvl.h
+++ b/gcc/config/riscv/riscv-vsetvl.h
@@ -21,8 +21,6 @@ along with GCC; see the file COPYING3.  If not see
 #ifndef GCC_RISCV_VSETVL_H
 #define GCC_RISCV_VSETVL_H
 
-#define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1))
-
 namespace riscv_vector {
 
 /* Classification of vsetvl instruction.  */

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index d84fa2311faf8c022a932bb5d24b17087019ad10..8bca8075713e310bfd52a6ba5c03f5610664b2f2 100644 (file)
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5246,8 +5246,7 @@ riscv_print_operand (FILE *file, rtx op, int letter)
        else if (code == CONST_INT)
          {
            /* Tail && Mask policy.  */
-           bool agnostic_p = UINTVAL (op) & 0x1;
-           asm_fprintf (file, "%s", agnostic_p ? "a" : "u");
+           asm_fprintf (file, "%s", IS_AGNOSTIC (UINTVAL (op)) ? "a" : "u");
          }
        else
          output_operand_lossage ("invalid vector constant");

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
index dae5eff42ce10dac46d73ce6ab7b5031c469878d..6e8669ae59ec5532c42f037b50a28d17475ac4bf 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
@@ -7,7 +7,7 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au]
+**     vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au]
 **  ...
 **     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
 **  ...
@@ -41,7 +41,7 @@ void f1 (void * in, void *out, int64_t x, int n)
 /*
 ** f2:
 **  ...
-**     vsetivli\t[a-x0-9]+,\s*4,e64,m1,tu,m[au]
+**     vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au]
 **  ...
 **     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
 **  ...

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
index 0d5a2603856ab26332ab299740e6d59b3e7157b8..af9c45e942b499688bbbb7622bc8b3a1fa71c17d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
@@ -7,7 +7,7 @@
 /*
 ** f1:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au]
+**     vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au]
 **  ...
 **     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
 **  ...
@@ -41,7 +41,7 @@ void f1 (void * in, void *out, int64_t x, int vl)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,tu,m[au]
+**     vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au]
 **  ...
 **     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
 **  ...

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
new file mode 100644 (file)
index 0000000..1703c73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-24.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include <riscv_vector.h>
+
+size_t foo ()
+{
+    return __riscv_vsetvlmax_e8m1 ();
+}
+
+/* { dg-final { scan-assembler-times {\tvsetvli\t[a-x0-9]+,zero,e8,m1,ta,ma} 1 } } */