[testsuite] [ppc] expect vectorization in gen-vect-11c.c with lp64

The first loop in main gets stores "vectorized" on powerpc64 into
full-word stores, even without any vector instruction support, so the
test's expectation of no loop vectorization is not met.

for  gcc/testsuite/ChangeLog

	* gcc.dg/tree-ssa/gen-vect-11c.c: xfail the test for no
	vectorization on powerpc*-*-* && lp64.

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c
index 22ff44cf66da94ce97b993c6ef130f461b6eefc5..c0367ed29212b7a754f49279d24466d4efda8590 100644 (file)
--- a/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/gen-vect-11c.c
@@ -38,5 +38,6 @@ int main ()
   return 0;
 }
 
-
-/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail amdgcn*-*-* } } } */
+/* On power64, we vectorize pairs of ints into single non-vector registers.
+   That's not necessarily profitable, the costmodel may need adjustments.  */
+/* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { xfail { amdgcn*-*-* || { powerpc*-*-* && lp64 } } } } } */