clk: renesas: r9a09g056: Add clock and reset entries for USB2.0

Add clock and reset entries for USB2.0.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250528132558.167178-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 13b5db79aab47400a9f645fc4183a243a28720a8..e370ffb8c1e2325e861d75037891d23e779b0e78 100644 (file)
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -134,6 +134,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
        DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
                 CDDIV1_DIVCTL3, dtable_1_8),
        DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+       DEF_FIXED("usb2_0_clk_core0", R9A09G056_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1),
        DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G056_GBETH_0_CLK_PTP_REF_I,
                  CLK_PLLETH_DIV_125_FIX, 1, 1),
        DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G056_GBETH_1_CLK_PTP_REF_I,
@@ -219,6 +220,12 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
                                                BUS_MSTOP(8, BIT(4))),
        DEF_MOD("sdhi_2_aclk",                  CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
                                                BUS_MSTOP(8, BIT(4))),
+       DEF_MOD("usb2_0_u2h0_hclk",             CLK_PLLDTY_DIV8, 11, 3, 5, 19,
+                                               BUS_MSTOP(7, BIT(7))),
+       DEF_MOD("usb2_0_u2p_exr_cpuclk",        CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
+                                               BUS_MSTOP(7, BIT(9))),
+       DEF_MOD("usb2_0_pclk_usbtst0",          CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
+                                               BUS_MSTOP(7, BIT(10))),
        DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
                                                BUS_MSTOP(8, BIT(5)), 1),
        DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
@@ -280,6 +287,9 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
        DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
        DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
        DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */
+       DEF_RST(10, 12, 4, 29),         /* USB2_0_U2H0_HRESETN */
+       DEF_RST(10, 14, 4, 31),         /* USB2_0_U2P_EXL_SYSRST */
+       DEF_RST(10, 15, 5, 0),          /* USB2_0_PRESETN */
        DEF_RST(11, 0, 5, 1),           /* GBETH_0_ARESETN_I */
        DEF_RST(11, 1, 5, 2),           /* GBETH_1_ARESETN_I */
        DEF_RST(13, 13, 6, 14),         /* GPU_0_RESETN */