net: stmmac: qcom-ethqos: remove register field value obfuscations

Convert the register field values to something more human readable.

For example, using (BIT(29) | BIT(27)) to update a register field that
consists of bits 29:27 is an obfuscated way of writing decimal 5 for
this field. The comment above needs to explain that this value is 5.

Worse still is BIT(12) | GENMASK(9, 8), which is used to hide the
decimal value 19 for the bitfield 16:8.

Fix these, and a few others by using FIELD_PREP(). While it means we
have bare numeric constants, this is more preferable than having the
obfuscation.

Reviewed-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vuSKa-0000000ASbo-2zQg@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 690bd5c7e1a64fdd41e30e3b59447e9f2853718f..50b95fd19f9d69e706eddca5f863105f147e4cd9 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -361,10 +361,12 @@ static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
                              SDCC_HC_REG_DLL_CONFIG2);
 
                rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
-                             0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
+                             FIELD_PREP(SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 26),
+                             SDCC_HC_REG_DLL_CONFIG2);
 
                rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
-                             BIT(2), SDCC_HC_REG_DLL_CONFIG2);
+                             FIELD_PREP(SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
+                                        1), SDCC_HC_REG_DLL_CONFIG2);
 
                rgmii_setmask(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
                              SDCC_HC_REG_DLL_CONFIG2);
@@ -425,11 +427,13 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                if (ethqos->has_emac_ge_3) {
                        /* 0.9 ns */
                        rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
-                                     115, SDCC_HC_REG_DDR_CONFIG);
+                                     FIELD_PREP(SDCC_DDR_CONFIG_PRG_RCLK_DLY,
+                                                115), SDCC_HC_REG_DDR_CONFIG);
                } else {
                        /* 1.8 ns */
                        rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
-                                     57, SDCC_HC_REG_DDR_CONFIG);
+                                     FIELD_PREP(SDCC_DDR_CONFIG_PRG_RCLK_DLY,
+                                                57), SDCC_HC_REG_DDR_CONFIG);
                }
                rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
                              SDCC_HC_REG_DDR_CONFIG);
@@ -451,7 +455,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
                              phase_shift, RGMII_IO_MACRO_CONFIG2);
                rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
-                             BIT(6), RGMII_IO_MACRO_CONFIG);
+                             FIELD_PREP(RGMII_CONFIG_MAX_SPD_PRG_2, 1),
+                             RGMII_IO_MACRO_CONFIG);
                rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
                              RGMII_IO_MACRO_CONFIG2);
 
@@ -464,7 +469,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
 
                /* Write 0x5 to PRG_RCLK_DLY_CODE */
                rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
-                             (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
+                             FIELD_PREP(SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
+                                        5), SDCC_HC_REG_DDR_CONFIG);
                rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
                              SDCC_HC_REG_DDR_CONFIG);
                rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
@@ -487,7 +493,7 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
                              phase_shift, RGMII_IO_MACRO_CONFIG2);
                rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
-                             BIT(12) | GENMASK(9, 8),
+                             FIELD_PREP(RGMII_CONFIG_MAX_SPD_PRG_9, 19),
                              RGMII_IO_MACRO_CONFIG);
                rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
                              RGMII_IO_MACRO_CONFIG2);
@@ -499,7 +505,8 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                                      RGMII_IO_MACRO_CONFIG2);
                /* Write 0x5 to PRG_RCLK_DLY_CODE */
                rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
-                             (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
+                             FIELD_PREP(SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
+                                        5), SDCC_HC_REG_DDR_CONFIG);
                rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
                              SDCC_HC_REG_DDR_CONFIG);
                rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,