testsuite: arm: Use -mtune=cortex-m4 for thumb-ifcvt.c test

On Cortex-M4, the code generated is:
     cmp     r0, r1
     itte    ne
     lslne   r0, r0, r1
     asrne   r0, r0, #1
     moveq   r0, r1
     add     r0, r0, r1
     bx      lr

On Cortex-M7, the code generated is:
     cmp     r0, r1
     beq     .L3
     lsls    r0, r0, r1
     asrs    r0, r0, #1
     add     r0, r0, r1
     bx      lr
.L3:
     mov     r0, r1
     add     r0, r0, r1
     bx      lr

As Cortex-M7 only allow maximum one conditional instruction, force
Cortex-M4 to have a stable test case.

gcc/testsuite/ChangeLog:

	* gcc.target/arm/thumb-ifcvt.c: Use -mtune=cortex-m4.

Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>

diff --git a/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c b/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c
index 02e56f53b0d31b9e6ea1b1424f130ffe90d21e36..c7786faae7635f41be27e8ec3d8391091cc1c3a9 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c
+++ b/gcc/testsuite/gcc.target/arm/thumb-ifcvt.c
@@ -1,7 +1,7 @@
 /* Check that Thumb 16-bit shifts can be if-converted.  */
 /* { dg-do compile } */
 /* { dg-require-effective-target arm_thumb2_ok } */
-/* { dg-options "-O2 -mthumb -mno-restrict-it" } */
+/* { dg-options "-O2 -mthumb -mtune=cortex-m4 -mno-restrict-it" } */
 
 int
 foo (int a, int b)