arm64: dts: qcom: ipq5424: Add NSS clock controller node

NSS clock controller provides the clocks and resets to the networking
hardware blocks on the IPQ5424, such as PPE (Packet Process Engine) and
UNIPHY (PCS) blocks.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Link: https://lore.kernel.org/r/20251014-qcom_ipq5424_nsscc-v7-9-081f4956be02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
index e4a51eeefeac4fa145a6d7b144ca4114029aaf68..58e6852bebbc03739149511df0c96b2633218657 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
@@ -3,7 +3,7 @@
  * IPQ5424 device tree source
  *
  * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -820,6 +820,36 @@
                        #interconnect-cells = <1>;
                };
 
+               clock-controller@39b00000 {
+                       compatible = "qcom,ipq5424-nsscc";
+                       reg = <0 0x39b00000 0 0x100000>;
+                       clocks = <&cmn_pll IPQ5424_XO_24MHZ_CLK>,
+                                <&cmn_pll IPQ5424_NSS_300MHZ_CLK>,
+                                <&cmn_pll IPQ5424_PPE_375MHZ_CLK>,
+                                <&gcc GPLL0_OUT_AUX>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <&gcc GCC_NSSCC_CLK>;
+                       clock-names = "xo",
+                                     "nss",
+                                     "ppe",
+                                     "gpll0_out",
+                                     "uniphy0_rx",
+                                     "uniphy0_tx",
+                                     "uniphy1_rx",
+                                     "uniphy1_tx",
+                                     "uniphy2_rx",
+                                     "uniphy2_tx",
+                                     "bus";
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #interconnect-cells = <1>;
+               };
+
                pcie3: pcie@40000000 {
                        compatible = "qcom,pcie-ipq5424", "qcom,pcie-ipq9574";
                        reg = <0x0 0x40000000 0x0 0xf1c>,