switch (source) {
case CS530X_SYSCLK_SRC_MCLK:
- if (freq != 24560000 && freq != 22572000) {
- dev_err(component->dev, "Invalid MCLK source rate %d\n",
- freq);
+ switch (freq) {
+ case CS530X_SYSCLK_REF_45_1MHZ:
+ case CS530X_SYSCLK_REF_49_1MHZ:
+ break;
+ default:
+ dev_err(component->dev, "Invalid MCLK source rate %d\n", freq);
return -EINVAL;
}
break;
/* IN_VOL_CTL5 and OUT_VOL_CTL5 */
#define CS530X_INOUT_VU BIT(0)
+/* MCLK Reference Source Frequency */
+/* 41KHz related */
+#define CS530X_SYSCLK_REF_45_1MHZ 45158400
+/* 48KHz related */
+#define CS530X_SYSCLK_REF_49_1MHZ 49152000
+
/* System Clock Source */
#define CS530X_SYSCLK_SRC_MCLK 0
#define CS530X_SYSCLK_SRC_PLL 1