mips64: Change the initial value of fpu registers.

Initial value of mips fpu registers should be nan instead of 0xffffffffffffffff.

git-svn-id: svn://svn.valgrind.org/vex/trunk@2806

diff --git a/VEX/priv/guest_mips_helpers.c b/VEX/priv/guest_mips_helpers.c
index b8b25daab7e9589ef8cc90877da682e546ee87a3..9e47bc7f22e49989d64d754f8c15307a1a7c86ad 100644 (file)
--- a/VEX/priv/guest_mips_helpers.c
+++ b/VEX/priv/guest_mips_helpers.c
@@ -212,38 +212,38 @@ void LibVEX_GuestMIPS64_initialise ( /*OUT*/ VexGuestMIPS64State * vex_state )
    vex_state->guest_LO = 0;   /* Multiply and divide register lower result */
 
    /* FPU Registers */
-   vex_state->guest_f0 = 0xffffffffffffffffULL;  /* Floting point registers */
-   vex_state->guest_f1 = 0xffffffffffffffffULL;
-   vex_state->guest_f2 = 0xffffffffffffffffULL;
-   vex_state->guest_f3 = 0xffffffffffffffffULL;
-   vex_state->guest_f4 = 0xffffffffffffffffULL;
-   vex_state->guest_f5 = 0xffffffffffffffffULL;
-   vex_state->guest_f6 = 0xffffffffffffffffULL;
-   vex_state->guest_f7 = 0xffffffffffffffffULL;
-   vex_state->guest_f8 = 0xffffffffffffffffULL;
-   vex_state->guest_f9 = 0xffffffffffffffffULL;
-   vex_state->guest_f10 = 0xffffffffffffffffULL;
-   vex_state->guest_f11 = 0xffffffffffffffffULL;
-   vex_state->guest_f12 = 0xffffffffffffffffULL;
-   vex_state->guest_f13 = 0xffffffffffffffffULL;
-   vex_state->guest_f14 = 0xffffffffffffffffULL;
-   vex_state->guest_f15 = 0xffffffffffffffffULL;
-   vex_state->guest_f16 = 0xffffffffffffffffULL;
-   vex_state->guest_f17 = 0xffffffffffffffffULL;
-   vex_state->guest_f18 = 0xffffffffffffffffULL;
-   vex_state->guest_f19 = 0xffffffffffffffffULL;
-   vex_state->guest_f20 = 0xffffffffffffffffULL;
-   vex_state->guest_f21 = 0xffffffffffffffffULL;
-   vex_state->guest_f22 = 0xffffffffffffffffULL;
-   vex_state->guest_f23 = 0xffffffffffffffffULL;
-   vex_state->guest_f24 = 0xffffffffffffffffULL;
-   vex_state->guest_f25 = 0xffffffffffffffffULL;
-   vex_state->guest_f26 = 0xffffffffffffffffULL;
-   vex_state->guest_f27 = 0xffffffffffffffffULL;
-   vex_state->guest_f28 = 0xffffffffffffffffULL;
-   vex_state->guest_f29 = 0xffffffffffffffffULL;
-   vex_state->guest_f30 = 0xffffffffffffffffULL;
-   vex_state->guest_f31 = 0xffffffffffffffffULL;
+   vex_state->guest_f0 =  0x7ff800007ff80000ULL;  /* Floting point registers */
+   vex_state->guest_f1 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f2 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f3 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f4 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f5 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f6 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f7 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f8 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f9 =  0x7ff800007ff80000ULL;
+   vex_state->guest_f10 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f11 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f12 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f13 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f14 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f15 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f16 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f17 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f18 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f19 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f20 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f21 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f22 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f23 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f24 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f25 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f26 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f27 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f28 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f29 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f30 = 0x7ff800007ff80000ULL;
+   vex_state->guest_f31 = 0x7ff800007ff80000ULL;
 
    vex_state->guest_FIR = 0;   /* FP implementation and revision register */
    vex_state->guest_FCCR = 0;  /* FP condition codes register */