rs6000.md (*boolccsi3_internal1, [...]): Delete.

2014-08-17  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (*boolccsi3_internal1, *boolccsi3_internal2
	and split, *boolccsi3_internal3 and split): Delete.
	(*boolccdi3_internal1, *boolccdi3_internal2 and split,
	*boolccdi3_internal3 and split): Delete.
	(*boolcc<mode>3, *boolcc<mode>3_dot, *boolcc<mode>3_dot2): New.
	(*eqv<mode>3): Move.  Add TODO comment.  Fix attributes.

From-SVN: r214079

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b810dbf7cd23121241996d303d65524b31dc5cd0..bf1dfd68f47dc07b30197b1d676534ec08313fd6 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2014-08-17  Segher Boessenkool  <segher@kernel.crashing.org>
+
+       * config/rs6000/rs6000.md (*boolccsi3_internal1, *boolccsi3_internal2
+       and split, *boolccsi3_internal3 and split): Delete.
+       (*boolccdi3_internal1, *boolccdi3_internal2 and split,
+       *boolccdi3_internal3 and split): Delete.
+       (*boolcc<mode>3, *boolcc<mode>3_dot, *boolcc<mode>3_dot2): New.
+       (*eqv<mode>3): Move.  Add TODO comment.  Fix attributes.
+
 2014-08-17  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/rs6000.md (*boolcsi3_internal1, *boolcsi3_internal2

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 46f4f555d5461c13be25fe097993e8f2da06a99e..b6258310c7acf285fa9fa50fed8cd7478cf556d8 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3352,73 +3352,70 @@
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
-(define_insn "*boolccsi3_internal1"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-       (match_operator:SI 3 "boolean_operator"
-        [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-         (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
+
+(define_insn "*boolcc<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+       (match_operator:GPR 3 "boolean_operator"
+        [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))
+         (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r"))]))]
   ""
-  "%q3 %0,%1,%2")
+  "%q3 %0,%1,%2"
+  [(set_attr "type" "logical")])
 
-(define_insn "*boolccsi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-       (compare:CC (match_operator:SI 4 "boolean_operator"
-        [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
-         (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
+(define_insn_and_split "*boolcc<mode>3_dot"
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+       (compare:CC (match_operator:GPR 3 "boolean_operator"
+        [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
+         (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
         (const_int 0)))
-   (clobber (match_scratch:SI 3 "=r,r"))]
-  "TARGET_32BIT"
+   (clobber (match_scratch:GPR 0 "=r,r"))]
+  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
-   %q4. %3,%1,%2
+   %q3. %0,%1,%2
    #"
-  [(set_attr "type" "logical,compare")
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
+  [(set (match_dup 0)
+       (match_dup 3))
+   (set (match_dup 4)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  ""
+  [(set_attr "type" "logical")
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-       (compare:CC (match_operator:SI 4 "boolean_operator"
-        [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-         (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
-        (const_int 0)))
-   (clobber (match_scratch:SI 3 ""))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 0)
-       (compare:CC (match_dup 3)
-                   (const_int 0)))]
-  "")
-
-(define_insn "*boolccsi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-       (compare:CC (match_operator:SI 4 "boolean_operator"
-        [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
-         (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
+(define_insn_and_split "*boolcc<mode>3_dot2"
+  [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
+       (compare:CC (match_operator:GPR 3 "boolean_operator"
+        [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
+         (not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
         (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
-       (match_dup 4))]
-  "TARGET_32BIT"
+   (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
+       (match_dup 3))]
+  "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
   "@
-   %q4. %0,%1,%2
+   %q3. %0,%1,%2
    #"
-  [(set_attr "type" "logical,compare")
+  "&& reload_completed && cc_reg_not_cr0_operand (operands[4], CCmode)"
+  [(set (match_dup 0)
+       (match_dup 3))
+   (set (match_dup 4)
+       (compare:CC (match_dup 0)
+                   (const_int 0)))]
+  ""
+  [(set_attr "type" "logical")
    (set_attr "dot" "yes")
    (set_attr "length" "4,8")])
 
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-       (compare:CC (match_operator:SI 4 "boolean_operator"
-        [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
-         (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
-        (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "")
-       (match_dup 4))]
-  "TARGET_32BIT && reload_completed"
-  [(set (match_dup 0) (match_dup 4))
-   (set (match_dup 3)
-       (compare:CC (match_dup 0)
-                   (const_int 0)))]
-  "")
+
+;; TODO: Should have dots of this as well.
+(define_insn "*eqv<mode>3"
+  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+       (not:GPR (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
+                         (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
+  ""
+  "eqv %0,%1,%2"
+  [(set_attr "type" "logical")])
 \f
 ;; Rotate and shift insns, in all their variants.  These support shifts,
 ;; field inserts and extracts, and various combinations thereof.
@@ -7827,86 +7824,6 @@
 {
   build_mask64_2_operands (operands[2], &operands[5]);
 }")
-
-(define_insn "*boolccdi3_internal1"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
-       (match_operator:DI 3 "boolean_operator"
-        [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
-         (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
-  "TARGET_POWERPC64"
-  "%q3 %0,%1,%2")
-
-(define_insn "*boolccdi3_internal2"
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
-       (compare:CC (match_operator:DI 4 "boolean_operator"
-        [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
-         (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
-        (const_int 0)))
-   (clobber (match_scratch:DI 3 "=r,r"))]
-  "TARGET_64BIT"
-  "@
-   %q4. %3,%1,%2
-   #"
-  [(set_attr "type" "logical,compare")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
-       (compare:CC (match_operator:DI 4 "boolean_operator"
-        [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-         (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
-        (const_int 0)))
-   (clobber (match_scratch:DI 3 ""))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 3) (match_dup 4))
-   (set (match_dup 0)
-       (compare:CC (match_dup 3)
-                   (const_int 0)))]
-  "")
-
-(define_insn "*boolccdi3_internal3"
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
-       (compare:CC (match_operator:DI 4 "boolean_operator"
-        [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
-         (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
-        (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
-       (match_dup 4))]
-  "TARGET_64BIT"
-  "@
-   %q4. %0,%1,%2
-   #"
-  [(set_attr "type" "logical,compare")
-   (set_attr "dot" "yes")
-   (set_attr "length" "4,8")])
-
-(define_split
-  [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
-       (compare:CC (match_operator:DI 4 "boolean_operator"
-        [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
-         (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
-        (const_int 0)))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-       (match_dup 4))]
-  "TARGET_POWERPC64 && reload_completed"
-  [(set (match_dup 0) (match_dup 4))
-   (set (match_dup 3)
-       (compare:CC (match_dup 0)
-                   (const_int 0)))]
-  "")
-
-;; Eqv operation.
-(define_insn "*eqv<mode>3"
-  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
-       (not:GPR
-        (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
-                 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
-  ""
-  "eqv %0,%1,%2"
-  [(set_attr "type" "integer")
-   (set_attr "length" "4")])
-
 \f
 ;; 128-bit logical operations expanders