In order to access the protected IO power domain registers, a valid
unlock sequence must be performed by writing the required keys to the
AIB Secure Access Register (ASAR).
The ASAR register resides within the APBC register address space.
A corresponding syscon property is added to allow the pinctrl driver
to access this register.
Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
resets:
maxItems: 1
+ spacemit,apbc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to syscon that access the protected register
+
patternProperties:
'-cfg$':
type: object
clocks = <&syscon_apbc 42>,
<&syscon_apbc 94>;
clock-names = "func", "bus";
+ spacemit,apbc = <&syscon_apbc>;
uart0_2_cfg: uart0-2-cfg {
uart0-2-pins {