arm64: dts: qcom: sm8650: Add CAMSS device tree node

Add Qualcomm SM8650 CAMSS device tree node to the platform dtsi file,
the SM8650 CAMSS IP contains
* 6 x CSIPHY,
* 3 x CSID, 2 x CSID Lite,
* 3 x IFE, 2 x IFE Lite.

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20251204041505.131891-2-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 07ae74851621f2ec127735e6f1dd92164ffb8d4b..06eedd2cd7824eb6ae260b3ef48fa0a14f812ae6 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5380,6 +5380,193 @@
                        };
                };
 
+               camss: isp@acb6000 {
+                       compatible = "qcom,sm8650-camss";
+
+                       reg = <0 0x0acb6000 0 0x1000>,
+                             <0 0x0acb8000 0 0x1000>,
+                             <0 0x0acba000 0 0x1000>,
+                             <0 0x0acbc000 0 0x1000>,
+                             <0 0x0accb000 0 0x1000>,
+                             <0 0x0acd0000 0 0x1000>,
+                             <0 0x0ace4000 0 0x2000>,
+                             <0 0x0ace6000 0 0x2000>,
+                             <0 0x0ace8000 0 0x2000>,
+                             <0 0x0acea000 0 0x2000>,
+                             <0 0x0acec000 0 0x2000>,
+                             <0 0x0acee000 0 0x2000>,
+                             <0 0x0ac62000 0 0xf000>,
+                             <0 0x0ac71000 0 0xf000>,
+                             <0 0x0ac80000 0 0xf000>,
+                             <0 0x0accc000 0 0x2000>,
+                             <0 0x0acd1000 0 0x2000>;
+                       reg-names = "csid_wrapper",
+                                   "csid0",
+                                   "csid1",
+                                   "csid2",
+                                   "csid_lite0",
+                                   "csid_lite1",
+                                   "csiphy0",
+                                   "csiphy1",
+                                   "csiphy2",
+                                   "csiphy3",
+                                   "csiphy4",
+                                   "csiphy5",
+                                   "vfe0",
+                                   "vfe1",
+                                   "vfe2",
+                                   "vfe_lite0",
+                                   "vfe_lite1";
+
+                       clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+                                <&camcc CAM_CC_CPAS_AHB_CLK>,
+                                <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+                                <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+                                <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+                                <&camcc CAM_CC_CPAS_IFE_2_CLK>,
+                                <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+                                <&camcc CAM_CC_CSID_CLK>,
+                                <&camcc CAM_CC_CSIPHY0_CLK>,
+                                <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY1_CLK>,
+                                <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY2_CLK>,
+                                <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY3_CLK>,
+                                <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY4_CLK>,
+                                <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+                                <&camcc CAM_CC_CSIPHY5_CLK>,
+                                <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+                                <&gcc GCC_CAMERA_HF_AXI_CLK>,
+                                <&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
+                                <&camcc CAM_CC_IFE_0_CLK>,
+                                <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_1_CLK>,
+                                <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_2_CLK>,
+                                <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+                                <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+                       clock-names = "camnoc_axi",
+                                     "cpas_ahb",
+                                     "cpas_fast_ahb",
+                                     "cpas_vfe0",
+                                     "cpas_vfe1",
+                                     "cpas_vfe2",
+                                     "cpas_vfe_lite",
+                                     "csid",
+                                     "csiphy0",
+                                     "csiphy0_timer",
+                                     "csiphy1",
+                                     "csiphy1_timer",
+                                     "csiphy2",
+                                     "csiphy2_timer",
+                                     "csiphy3",
+                                     "csiphy3_timer",
+                                     "csiphy4",
+                                     "csiphy4_timer",
+                                     "csiphy5",
+                                     "csiphy5_timer",
+                                     "csiphy_rx",
+                                     "gcc_axi_hf",
+                                     "qdss_debug_xo",
+                                     "vfe0",
+                                     "vfe0_fast_ahb",
+                                     "vfe1",
+                                     "vfe1_fast_ahb",
+                                     "vfe2",
+                                     "vfe2_fast_ahb",
+                                     "vfe_lite",
+                                     "vfe_lite_ahb",
+                                     "vfe_lite_cphy_rx",
+                                     "vfe_lite_csid";
+
+                       interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 603 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 431 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 605 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 376 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 477 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 478 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 479 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 448 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 122 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 89 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 602 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 604 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 688 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 606 IRQ_TYPE_EDGE_RISING 0>,
+                                    <GIC_SPI 377 IRQ_TYPE_EDGE_RISING 0>;
+                       interrupt-names = "csid0",
+                                         "csid1",
+                                         "csid2",
+                                         "csid_lite0",
+                                         "csid_lite1",
+                                         "csiphy0",
+                                         "csiphy1",
+                                         "csiphy2",
+                                         "csiphy3",
+                                         "csiphy4",
+                                         "csiphy5",
+                                         "vfe0",
+                                         "vfe1",
+                                         "vfe2",
+                                         "vfe_lite0",
+                                         "vfe_lite1";
+
+                       interconnects = <&gem_noc MASTER_APPSS_PROC 0
+                                        &config_noc SLAVE_CAMERA_CFG 0>,
+                                       <&mmss_noc MASTER_CAMNOC_HF 0
+                                        &mc_virt SLAVE_EBI1 0>;
+                       interconnect-names = "ahb",
+                                            "hf_mnoc";
+
+                       iommus = <&apps_smmu 0x800 0x20>,
+                                <&apps_smmu 0x18a0 0x40>,
+                                <&apps_smmu 0x1860 0x00>;
+
+                       power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+                                       <&camcc CAM_CC_IFE_1_GDSC>,
+                                       <&camcc CAM_CC_IFE_2_GDSC>,
+                                       <&camcc CAM_CC_TITAN_TOP_GDSC>;
+                       power-domain-names = "ife0", "ife1", "ife2", "top";
+
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+
+                               port@2 {
+                                       reg = <2>;
+                               };
+
+                               port@3 {
+                                       reg = <3>;
+                               };
+
+                               port@4 {
+                                       reg = <4>;
+                               };
+
+                               port@5 {
+                                       reg = <5>;
+                               };
+                       };
+               };
+
                camcc: clock-controller@ade0000 {
                        compatible = "qcom,sm8650-camcc";
                        reg = <0 0x0ade0000 0 0x20000>;